Merge branch 'master' of git://git.denx.de/u-boot-arm

arch/arm/cpu/arm926ejs/orion5x/cpu.c

@@ -87,56 +87,56 @@ int orion5x_config_adr_windows(void)
 		(struct orion5x_win_registers *)ORION5X_CPU_WIN_BASE;
 
 	/* Window 0: PCIE MEM address space */
-	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCIE_MEM,
+	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_MEM,
 		ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_MEM,
 		ORION5X_WIN_ENABLE), &winregs[0].ctrl);
-	writel(ORION5X_DEFADR_PCIE_MEM, &winregs[0].base);
-	writel(ORION5X_DEFADR_PCIE_MEM_REMAP_LO, &winregs[0].remap_lo);
-	writel(ORION5X_DEFADR_PCIE_MEM_REMAP_HI, &winregs[0].remap_hi);
+	writel(ORION5X_ADR_PCIE_MEM, &winregs[0].base);
+	writel(ORION5X_ADR_PCIE_MEM_REMAP_LO, &winregs[0].remap_lo);
+	writel(ORION5X_ADR_PCIE_MEM_REMAP_HI, &winregs[0].remap_hi);
 
 	/* Window 1: PCIE IO address space */
-	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCIE_IO,
+	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_IO,
 		ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_IO,
 		ORION5X_WIN_ENABLE), &winregs[1].ctrl);
-	writel(ORION5X_DEFADR_PCIE_IO, &winregs[1].base);
-	writel(ORION5X_DEFADR_PCIE_IO_REMAP_LO, &winregs[1].remap_lo);
-	writel(ORION5X_DEFADR_PCIE_IO_REMAP_HI, &winregs[1].remap_hi);
+	writel(ORION5X_ADR_PCIE_IO, &winregs[1].base);
+	writel(ORION5X_ADR_PCIE_IO_REMAP_LO, &winregs[1].remap_lo);
+	writel(ORION5X_ADR_PCIE_IO_REMAP_HI, &winregs[1].remap_hi);
 
 	/* Window 2: PCI MEM address space */
-	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCI_MEM,
+	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_MEM,
 		ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_MEM,
 		ORION5X_WIN_ENABLE), &winregs[2].ctrl);
-	writel(ORION5X_DEFADR_PCI_MEM, &winregs[2].base);
+	writel(ORION5X_ADR_PCI_MEM, &winregs[2].base);
 
 	/* Window 3: PCI IO address space */
-	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCI_IO,
+	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_IO,
 		ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_IO,
 		ORION5X_WIN_ENABLE), &winregs[3].ctrl);
-	writel(ORION5X_DEFADR_PCI_IO, &winregs[3].base);
+	writel(ORION5X_ADR_PCI_IO, &winregs[3].base);
 
 	/* Window 4: DEV_CS0 address space */
-	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS0,
+	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS0,
 		ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS0,
 		ORION5X_WIN_ENABLE), &winregs[4].ctrl);
-	writel(ORION5X_DEFADR_DEV_CS0, &winregs[4].base);
+	writel(ORION5X_ADR_DEV_CS0, &winregs[4].base);
 
 	/* Window 5: DEV_CS1 address space */
-	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS1,
+	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS1,
 		ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS1,
 		ORION5X_WIN_ENABLE), &winregs[5].ctrl);
-	writel(ORION5X_DEFADR_DEV_CS1, &winregs[5].base);
+	writel(ORION5X_ADR_DEV_CS1, &winregs[5].base);
 
 	/* Window 6: DEV_CS2 address space */
-	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS2,
+	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS2,
 		ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS2,
 		ORION5X_WIN_ENABLE), &winregs[6].ctrl);
-	writel(ORION5X_DEFADR_DEV_CS2, &winregs[6].base);
+	writel(ORION5X_ADR_DEV_CS2, &winregs[6].base);
 
 	/* Window 7: BOOT Memory address space */
-	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_BOOTROM,
+	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM,
 		ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM,
 		ORION5X_WIN_ENABLE), &winregs[7].ctrl);
-	writel(ORION5X_DEFADR_BOOTROM, &winregs[7].base);
+	writel(ORION5X_ADR_BOOTROM, &winregs[7].base);
 
 	return 0;
 }

arch/arm/cpu/armv7/mx51/timer.c

@@ -89,7 +89,7 @@ ulong get_timer_masked(void)
 		timestamp += ((0xFFFFFFFF / (CONFIG_MX51_CLK32 / CONFIG_SYS_HZ))
 				- lastinc) + val;
 	lastinc = val;
-	return val;
+	return timestamp;
 }
 
 ulong get_timer(ulong base)

arch/arm/cpu/armv7/omap-common/timer.c

@@ -41,12 +41,8 @@ static struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
 
 /*
  * Nothing really to do with interrupts, just starts up a counter.
- * We run the counter with 13MHz, divided by 8, resulting in timer
- * frequency of 1.625MHz. With 32bit counter register, counter
- * overflows in ~44min
  */
 
-/* 13MHz / 8 = 1.625MHz */
 #define TIMER_CLOCK	(V_SCLK / (2 << CONFIG_SYS_PTV))
 #define TIMER_LOAD_VAL	0xffffffff
 
@@ -84,11 +80,6 @@ void set_timer(ulong t)
 /* delay x useconds */
 void __udelay(unsigned long usec)
 {
-#if defined(CONFIG_OMAP44XX)
-	/* TODO temporary hack until OMAP4 clock setup routines are present */
-	if (usec > 1000)
-		usec = usec/1000;
-#endif
 	long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
 	unsigned long now, last = readl(&timer_base->tcrr);
 

arch/arm/cpu/armv7/omap4/Makefile

@@ -28,6 +28,7 @@ LIB	=  $(obj)lib$(SOC).a
 SOBJS	+= lowlevel_init.o
 
 COBJS	+= board.o
+COBJS	+= mem.o
 COBJS	+= sys_info.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)

arch/arm/cpu/armv7/omap4/board.c

@@ -88,3 +88,14 @@ int checkboard(void)
 	return 0;
 }
 
+/*
+* This function is called by start_armboot. You can reliably use static
+* data. Any boot-time function that require static data should be
+* called from here
+*/
+int arch_cpu_init(void)
+{
+	set_muxconf_regs();
+	return 0;
+}
+

arch/arm/cpu/armv7/omap4/mem.c

@@ -0,0 +1,45 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Steve Sakoman <steve@sakoman.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/cpu.h>
+#include <asm/arch/sys_proto.h>
+
+struct gpmc *gpmc_cfg;
+
+/*****************************************************
+ * gpmc_init(): init gpmc bus
+ * This code can only be executed from SRAM or SDRAM.
+ *****************************************************/
+void gpmc_init(void)
+{
+	gpmc_cfg = (struct gpmc *)GPMC_BASE;
+
+	/* global settings */
+	writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */
+	writel(0, &gpmc_cfg->timeout_control);/* timeout disable */
+
+	/*
+	 * Disable the GPMC0 config set by ROM code
+	 * It conflicts with our MPDB (both at 0x08000000)
+	 */
+	writel(0, &gpmc_cfg->cs[0].config7);
+}

arch/arm/include/asm/arch-kirkwood/kirkwood.h

@@ -59,6 +59,11 @@
 #define KW_USB20_BASE			(KW_REGISTER(0x50000))
 #define KW_EGIGA0_BASE			(KW_REGISTER(0x72000))
 #define KW_EGIGA1_BASE			(KW_REGISTER(0x76000))
+#define KW_SATA_BASE			(KW_REGISTER(0x80000))
+
+/* Kirkwood Sata controller has two ports */
+#define KW_SATA_PORT0_OFFSET		0x2000
+#define KW_SATA_PORT1_OFFSET		0x4000
 
 /* Kirkwood GbE controller has two ports */
 #define MAX_MVGBE_DEVS	2

arch/arm/include/asm/arch-omap3/cpu.h

@@ -483,4 +483,7 @@ struct pm {
 #define I2C_BASE2		(OMAP34XX_CORE_L4_IO_BASE + 0x72000)
 #define I2C_BASE3		(OMAP34XX_CORE_L4_IO_BASE + 0x60000)
 
+/* MUSB base */
+#define MUSB_BASE		(OMAP34XX_CORE_L4_IO_BASE + 0xAB000)
+
 #endif /* _CPU_H */

arch/arm/include/asm/arch-omap3/i2c.h

@@ -34,7 +34,9 @@ struct i2c {
 	unsigned short stat;	/* 0x08 */
 	unsigned short res3;
 	unsigned short iv;	/* 0x0C */
-	unsigned short res4[3];
+	unsigned short res4;
+	unsigned short syss;	/* 0x10 */
+	unsigned short res4a;
 	unsigned short buf;	/* 0x14 */
 	unsigned short res5;
 	unsigned short cnt;	/* 0x18 */

arch/arm/include/asm/arch-omap4/cpu.h

@@ -31,6 +31,51 @@
 
 #ifndef __KERNEL_STRICT_NAMES
 #ifndef __ASSEMBLY__
+struct gpmc_cs {
+	u32 config1;		/* 0x00 */
+	u32 config2;		/* 0x04 */
+	u32 config3;		/* 0x08 */
+	u32 config4;		/* 0x0C */
+	u32 config5;		/* 0x10 */
+	u32 config6;		/* 0x14 */
+	u32 config7;		/* 0x18 */
+	u32 nand_cmd;		/* 0x1C */
+	u32 nand_adr;		/* 0x20 */
+	u32 nand_dat;		/* 0x24 */
+	u8 res[8];		/* blow up to 0x30 byte */
+};
+
+struct gpmc {
+	u8 res1[0x10];
+	u32 sysconfig;		/* 0x10 */
+	u8 res2[0x4];
+	u32 irqstatus;		/* 0x18 */
+	u32 irqenable;		/* 0x1C */
+	u8 res3[0x20];
+	u32 timeout_control;	/* 0x40 */
+	u8 res4[0xC];
+	u32 config;		/* 0x50 */
+	u32 status;		/* 0x54 */
+	u8 res5[0x8];	/* 0x58 */
+	struct gpmc_cs cs[8];	/* 0x60, 0x90, .. */
+	u8 res6[0x14];		/* 0x1E0 */
+	u32 ecc_config;		/* 0x1F4 */
+	u32 ecc_control;	/* 0x1F8 */
+	u32 ecc_size_config;	/* 0x1FC */
+	u32 ecc1_result;	/* 0x200 */
+	u32 ecc2_result;	/* 0x204 */
+	u32 ecc3_result;	/* 0x208 */
+	u32 ecc4_result;	/* 0x20C */
+	u32 ecc5_result;	/* 0x210 */
+	u32 ecc6_result;	/* 0x214 */
+	u32 ecc7_result;	/* 0x218 */
+	u32 ecc8_result;	/* 0x21C */
+	u32 ecc9_result;	/* 0x220 */
+};
+
+/* Used for board specific gpmc initialization */
+extern struct gpmc *gpmc_cfg;
+
 struct gptimer {
 	u32 tidr;		/* 0x00 r */
 	u8 res[0xc];
@@ -86,9 +131,15 @@ struct watchdog {
 #define TCLR_AR			(0x1 << 1)
 #define TCLR_PRE		(0x1 << 5)
 
+/* GPMC BASE */
+#define GPMC_BASE		(OMAP44XX_GPMC_BASE)
+
 /* I2C base */
 #define I2C_BASE1		(OMAP44XX_L4_PER_BASE + 0x70000)
 #define I2C_BASE2		(OMAP44XX_L4_PER_BASE + 0x72000)
 #define I2C_BASE3		(OMAP44XX_L4_PER_BASE + 0x60000)
 
+/* MUSB base */
+#define MUSB_BASE		(OMAP44XX_L4_CORE_BASE + 0xAB000)
+
 #endif /* _CPU_H */

arch/arm/include/asm/arch-omap4/mux_omap4.h

@@ -0,0 +1,344 @@
+/*
+ * (C) Copyright 2004-2009
+ * Texas Instruments Incorporated
+ * Richard Woodruff		<r-woodruff2@ti.com>
+ * Aneesh V			<aneesh@ti.com>
+ * Balaji Krishnamoorthy	<balajitk@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _MUX_OMAP4_H_
+#define _MUX_OMAP4_H_
+
+#include <asm/types.h>
+
+struct pad_conf_entry {
+
+	u16 offset;
+
+	u16 val;
+
+} __attribute__ ((packed));
+
+#ifdef CONFIG_OFF_PADCONF
+#define OFF_PD          (1 << 12)
+#define OFF_PU          (3 << 12)
+#define OFF_OUT_PTD     (0 << 10)
+#define OFF_OUT_PTU     (2 << 10)
+#define OFF_IN          (1 << 10)
+#define OFF_OUT         (0 << 10)
+#define OFF_EN          (1 << 9)
+#else
+#define OFF_PD          (0 << 12)
+#define OFF_PU          (0 << 12)
+#define OFF_OUT_PTD     (0 << 10)
+#define OFF_OUT_PTU     (0 << 10)
+#define OFF_IN          (0 << 10)
+#define OFF_OUT         (0 << 10)
+#define OFF_EN          (0 << 9)
+#endif
+
+#define IEN             (1 << 8)
+#define IDIS            (0 << 8)
+#define PTU             (3 << 3)
+#define PTD             (1 << 3)
+#define EN              (1 << 3)
+#define DIS             (0 << 3)
+
+#define M0              0
+#define M1              1
+#define M2              2
+#define M3              3
+#define M4              4
+#define M5              5
+#define M6              6
+#define M7              7
+
+#define SAFE_MODE	M7
+
+#ifdef CONFIG_OFF_PADCONF
+#define OFF_IN_PD       (OFF_PD | OFF_IN | OFF_EN)
+#define OFF_IN_PU       (OFF_PU | OFF_IN | OFF_EN)
+#define OFF_OUT_PD      (OFF_OUT_PTD | OFF_OUT | OFF_EN)
+#define OFF_OUT_PU      (OFF_OUT_PTU | OFF_OUT | OFF_EN)
+#else
+#define OFF_IN_PD       0
+#define OFF_IN_PU       0
+#define OFF_OUT_PD      0
+#define OFF_OUT_PU      0
+#endif
+
+#define CORE_REVISION		0x0000
+#define CORE_HWINFO		0x0004
+#define CORE_SYSCONFIG		0x0010
+#define GPMC_AD0		0x0040
+#define GPMC_AD1		0x0042
+#define GPMC_AD2		0x0044
+#define GPMC_AD3		0x0046
+#define GPMC_AD4		0x0048
+#define GPMC_AD5		0x004A
+#define GPMC_AD6		0x004C
+#define GPMC_AD7		0x004E
+#define GPMC_AD8		0x0050
+#define GPMC_AD9		0x0052
+#define GPMC_AD10		0x0054
+#define GPMC_AD11		0x0056
+#define GPMC_AD12		0x0058
+#define GPMC_AD13		0x005A
+#define GPMC_AD14		0x005C
+#define GPMC_AD15		0x005E
+#define GPMC_A16		0x0060
+#define GPMC_A17		0x0062
+#define GPMC_A18		0x0064
+#define GPMC_A19		0x0066
+#define GPMC_A20		0x0068
+#define GPMC_A21		0x006A
+#define GPMC_A22		0x006C
+#define GPMC_A23		0x006E
+#define GPMC_A24		0x0070
+#define GPMC_A25		0x0072
+#define GPMC_NCS0		0x0074
+#define GPMC_NCS1		0x0076
+#define GPMC_NCS2		0x0078
+#define GPMC_NCS3		0x007A
+#define GPMC_NWP		0x007C
+#define GPMC_CLK		0x007E
+#define GPMC_NADV_ALE		0x0080
+#define GPMC_NOE		0x0082
+#define GPMC_NWE		0x0084
+#define GPMC_NBE0_CLE		0x0086
+#define GPMC_NBE1		0x0088
+#define GPMC_WAIT0		0x008A
+#define GPMC_WAIT1		0x008C
+#define C2C_DATA11		0x008E
+#define C2C_DATA12		0x0090
+#define C2C_DATA13		0x0092
+#define C2C_DATA14		0x0094
+#define C2C_DATA15		0x0096
+#define HDMI_HPD		0x0098
+#define HDMI_CEC		0x009A
+#define HDMI_DDC_SCL		0x009C
+#define HDMI_DDC_SDA		0x009E
+#define CSI21_DX0		0x00A0
+#define CSI21_DY0		0x00A2
+#define CSI21_DX1		0x00A4
+#define CSI21_DY1		0x00A6
+#define CSI21_DX2		0x00A8
+#define CSI21_DY2		0x00AA
+#define CSI21_DX3		0x00AC
+#define CSI21_DY3		0x00AE
+#define CSI21_DX4		0x00B0
+#define CSI21_DY4		0x00B2
+#define CSI22_DX0		0x00B4
+#define CSI22_DY0		0x00B6
+#define CSI22_DX1		0x00B8
+#define CSI22_DY1		0x00BA
+#define CAM_SHUTTER		0x00BC
+#define CAM_STROBE		0x00BE
+#define CAM_GLOBALRESET		0x00C0
+#define USBB1_ULPITLL_CLK	0x00C2
+#define USBB1_ULPITLL_STP	0x00C4
+#define USBB1_ULPITLL_DIR	0x00C6
+#define USBB1_ULPITLL_NXT	0x00C8
+#define USBB1_ULPITLL_DAT0	0x00CA
+#define USBB1_ULPITLL_DAT1	0x00CC
+#define USBB1_ULPITLL_DAT2	0x00CE
+#define USBB1_ULPITLL_DAT3	0x00D0
+#define USBB1_ULPITLL_DAT4	0x00D2
+#define USBB1_ULPITLL_DAT5	0x00D4
+#define USBB1_ULPITLL_DAT6	0x00D6
+#define USBB1_ULPITLL_DAT7	0x00D8
+#define USBB1_HSIC_DATA		0x00DA
+#define USBB1_HSIC_STROBE	0x00DC
+#define USBC1_ICUSB_DP		0x00DE
+#define USBC1_ICUSB_DM		0x00E0
+#define SDMMC1_CLK		0x00E2
+#define SDMMC1_CMD		0x00E4
+#define SDMMC1_DAT0		0x00E6
+#define SDMMC1_DAT1		0x00E8
+#define SDMMC1_DAT2		0x00EA
+#define SDMMC1_DAT3		0x00EC
+#define SDMMC1_DAT4		0x00EE
+#define SDMMC1_DAT5		0x00F0
+#define SDMMC1_DAT6		0x00F2
+#define SDMMC1_DAT7		0x00F4
+#define ABE_MCBSP2_CLKX		0x00F6
+#define ABE_MCBSP2_DR		0x00F8
+#define ABE_MCBSP2_DX		0x00FA
+#define ABE_MCBSP2_FSX		0x00FC
+#define ABE_MCBSP1_CLKX		0x00FE
+#define ABE_MCBSP1_DR		0x0100
+#define ABE_MCBSP1_DX		0x0102
+#define ABE_MCBSP1_FSX		0x0104
+#define ABE_PDM_UL_DATA		0x0106
+#define ABE_PDM_DL_DATA		0x0108
+#define ABE_PDM_FRAME		0x010A
+#define ABE_PDM_LB_CLK		0x010C
+#define ABE_CLKS		0x010E
+#define ABE_DMIC_CLK1		0x0110
+#define ABE_DMIC_DIN1		0x0112
+#define ABE_DMIC_DIN2		0x0114
+#define ABE_DMIC_DIN3		0x0116
+#define UART2_CTS		0x0118
+#define UART2_RTS		0x011A
+#define UART2_RX		0x011C
+#define UART2_TX		0x011E
+#define HDQ_SIO			0x0120
+#define I2C1_SCL		0x0122
+#define I2C1_SDA		0x0124
+#define I2C2_SCL		0x0126
+#define I2C2_SDA		0x0128
+#define I2C3_SCL		0x012A
+#define I2C3_SDA		0x012C
+#define I2C4_SCL		0x012E
+#define I2C4_SDA		0x0130
+#define MCSPI1_CLK		0x0132
+#define MCSPI1_SOMI		0x0134
+#define MCSPI1_SIMO		0x0136
+#define MCSPI1_CS0		0x0138
+#define MCSPI1_CS1		0x013A
+#define MCSPI1_CS2		0x013C
+#define MCSPI1_CS3		0x013E
+#define UART3_CTS_RCTX		0x0140
+#define UART3_RTS_SD		0x0142
+#define UART3_RX_IRRX		0x0144
+#define UART3_TX_IRTX		0x0146
+#define SDMMC5_CLK		0x0148
+#define SDMMC5_CMD		0x014A
+#define SDMMC5_DAT0		0x014C
+#define SDMMC5_DAT1		0x014E
+#define SDMMC5_DAT2		0x0150
+#define SDMMC5_DAT3		0x0152
+#define MCSPI4_CLK		0x0154
+#define MCSPI4_SIMO		0x0156
+#define MCSPI4_SOMI		0x0158
+#define MCSPI4_CS0		0x015A
+#define UART4_RX		0x015C
+#define UART4_TX		0x015E
+#define USBB2_ULPITLL_CLK	0x0160
+#define USBB2_ULPITLL_STP	0x0162
+#define USBB2_ULPITLL_DIR	0x0164
+#define USBB2_ULPITLL_NXT	0x0166
+#define USBB2_ULPITLL_DAT0	0x0168
+#define USBB2_ULPITLL_DAT1	0x016A
+#define USBB2_ULPITLL_DAT2	0x016C
+#define USBB2_ULPITLL_DAT3	0x016E
+#define USBB2_ULPITLL_DAT4	0x0170
+#define USBB2_ULPITLL_DAT5	0x0172
+#define USBB2_ULPITLL_DAT6	0x0174
+#define USBB2_ULPITLL_DAT7	0x0176
+#define USBB2_HSIC_DATA		0x0178
+#define USBB2_HSIC_STROBE	0x017A
+#define UNIPRO_TX0		0x017C
+#define UNIPRO_TY0		0x017E
+#define UNIPRO_TX1		0x0180
+#define UNIPRO_TY1		0x0182
+#define UNIPRO_TX2		0x0184
+#define UNIPRO_TY2		0x0186
+#define UNIPRO_RX0		0x0188
+#define UNIPRO_RY0		0x018A
+#define UNIPRO_RX1		0x018C
+#define UNIPRO_RY1		0x018E
+#define UNIPRO_RX2		0x0190
+#define UNIPRO_RY2		0x0192
+#define USBA0_OTG_CE		0x0194
+#define USBA0_OTG_DP		0x0196
+#define USBA0_OTG_DM		0x0198
+#define FREF_CLK1_OUT		0x019A
+#define FREF_CLK2_OUT		0x019C
+#define SYS_NIRQ1		0x019E
+#define SYS_NIRQ2		0x01A0
+#define SYS_BOOT0		0x01A2
+#define SYS_BOOT1		0x01A4
+#define SYS_BOOT2		0x01A6
+#define SYS_BOOT3		0x01A8
+#define SYS_BOOT4		0x01AA
+#define SYS_BOOT5		0x01AC
+#define DPM_EMU0		0x01AE
+#define DPM_EMU1		0x01B0
+#define DPM_EMU2		0x01B2
+#define DPM_EMU3		0x01B4
+#define DPM_EMU4		0x01B6
+#define DPM_EMU5		0x01B8
+#define DPM_EMU6		0x01BA
+#define DPM_EMU7		0x01BC
+#define DPM_EMU8		0x01BE
+#define DPM_EMU9		0x01C0
+#define DPM_EMU10		0x01C2
+#define DPM_EMU11		0x01C4
+#define DPM_EMU12		0x01C6
+#define DPM_EMU13		0x01C8
+#define DPM_EMU14		0x01CA
+#define DPM_EMU15		0x01CC
+#define DPM_EMU16		0x01CE
+#define DPM_EMU17		0x01D0
+#define DPM_EMU18		0x01D2
+#define DPM_EMU19		0x01D4
+#define WAKEUPEVENT_0		0x01D8
+#define WAKEUPEVENT_1		0x01DC
+#define WAKEUPEVENT_2		0x01E0
+#define WAKEUPEVENT_3		0x01E4
+#define WAKEUPEVENT_4		0x01E8
+#define WAKEUPEVENT_5		0x01EC
+#define WAKEUPEVENT_6		0x01F0
+
+#define WKUP_REVISION		0x0000
+#define WKUP_HWINFO		0x0004
+#define WKUP_SYSCONFIG		0x0010
+#define PAD0_SIM_IO		0x0040
+#define PAD1_SIM_CLK		0x0042
+#define PAD0_SIM_RESET		0x0044
+#define PAD1_SIM_CD		0x0046
+#define PAD0_SIM_PWRCTRL		0x0048
+#define PAD1_SR_SCL		0x004A
+#define PAD0_SR_SDA		0x004C
+#define PAD1_FREF_XTAL_IN		0x004E
+#define PAD0_FREF_SLICER_IN	0x0050
+#define PAD1_FREF_CLK_IOREQ	0x0052
+#define PAD0_FREF_CLK0_OUT		0x0054
+#define PAD1_FREF_CLK3_REQ		0x0056
+#define PAD0_FREF_CLK3_OUT		0x0058
+#define PAD1_FREF_CLK4_REQ		0x005A
+#define PAD0_FREF_CLK4_OUT		0x005C
+#define PAD1_SYS_32K		0x005E
+#define PAD0_SYS_NRESPWRON		0x0060
+#define PAD1_SYS_NRESWARM		0x0062
+#define PAD0_SYS_PWR_REQ		0x0064
+#define PAD1_SYS_PWRON_RESET	0x0066
+#define PAD0_SYS_BOOT6		0x0068
+#define PAD1_SYS_BOOT7		0x006A
+#define PAD0_JTAG_NTRST		0x006C
+#define PAD1_JTAG_TCK		0x006D
+#define PAD0_JTAG_RTCK		0x0070
+#define PAD1_JTAG_TMS_TMSC		0x0072
+#define PAD0_JTAG_TDI		0x0074
+#define PAD1_JTAG_TDO		0x0076
+#define PADCONF_WAKEUPEVENT_0	0x007C
+#define CONTROL_SMART1NOPMIO_PADCONF_0		0x05A0
+#define CONTROL_SMART1NOPMIO_PADCONF_1		0x05A4
+#define PADCONF_MODE		0x05A8
+#define CONTROL_XTAL_OSCILLATOR			0x05AC
+#define CONTROL_CONTROL_I2C_2			0x0604
+#define CONTROL_CONTROL_JTAG			0x0608
+#define CONTROL_CONTROL_SYS			0x060C
+#define CONTROL_SPARE_RW		0x0614
+#define CONTROL_SPARE_R		0x0618
+#define CONTROL_SPARE_R_C0		0x061C
+
+#endif /* _MUX_OMAP4_H_ */

arch/arm/include/asm/arch-omap4/omap4.h

@@ -44,6 +44,8 @@
 
 /* CONTROL */
 #define CTRL_BASE		(OMAP44XX_L4_CORE_BASE + 0x2000)
+#define CONTROL_PADCONF_CORE	(OMAP44XX_L4_CORE_BASE + 0x100000)
+#define CONTROL_PADCONF_WKUP	(OMAP44XX_L4_CORE_BASE + 0x31E000)
 
 /* UART */
 #define UART1_BASE		(OMAP44XX_L4_PER_BASE + 0x6a000)
@@ -62,7 +64,7 @@
 #define SYNC_32KTIMER_BASE	(OMAP44XX_L4_WKUP_BASE + 0x4000)
 
 /* GPMC */
-#define GPMC_BASE	0x50000000
+#define OMAP44XX_GPMC_BASE	0x50000000
 
 /*
  * Hardware Register Details

arch/arm/include/asm/arch-omap4/sys_proto.h

@@ -28,9 +28,11 @@ struct omap_sysinfo {
 	char *board_string;
 };
 
+void gpmc_init(void);
 void watchdog_init(void);
 u32 get_device_type(void);
 void invalidate_dcache(u32);
+void set_muxconf_regs(void);
 
 extern const struct omap_sysinfo sysinfo;
 

arch/arm/include/asm/arch-orion5x/cpu.h

@@ -75,35 +75,91 @@ enum orion5x_cpu_attrib {
 };
 
 /*
- * Default Device Address MAP BAR values
+ * Device Address MAP BAR values
+/*
+ * All addresses and sizes not defined by board code
+ * will be given default values here.
  */
-#define ORION5X_DEFADR_PCIE_MEM	0x90000000
-#define ORION5X_DEFADR_PCIE_MEM_REMAP_LO	0x90000000
-#define ORION5X_DEFADR_PCIE_MEM_REMAP_HI	0
-#define ORION5X_DEFSZ_PCIE_MEM	(128*1024*1024)
 
-#define ORION5X_DEFADR_PCIE_IO	0xf0000000
-#define ORION5X_DEFADR_PCIE_IO_REMAP_LO	0x90000000
-#define ORION5X_DEFADR_PCIE_IO_REMAP_HI	0
-#define ORION5X_DEFSZ_PCIE_IO	(64*1024)
+#if !defined (ORION5X_ADR_PCIE_MEM)
+#define ORION5X_ADR_PCIE_MEM	0x90000000
+#endif
+
+#if !defined (ORION5X_ADR_PCIE_MEM_REMAP_LO)
+#define ORION5X_ADR_PCIE_MEM_REMAP_LO	0x90000000
+#endif
+
+#if !defined (ORION5X_ADR_PCIE_MEM_REMAP_HI)
+#define ORION5X_ADR_PCIE_MEM_REMAP_HI	0
+#endif
+
+#if !defined (ORION5X_SZ_PCIE_MEM)
+#define ORION5X_SZ_PCIE_MEM	(128*1024*1024)
+#endif
+
+#if !defined (ORION5X_ADR_PCIE_IO)
+#define ORION5X_ADR_PCIE_IO	0xf0000000
+#endif
+
+#if !defined (ORION5X_ADR_PCIE_IO_REMAP_LO)
+#define ORION5X_ADR_PCIE_IO_REMAP_LO	0x90000000
+#endif
+
+#if !defined (ORION5X_ADR_PCIE_IO_REMAP_HI)
+#define ORION5X_ADR_PCIE_IO_REMAP_HI	0
+#endif
+
+#if !defined (ORION5X_SZ_PCIE_IO)
+#define ORION5X_SZ_PCIE_IO	(64*1024)
+#endif
+
+#if !defined (ORION5X_ADR_PCI_MEM)
+#define ORION5X_ADR_PCI_MEM	0x98000000
+#endif
+
+#if !defined (ORION5X_SZ_PCI_MEM)
+#define ORION5X_SZ_PCI_MEM	(128*1024*1024)
+#endif
+
+#if !defined (ORION5X_ADR_PCI_IO)
+#define ORION5X_ADR_PCI_IO	0xf0100000
+#endif
+
+#if !defined (ORION5X_SZ_PCI_IO)
+#define ORION5X_SZ_PCI_IO	(64*1024)
+#endif
+
+#if !defined (ORION5X_ADR_DEV_CS0)
+#define ORION5X_ADR_DEV_CS0	0xfa000000
+#endif
+
+#if !defined (ORION5X_SZ_DEV_CS0)
+#define ORION5X_SZ_DEV_CS0	(2*1024*1024)
+#endif
 
-#define ORION5X_DEFADR_PCI_MEM	0x98000000
-#define ORION5X_DEFSZ_PCI_MEM	(128*1024*1024)
+#if !defined (ORION5X_ADR_DEV_CS1)
+#define ORION5X_ADR_DEV_CS1	0xf8000000
+#endif
 
-#define ORION5X_DEFADR_PCI_IO	0xf0100000
-#define ORION5X_DEFSZ_PCI_IO	(64*1024)
+#if !defined (ORION5X_SZ_DEV_CS1)
+#define ORION5X_SZ_DEV_CS1	(32*1024*1024)
+#endif
 
-#define ORION5X_DEFADR_DEV_CS0	0xfa000000
-#define ORION5X_DEFSZ_DEV_CS0	(2*1024*1024)
+#if !defined (ORION5X_ADR_DEV_CS2)
+#define ORION5X_ADR_DEV_CS2	0xfa800000
+#endif
 
-#define ORION5X_DEFADR_DEV_CS1	0xf8000000
-#define ORION5X_DEFSZ_DEV_CS1	(32*1024*1024)
+#if !defined (ORION5X_SZ_DEV_CS2)
+#define ORION5X_SZ_DEV_CS2	(1*1024*1024)
+#endif
 
-#define ORION5X_DEFADR_DEV_CS2	0xfa800000
-#define ORION5X_DEFSZ_DEV_CS2	(1*1024*1024)
+#if !defined (ORION5X_ADR_BOOTROM)
+#define ORION5X_ADR_BOOTROM	0xFFF80000
+#endif
 
-#define ORION5X_DEFADR_BOOTROM	0xFFF80000
-#define ORION5X_DEFSZ_BOOTROM	(512*1024)
+#if !defined (ORION5X_SZ_BOOTROM)
+#define ORION5X_SZ_BOOTROM	(512*1024)
+#endif
 
 /*
  * PCIE registers are used for SoC device ID and revision

arch/arm/include/asm/arch-orion5x/orion5x.h

@@ -55,6 +55,9 @@
 #define ORION5X_USB20_PORT0_BASE		(ORION5X_REGISTER(0x50000))
 #define ORION5X_USB20_PORT1_BASE		(ORION5X_REGISTER(0xA0000))
 #define ORION5X_EGIGA_BASE			(ORION5X_REGISTER(0x72000))
+#define ORION5X_SATA_BASE			(ORION5X_REGISTER(0x80000))
+#define ORION5X_SATA_PORT0_OFFSET		0x2000
+#define ORION5X_SATA_PORT1_OFFSET		0x4000
 
 /* Orion5x GbE controller has a single port */
 #define MAX_MVGBE_DEVS	1

arch/arm/include/asm/arch-s5pc1xx/cpu.h

@@ -38,6 +38,7 @@
 #define S5PC100_PWMTIMER_BASE	0xEA000000
 #define S5PC100_WATCHDOG_BASE	0xEA200000
 #define S5PC100_UART_BASE	0xEC000000
+#define S5PC100_MMC_BASE	0xED800000
 
 /* S5PC110 */
 #define S5PC110_GPIO_BASE	0xE0200000
@@ -45,6 +46,7 @@
 #define S5PC110_WATCHDOG_BASE	0xE2700000
 #define S5PC110_UART_BASE	0xE2900000
 #define S5PC110_SROMC_BASE	0xE8000000
+#define S5PC110_MMC_BASE	0xEB000000
 #define S5PC110_DMC0_BASE	0xF0000000
 #define S5PC110_DMC1_BASE	0xF1400000
 #define S5PC110_VIC0_BASE	0xF2000000

arch/arm/include/asm/arch-s5pc1xx/mmc.h

@@ -0,0 +1,71 @@
+/*
+ * (C) Copyright 2009 SAMSUNG Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __ASM_ARCH_MMC_H_
+#define __ASM_ARCH_MMC_H_
+
+#ifndef __ASSEMBLY__
+struct s5p_mmc {
+	unsigned int	sysad;
+	unsigned short	blksize;
+	unsigned short	blkcnt;
+	unsigned int	argument;
+	unsigned short	trnmod;
+	unsigned short	cmdreg;
+	unsigned int	rspreg0;
+	unsigned int	rspreg1;
+	unsigned int	rspreg2;
+	unsigned int	rspreg3;
+	unsigned int	bdata;
+	unsigned int	prnsts;
+	unsigned char	hostctl;
+	unsigned char	pwrcon;
+	unsigned char	blkgap;
+	unsigned char	wakcon;
+	unsigned short	clkcon;
+	unsigned char	timeoutcon;
+	unsigned char	swrst;
+	unsigned int	norintsts;	/* errintsts */
+	unsigned int	norintstsen;	/* errintstsen */
+	unsigned int	norintsigen;	/* errintsigen */
+	unsigned short	acmd12errsts;
+	unsigned char	res1[2];
+	unsigned int	capareg;
+	unsigned char	res2[4];
+	unsigned int	maxcurr;
+	unsigned char	res3[0x34];
+	unsigned int	control2;
+	unsigned int	control3;
+	unsigned int	control4;
+	unsigned char	res4[0x6e];
+	unsigned short	hcver;
+	unsigned char	res5[0xFFF00];
+};
+
+struct mmc_host {
+	struct s5p_mmc *reg;
+	unsigned int version;	/* SDHCI spec. version */
+	unsigned int clock;	/* Current clock (MHz) */
+};
+
+int s5p_mmc_init(int dev_index);
+
+#endif	/* __ASSEMBLY__ */
+#endif

arch/arm/include/asm/io.h

@@ -75,13 +75,47 @@ static inline phys_addr_t virt_to_phys(void * vaddr)
 #define __arch_putw(v,a)		(*(volatile unsigned short *)(a) = (v))
 #define __arch_putl(v,a)		(*(volatile unsigned int *)(a) = (v))
 
-extern void __raw_writesb(unsigned int addr, const void *data, int bytelen);
-extern void __raw_writesw(unsigned int addr, const void *data, int wordlen);
-extern void __raw_writesl(unsigned int addr, const void *data, int longlen);
+extern inline void __raw_writesb(unsigned int addr, const void *data, int bytelen)
+{
+	uint8_t *buf = (uint8_t *)data;
+	while(bytelen--)
+		__arch_putb(*buf++, addr);
+}
+
+extern inline void __raw_writesw(unsigned int addr, const void *data, int wordlen)
+{
+	uint16_t *buf = (uint16_t *)data;
+	while(wordlen--)
+		__arch_putw(*buf++, addr);
+}
+
+extern inline void __raw_writesl(unsigned int addr, const void *data, int longlen)
+{
+	uint32_t *buf = (uint32_t *)data;
+	while(longlen--)
+		__arch_putl(*buf++, addr);
+}
 
-extern void __raw_readsb(unsigned int addr, void *data, int bytelen);
-extern void __raw_readsw(unsigned int addr, void *data, int wordlen);
-extern void __raw_readsl(unsigned int addr, void *data, int longlen);
+extern inline void __raw_readsb(unsigned int addr, void *data, int bytelen)
+{
+	uint8_t *buf = (uint8_t *)data;
+	while(bytelen--)
+		*buf++ = __arch_getb(addr);
+}
+
+extern inline void __raw_readsw(unsigned int addr, void *data, int wordlen)
+{
+	uint16_t *buf = (uint16_t *)data;
+	while(wordlen--)
+		*buf++ = __arch_getw(addr);
+}
+
+extern inline void __raw_readsl(unsigned int addr, void *data, int longlen)
+{
+	uint32_t *buf = (uint32_t *)data;
+	while(longlen--)
+		*buf++ = __arch_getl(addr);
+}
 
 #define __raw_writeb(v,a)		__arch_putb(v,a)
 #define __raw_writew(v,a)		__arch_putw(v,a)

arch/powerpc/include/asm/config.h

@@ -95,4 +95,7 @@
 #define CONFIG_FSL_LBC
 #endif
 
+/* All PPC boards must swap IDE bytes */
+#define CONFIG_IDE_SWAP_IO
+
 #endif /* _ASM_CONFIG_H_ */

board/davinci/da8xxevm/da830evm.c

@@ -45,63 +45,63 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define pinmux	&davinci_syscfg_regs->pinmux
+#define pinmux(x)	(&davinci_syscfg_regs->pinmux[x])
 
 /* SPI0 pin muxer settings */
 static const struct pinmux_config spi0_pins[] = {
-	{ pinmux[7], 1, 3 },
-	{ pinmux[7], 1, 4 },
-	{ pinmux[7], 1, 5 },
-	{ pinmux[7], 1, 6 },
-	{ pinmux[7], 1, 7 }
+	{ pinmux(7), 1, 3 },
+	{ pinmux(7), 1, 4 },
+	{ pinmux(7), 1, 5 },
+	{ pinmux(7), 1, 6 },
+	{ pinmux(7), 1, 7 }
 };
 
 /* EMIF-A bus pins for 8-bit NAND support on CS3 */
 static const struct pinmux_config emifa_nand_pins[] = {
-	{ pinmux[13], 1, 6 },
-	{ pinmux[13], 1, 7 },
-	{ pinmux[14], 1, 0 },
-	{ pinmux[14], 1, 1 },
-	{ pinmux[14], 1, 2 },
-	{ pinmux[14], 1, 3 },
-	{ pinmux[14], 1, 4 },
-	{ pinmux[14], 1, 5 },
-	{ pinmux[15], 1, 7 },
-	{ pinmux[16], 1, 0 },
-	{ pinmux[18], 1, 1 },
-	{ pinmux[18], 1, 4 },
-	{ pinmux[18], 1, 5 },
+	{ pinmux(13), 1, 6 },
+	{ pinmux(13), 1, 7 },
+	{ pinmux(14), 1, 0 },
+	{ pinmux(14), 1, 1 },
+	{ pinmux(14), 1, 2 },
+	{ pinmux(14), 1, 3 },
+	{ pinmux(14), 1, 4 },
+	{ pinmux(14), 1, 5 },
+	{ pinmux(15), 1, 7 },
+	{ pinmux(16), 1, 0 },
+	{ pinmux(18), 1, 1 },
+	{ pinmux(18), 1, 4 },
+	{ pinmux(18), 1, 5 },
 };
 
 /* EMAC PHY interface pins */
 static const struct pinmux_config emac_pins[] = {
-	{ pinmux[9], 0, 5 },
-	{ pinmux[10], 2, 1 },
-	{ pinmux[10], 2, 2 },
-	{ pinmux[10], 2, 3 },
-	{ pinmux[10], 2, 4 },
-	{ pinmux[10], 2, 5 },
-	{ pinmux[10], 2, 6 },
-	{ pinmux[10], 2, 7 },
-	{ pinmux[11], 2, 0 },
-	{ pinmux[11], 2, 1 },
+	{ pinmux(9), 0, 5 },
+	{ pinmux(10), 2, 1 },
+	{ pinmux(10), 2, 2 },
+	{ pinmux(10), 2, 3 },
+	{ pinmux(10), 2, 4 },
+	{ pinmux(10), 2, 5 },
+	{ pinmux(10), 2, 6 },
+	{ pinmux(10), 2, 7 },
+	{ pinmux(11), 2, 0 },
+	{ pinmux(11), 2, 1 },
 };
 
 /* UART pin muxer settings */
 static const struct pinmux_config uart_pins[] = {
-	{ pinmux[8], 2, 7 },
-	{ pinmux[9], 2, 0 }
+	{ pinmux(8), 2, 7 },
+	{ pinmux(9), 2, 0 }
 };
 
 /* I2C pin muxer settings */
 static const struct pinmux_config i2c_pins[] = {
-	{ pinmux[8], 2, 3 },
-	{ pinmux[8], 2, 4 }
+	{ pinmux(8), 2, 3 },
+	{ pinmux(8), 2, 4 }
 };
 
 /* USB0_DRVVBUS pin muxer settings */
 static const struct pinmux_config usb_pins[] = {
-	{ pinmux[9], 1, 1 }
+	{ pinmux(9), 1, 1 }
 };
 
 static const struct pinmux_resource pinmuxes[] = {

board/davinci/da8xxevm/da850evm.c

@@ -30,28 +30,28 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define pinmux	(&davinci_syscfg_regs->pinmux)
+#define pinmux(x)	(&davinci_syscfg_regs->pinmux[x])
 
 /* SPI0 pin muxer settings */
 static const struct pinmux_config spi1_pins[] = {
-	{ pinmux[5], 1, 1 },
-	{ pinmux[5], 1, 2 },
-	{ pinmux[5], 1, 4 },
-	{ pinmux[5], 1, 5 }
+	{ pinmux(5), 1, 1 },
+	{ pinmux(5), 1, 2 },
+	{ pinmux(5), 1, 4 },
+	{ pinmux(5), 1, 5 }
 };
 
 /* UART pin muxer settings */
 static const struct pinmux_config uart_pins[] = {
-	{ pinmux[0], 4, 6 },
-	{ pinmux[0], 4, 7 },
-	{ pinmux[4], 2, 4 },
-	{ pinmux[4], 2, 5 }
+	{ pinmux(0), 4, 6 },
+	{ pinmux(0), 4, 7 },
+	{ pinmux(4), 2, 4 },
+	{ pinmux(4), 2, 5 }
 };
 
 /* I2C pin muxer settings */
 static const struct pinmux_config i2c_pins[] = {
-	{ pinmux[4], 2, 2 },
-	{ pinmux[4], 2, 3 }
+	{ pinmux(4), 2, 2 },
+	{ pinmux(4), 2, 3 }
 };
 
 static const struct pinmux_resource pinmuxes[] = {

board/samsung/goni/goni.c

@@ -23,11 +23,18 @@
  */
 
 #include <common.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static struct s5pc110_gpio *s5pc110_gpio;
+
 int board_init(void)
 {
+	/* Set Initial global variables */
+	s5pc110_gpio = (struct s5pc110_gpio *)S5PC110_GPIO_BASE;
+
 	gd->bd->bi_arch_number = MACH_TYPE_GONI;
 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 
@@ -53,3 +60,33 @@ int checkboard(void)
 	return 0;
 }
 #endif
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+	int i;
+
+	/* MASSMEMORY_EN: XMSMDATA7: GPJ2[7] output high */
+	gpio_direction_output(&s5pc110_gpio->gpio_j2, 7, 1);
+
+	/*
+	 * MMC0 GPIO
+	 * GPG0[0]	SD_0_CLK
+	 * GPG0[1]	SD_0_CMD
+	 * GPG0[2]	SD_0_CDn	-> Not used
+	 * GPG0[3:6]	SD_0_DATA[0:3]
+	 */
+	for (i = 0; i < 7; i++) {
+		if (i == 2)
+			continue;
+		/* GPG0[0:6] special function 2 */
+		gpio_cfg_pin(&s5pc110_gpio->gpio_g0, i, 0x2);
+		/* GPG0[0:6] pull disable */
+		gpio_set_pull(&s5pc110_gpio->gpio_g0, i, GPIO_PULL_NONE);
+		/* GPG0[0:6] drv 4x */
+		gpio_set_drv(&s5pc110_gpio->gpio_g0, i, GPIO_DRV_4X);
+	}
+
+	return s5p_mmc_init(0);
+}
+#endif

board/ti/panda/panda.c

@@ -24,6 +24,8 @@
 #include <common.h>
 #include <asm/arch/sys_proto.h>
 
+#include "panda.h"
+
 DECLARE_GLOBAL_DATA_PTR;
 
 const struct omap_sysinfo sysinfo = {
@@ -37,6 +39,8 @@ const struct omap_sysinfo sysinfo = {
  */
 int board_init(void)
 {
+	gpmc_init();
+
 	gd->bd->bi_arch_number = MACH_TYPE_OMAP4_PANDA;
 	gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
 
@@ -59,3 +63,27 @@ int misc_init_r(void)
 {
 	return 0;
 }
+
+void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
+{
+	int i;
+	struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
+
+	for (i = 0; i < size; i++, pad++)
+		writew(pad->val, base + pad->offset);
+}
+
+/**
+ * @brief set_muxconf_regs Setting up the configuration Mux registers
+ * specific to the board.
+ */
+void set_muxconf_regs(void)
+{
+	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array,
+		   sizeof(core_padconf_array) /
+		   sizeof(struct pad_conf_entry));
+
+	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array,
+		   sizeof(wkup_padconf_array) /
+		   sizeof(struct pad_conf_entry));
+}

board/ti/panda/panda.h

@@ -0,0 +1,265 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ *	Balaji Krishnamoorthy	<balajitk@ti.com>
+ *	Aneesh V		<aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _PANDA_H_
+#define _PANDA_H_
+
+#include <asm/io.h>
+#include <asm/arch/mux_omap4.h>
+
+const struct pad_conf_entry core_padconf_array[] = {
+	{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat0 */
+	{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, 	/* sdmmc2_dat1 */
+	{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat2 */
+	{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat3 */
+	{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat4 */
+	{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat5 */
+	{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat6 */
+	{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat7 */
+	{GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* gpio_32 */
+	{GPMC_AD9, (PTU | IEN | M3)},					/* gpio_33 */
+	{GPMC_AD10, (PTU | IEN | M3)},					/* gpio_34 */
+	{GPMC_AD11, (PTU | IEN | M3)},					/* gpio_35 */
+	{GPMC_AD12, (PTU | IEN | M3)},					/* gpio_36 */
+	{GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_37 */
+	{GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_38 */
+	{GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_39 */
+	{GPMC_A16, (M3)},						/* gpio_40 */
+	{GPMC_A17, (PTD | M3)},						/* gpio_41 */
+	{GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row6 */
+	{GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row7 */
+	{GPMC_A20, (IEN | M3)},						/* gpio_44 */
+	{GPMC_A21, (M3)},						/* gpio_45 */
+	{GPMC_A22, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col6 */
+	{GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col7 */
+	{GPMC_A24, (PTD | M3)},						/* gpio_48 */
+	{GPMC_A25, (PTD | M3)},						/* gpio_49 */
+	{GPMC_NCS0, (M3)},						/* gpio_50 */
+	{GPMC_NCS1, (IEN | M3)},					/* gpio_51 */
+	{GPMC_NCS2, (IEN | M3)},					/* gpio_52 */
+	{GPMC_NCS3, (IEN | M3)},					/* gpio_53 */
+	{GPMC_NWP, (M3)},						/* gpio_54 */
+	{GPMC_CLK, (PTD | M3)},						/* gpio_55 */
+	{GPMC_NADV_ALE, (M3)},						/* gpio_56 */
+	{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)},		/* sdmmc2_clk */
+	{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_cmd */
+	{GPMC_NBE0_CLE, (M3)},						/* gpio_59 */
+	{GPMC_NBE1, (PTD | M3)},					/* gpio_60 */
+	{GPMC_WAIT0, (PTU | IEN | M3)},					/* gpio_61 */
+	{GPMC_WAIT1, (IEN | M3)},					/* gpio_62 */
+	{C2C_DATA11, (PTD | M3)},					/* gpio_100 */
+	{C2C_DATA12, (M1)},						/* dsi1_te0 */
+	{C2C_DATA13, (PTD | M3)},					/* gpio_102 */
+	{C2C_DATA14, (M1)},						/* dsi2_te0 */
+	{C2C_DATA15, (PTD | M3)},					/* gpio_104 */
+	{HDMI_HPD, (M0)},						/* hdmi_hpd */
+	{HDMI_CEC, (M0)},						/* hdmi_cec */
+	{HDMI_DDC_SCL, (PTU | M0)},					/* hdmi_ddc_scl */
+	{HDMI_DDC_SDA, (PTU | IEN | M0)},				/* hdmi_ddc_sda */
+	{CSI21_DX0, (IEN | M0)},					/* csi21_dx0 */
+	{CSI21_DY0, (IEN | M0)},					/* csi21_dy0 */
+	{CSI21_DX1, (IEN | M0)},					/* csi21_dx1 */
+	{CSI21_DY1, (IEN | M0)},					/* csi21_dy1 */
+	{CSI21_DX2, (IEN | M0)},					/* csi21_dx2 */
+	{CSI21_DY2, (IEN | M0)},					/* csi21_dy2 */
+	{CSI21_DX3, (PTD | M7)},					/* csi21_dx3 */
+	{CSI21_DY3, (PTD | M7)},					/* csi21_dy3 */
+	{CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)},		/* csi21_dx4 */
+	{CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)},		/* csi21_dy4 */
+	{CSI22_DX0, (IEN | M0)},					/* csi22_dx0 */
+	{CSI22_DY0, (IEN | M0)},					/* csi22_dy0 */
+	{CSI22_DX1, (IEN | M0)},					/* csi22_dx1 */
+	{CSI22_DY1, (IEN | M0)},					/* csi22_dy1 */
+	{CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_shutter */
+	{CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_strobe */
+	{CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_83 */
+	{USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */
+	{USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)},		/* usbb1_ulpiphy_stp */
+	{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dir */
+	{USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_nxt */
+	{USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat0 */
+	{USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat1 */
+	{USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat2 */
+	{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat3 */
+	{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat4 */
+	{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat5 */
+	{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat6 */
+	{USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat7 */
+	{USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* usbb1_hsic_data */
+	{USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* usbb1_hsic_strobe */
+	{USBC1_ICUSB_DP, (IEN | M0)},					/* usbc1_icusb_dp */
+	{USBC1_ICUSB_DM, (IEN | M0)},					/* usbc1_icusb_dm */
+	{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)},		/* sdmmc1_clk */
+	{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_cmd */
+	{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat0 */
+	{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat1 */
+	{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat2 */
+	{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat3 */
+	{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat4 */
+	{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat5 */
+	{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat6 */
+	{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat7 */
+	{ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_clkx */
+	{ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp2_dr */
+	{ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp2_dx */
+	{ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_fsx */
+	{ABE_MCBSP1_CLKX, (IEN | M1)},					/* abe_slimbus1_clock */
+	{ABE_MCBSP1_DR, (IEN | M1)},					/* abe_slimbus1_data */
+	{ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp1_dx */
+	{ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_fsx */
+	{ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_ul_data */
+	{ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_dl_data */
+	{ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_frame */
+	{ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_lb_clk */
+	{ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_clks */
+	{ABE_DMIC_CLK1, (M0)},						/* abe_dmic_clk1 */
+	{ABE_DMIC_DIN1, (IEN | M0)},					/* abe_dmic_din1 */
+	{ABE_DMIC_DIN2, (IEN | M0)},					/* abe_dmic_din2 */
+	{ABE_DMIC_DIN3, (IEN | M0)},					/* abe_dmic_din3 */
+	{UART2_CTS, (PTU | IEN | M0)},					/* uart2_cts */
+	{UART2_RTS, (M0)},						/* uart2_rts */
+	{UART2_RX, (PTU | IEN | M0)},					/* uart2_rx */
+	{UART2_TX, (M0)},						/* uart2_tx */
+	{HDQ_SIO, (M3)},						/* gpio_127 */
+	{I2C1_SCL, (PTU | IEN | M0)},					/* i2c1_scl */
+	{I2C1_SDA, (PTU | IEN | M0)},					/* i2c1_sda */
+	{I2C2_SCL, (PTU | IEN | M0)},					/* i2c2_scl */
+	{I2C2_SDA, (PTU | IEN | M0)},					/* i2c2_sda */
+	{I2C3_SCL, (PTU | IEN | M0)},					/* i2c3_scl */
+	{I2C3_SDA, (PTU | IEN | M0)},					/* i2c3_sda */
+	{I2C4_SCL, (PTU | IEN | M0)},					/* i2c4_scl */
+	{I2C4_SDA, (PTU | IEN | M0)},					/* i2c4_sda */
+	{MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_clk */
+	{MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_somi */
+	{MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_simo */
+	{MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* mcspi1_cs0 */
+	{MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* mcspi1_cs1 */
+	{MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_139 */
+	{MCSPI1_CS3, (PTU | IEN | M3)},					/* gpio_140 */
+	{UART3_CTS_RCTX, (PTU | IEN | M0)},				/* uart3_tx */
+	{UART3_RTS_SD, (M0)},						/* uart3_rts_sd */
+	{UART3_RX_IRRX, (IEN | M0)},					/* uart3_rx */
+	{UART3_TX_IRTX, (M0)},						/* uart3_tx */
+	{SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* sdmmc5_clk */
+	{SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_cmd */
+	{SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat0 */
+	{SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat1 */
+	{SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat2 */
+	{SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat3 */
+	{MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi4_clk */
+	{MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi4_simo */
+	{MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi4_somi */
+	{MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* mcspi4_cs0 */
+	{UART4_RX, (IEN | M0)},						/* uart4_rx */
+	{UART4_TX, (M0)},						/* uart4_tx */
+	{USBB2_ULPITLL_CLK, (IEN | M3)},				/* gpio_157 */
+	{USBB2_ULPITLL_STP, (IEN | M5)},				/* dispc2_data23 */
+	{USBB2_ULPITLL_DIR, (IEN | M5)},				/* dispc2_data22 */
+	{USBB2_ULPITLL_NXT, (IEN | M5)},				/* dispc2_data21 */
+	{USBB2_ULPITLL_DAT0, (IEN | M5)},				/* dispc2_data20 */
+	{USBB2_ULPITLL_DAT1, (IEN | M5)},				/* dispc2_data19 */
+	{USBB2_ULPITLL_DAT2, (IEN | M5)},				/* dispc2_data18 */
+	{USBB2_ULPITLL_DAT3, (IEN | M5)},				/* dispc2_data15 */
+	{USBB2_ULPITLL_DAT4, (IEN | M5)},				/* dispc2_data14 */
+	{USBB2_ULPITLL_DAT5, (IEN | M5)},				/* dispc2_data13 */
+	{USBB2_ULPITLL_DAT6, (IEN | M5)},				/* dispc2_data12 */
+	{USBB2_ULPITLL_DAT7, (IEN | M5)},				/* dispc2_data11 */
+	{USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_169 */
+	{USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_170 */
+	{UNIPRO_TX0, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col0 */
+	{UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col1 */
+	{UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col2 */
+	{UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col3 */
+	{UNIPRO_TX2, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* gpio_0 */
+	{UNIPRO_TY2, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* gpio_1 */
+	{UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row0 */
+	{UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row1 */
+	{UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row2 */
+	{UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row3 */
+	{UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row4 */
+	{UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row5 */
+	{USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},	/* usba0_otg_ce */
+	{USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dp */
+	{USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dm */
+	{FREF_CLK1_OUT, (M0)},						/* fref_clk1_out */
+	{FREF_CLK2_OUT, (M0)},						/* fref_clk2_out */
+	{SYS_NIRQ1, (PTU | IEN | M0)},					/* sys_nirq1 */
+	{SYS_NIRQ2, (PTU | IEN | M0)},					/* sys_nirq2 */
+	{SYS_BOOT0, (PTU | IEN | M3)},					/* gpio_184 */
+	{SYS_BOOT1, (M3)},						/* gpio_185 */
+	{SYS_BOOT2, (PTD | IEN | M3)},					/* gpio_186 */
+	{SYS_BOOT3, (M3)},						/* gpio_187 */
+	{SYS_BOOT4, (M3)},						/* gpio_188 */
+	{SYS_BOOT5, (PTD | IEN | M3)},					/* gpio_189 */
+	{DPM_EMU0, (IEN | M0)},						/* dpm_emu0 */
+	{DPM_EMU1, (IEN | M0)},						/* dpm_emu1 */
+	{DPM_EMU2, (IEN | M0)},						/* dpm_emu2 */
+	{DPM_EMU3, (IEN | M5)},						/* dispc2_data10 */
+	{DPM_EMU4, (IEN | M5)},						/* dispc2_data9 */
+	{DPM_EMU5, (IEN | M5)},						/* dispc2_data16 */
+	{DPM_EMU6, (IEN | M5)},						/* dispc2_data17 */
+	{DPM_EMU7, (IEN | M5)},						/* dispc2_hsync */
+	{DPM_EMU8, (IEN | M5)},						/* dispc2_pclk */
+	{DPM_EMU9, (IEN | M5)},						/* dispc2_vsync */
+	{DPM_EMU10, (IEN | M5)},					/* dispc2_de */
+	{DPM_EMU11, (IEN | M5)},					/* dispc2_data8 */
+	{DPM_EMU12, (IEN | M5)},					/* dispc2_data7 */
+	{DPM_EMU13, (IEN | M5)},					/* dispc2_data6 */
+	{DPM_EMU14, (IEN | M5)},					/* dispc2_data5 */
+	{DPM_EMU15, (IEN | M5)},					/* dispc2_data4 */
+	{DPM_EMU16, (IEN | M5)},					/* dispc2_data3 */
+	{DPM_EMU17, (IEN | M5)},					/* dispc2_data2 */
+	{DPM_EMU18, (IEN | M5)},					/* dispc2_data1 */
+	{DPM_EMU19, (IEN | M5)},					/* dispc2_data0 */
+};
+
+const struct pad_conf_entry wkup_padconf_array[] = {
+	{PAD0_SIM_IO, (IEN | M0)},		/* sim_io */
+	{PAD1_SIM_CLK, (M0)},			/* sim_clk */
+	{PAD0_SIM_RESET, (M0)},			/* sim_reset */
+	{PAD1_SIM_CD, (PTU | IEN | M0)},	/* sim_cd */
+	{PAD0_SIM_PWRCTRL, (M0)},		/* sim_pwrctrl */
+	{PAD1_SR_SCL, (PTU | IEN | M0)},	/* sr_scl */
+	{PAD0_SR_SDA, (PTU | IEN | M0)},	/* sr_sda */
+	{PAD1_FREF_XTAL_IN, (M0)},		/* # */
+	{PAD0_FREF_SLICER_IN, (M0)},		/* fref_slicer_in */
+	{PAD1_FREF_CLK_IOREQ, (M0)},		/* fref_clk_ioreq */
+	{PAD0_FREF_CLK0_OUT, (M2)},		/* sys_drm_msecure */
+	{PAD1_FREF_CLK3_REQ, (PTU | IEN | M0)},	/* # */
+	{PAD0_FREF_CLK3_OUT, (M0)},		/* fref_clk3_out */
+	{PAD1_FREF_CLK4_REQ, (PTU | IEN | M0)},	/* # */
+	{PAD0_FREF_CLK4_OUT, (M0)},		/* # */
+	{PAD1_SYS_32K, (IEN | M0)},		/* sys_32k */
+	{PAD0_SYS_NRESPWRON, (M0)},		/* sys_nrespwron */
+	{PAD1_SYS_NRESWARM, (M0)},		/* sys_nreswarm */
+	{PAD0_SYS_PWR_REQ, (PTU | M0)},		/* sys_pwr_req */
+	{PAD1_SYS_PWRON_RESET, (M3)},		/* gpio_wk29 */
+	{PAD0_SYS_BOOT6, (IEN | M3)},		/* gpio_wk9 */
+	{PAD1_SYS_BOOT7, (IEN | M3)},		/* gpio_wk10 */
+};
+
+#endif
+

board/ti/sdp4430/sdp.c

@@ -25,6 +25,8 @@
 #include <common.h>
 #include <asm/arch/sys_proto.h>
 
+#include "sdp.h"
+
 DECLARE_GLOBAL_DATA_PTR;
 
 const struct omap_sysinfo sysinfo = {
@@ -38,6 +40,8 @@ const struct omap_sysinfo sysinfo = {
  */
 int board_init(void)
 {
+	gpmc_init();
+
 	gd->bd->bi_arch_number = MACH_TYPE_OMAP_4430SDP;
 	gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
 
@@ -60,3 +64,27 @@ int misc_init_r(void)
 {
 	return 0;
 }
+
+void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
+{
+	int i;
+	struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
+
+	for (i = 0; i < size; i++, pad++)
+		writew(pad->val, base + pad->offset);
+}
+
+/**
+ * @brief set_muxconf_regs Setting up the configuration Mux registers
+ * specific to the board.
+ */
+void set_muxconf_regs(void)
+{
+	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array,
+		   sizeof(core_padconf_array) /
+		   sizeof(struct pad_conf_entry));
+
+	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array,
+		   sizeof(wkup_padconf_array) /
+		   sizeof(struct pad_conf_entry));
+}

board/ti/sdp4430/sdp.h

@@ -0,0 +1,265 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ *	Balaji Krishnamoorthy	<balajitk@ti.com>
+ *	Aneesh V		<aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SDP_H_
+#define _SDP_H_
+
+#include <asm/io.h>
+#include <asm/arch/mux_omap4.h>
+
+const struct pad_conf_entry core_padconf_array[] = {
+	{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat0 */
+	{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, 	/* sdmmc2_dat1 */
+	{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat2 */
+	{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat3 */
+	{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat4 */
+	{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat5 */
+	{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat6 */
+	{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat7 */
+	{GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* gpio_32 */
+	{GPMC_AD9, (PTU | IEN | M3)},					/* gpio_33 */
+	{GPMC_AD10, (PTU | IEN | M3)},					/* gpio_34 */
+	{GPMC_AD11, (PTU | IEN | M3)},					/* gpio_35 */
+	{GPMC_AD12, (PTU | IEN | M3)},					/* gpio_36 */
+	{GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_37 */
+	{GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_38 */
+	{GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_39 */
+	{GPMC_A16, (M3)},						/* gpio_40 */
+	{GPMC_A17, (PTD | M3)},						/* gpio_41 */
+	{GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row6 */
+	{GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row7 */
+	{GPMC_A20, (IEN | M3)},						/* gpio_44 */
+	{GPMC_A21, (M3)},						/* gpio_45 */
+	{GPMC_A22, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col6 */
+	{GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col7 */
+	{GPMC_A24, (PTD | M3)},						/* gpio_48 */
+	{GPMC_A25, (PTD | M3)},						/* gpio_49 */
+	{GPMC_NCS0, (M3)},						/* gpio_50 */
+	{GPMC_NCS1, (IEN | M3)},					/* gpio_51 */
+	{GPMC_NCS2, (IEN | M3)},					/* gpio_52 */
+	{GPMC_NCS3, (IEN | M3)},					/* gpio_53 */
+	{GPMC_NWP, (M3)},						/* gpio_54 */
+	{GPMC_CLK, (PTD | M3)},						/* gpio_55 */
+	{GPMC_NADV_ALE, (M3)},						/* gpio_56 */
+	{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)},		/* sdmmc2_clk */
+	{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_cmd */
+	{GPMC_NBE0_CLE, (M3)},						/* gpio_59 */
+	{GPMC_NBE1, (PTD | M3)},					/* gpio_60 */
+	{GPMC_WAIT0, (PTU | IEN | M3)},					/* gpio_61 */
+	{GPMC_WAIT1, (IEN | M3)},					/* gpio_62 */
+	{C2C_DATA11, (PTD | M3)},					/* gpio_100 */
+	{C2C_DATA12, (M1)},						/* dsi1_te0 */
+	{C2C_DATA13, (PTD | M3)},					/* gpio_102 */
+	{C2C_DATA14, (M1)},						/* dsi2_te0 */
+	{C2C_DATA15, (PTD | M3)},					/* gpio_104 */
+	{HDMI_HPD, (M0)},						/* hdmi_hpd */
+	{HDMI_CEC, (M0)},						/* hdmi_cec */
+	{HDMI_DDC_SCL, (PTU | M0)},					/* hdmi_ddc_scl */
+	{HDMI_DDC_SDA, (PTU | IEN | M0)},				/* hdmi_ddc_sda */
+	{CSI21_DX0, (IEN | M0)},					/* csi21_dx0 */
+	{CSI21_DY0, (IEN | M0)},					/* csi21_dy0 */
+	{CSI21_DX1, (IEN | M0)},					/* csi21_dx1 */
+	{CSI21_DY1, (IEN | M0)},					/* csi21_dy1 */
+	{CSI21_DX2, (IEN | M0)},					/* csi21_dx2 */
+	{CSI21_DY2, (IEN | M0)},					/* csi21_dy2 */
+	{CSI21_DX3, (PTD | M7)},					/* csi21_dx3 */
+	{CSI21_DY3, (PTD | M7)},					/* csi21_dy3 */
+	{CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)},		/* csi21_dx4 */
+	{CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)},		/* csi21_dy4 */
+	{CSI22_DX0, (IEN | M0)},					/* csi22_dx0 */
+	{CSI22_DY0, (IEN | M0)},					/* csi22_dy0 */
+	{CSI22_DX1, (IEN | M0)},					/* csi22_dx1 */
+	{CSI22_DY1, (IEN | M0)},					/* csi22_dy1 */
+	{CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_shutter */
+	{CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_strobe */
+	{CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_83 */
+	{USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */
+	{USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)},		/* usbb1_ulpiphy_stp */
+	{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dir */
+	{USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_nxt */
+	{USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat0 */
+	{USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat1 */
+	{USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat2 */
+	{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat3 */
+	{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat4 */
+	{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat5 */
+	{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat6 */
+	{USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat7 */
+	{USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* usbb1_hsic_data */
+	{USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* usbb1_hsic_strobe */
+	{USBC1_ICUSB_DP, (IEN | M0)},					/* usbc1_icusb_dp */
+	{USBC1_ICUSB_DM, (IEN | M0)},					/* usbc1_icusb_dm */
+	{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)},		/* sdmmc1_clk */
+	{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_cmd */
+	{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat0 */
+	{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat1 */
+	{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat2 */
+	{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat3 */
+	{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat4 */
+	{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat5 */
+	{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat6 */
+	{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat7 */
+	{ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_clkx */
+	{ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp2_dr */
+	{ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp2_dx */
+	{ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_fsx */
+	{ABE_MCBSP1_CLKX, (IEN | M1)},					/* abe_slimbus1_clock */
+	{ABE_MCBSP1_DR, (IEN | M1)},					/* abe_slimbus1_data */
+	{ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp1_dx */
+	{ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_fsx */
+	{ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_ul_data */
+	{ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_dl_data */
+	{ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_frame */
+	{ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_lb_clk */
+	{ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_clks */
+	{ABE_DMIC_CLK1, (M0)},						/* abe_dmic_clk1 */
+	{ABE_DMIC_DIN1, (IEN | M0)},					/* abe_dmic_din1 */
+	{ABE_DMIC_DIN2, (IEN | M0)},					/* abe_dmic_din2 */
+	{ABE_DMIC_DIN3, (IEN | M0)},					/* abe_dmic_din3 */
+	{UART2_CTS, (PTU | IEN | M0)},					/* uart2_cts */
+	{UART2_RTS, (M0)},						/* uart2_rts */
+	{UART2_RX, (PTU | IEN | M0)},					/* uart2_rx */
+	{UART2_TX, (M0)},						/* uart2_tx */
+	{HDQ_SIO, (M3)},						/* gpio_127 */
+	{I2C1_SCL, (PTU | IEN | M0)},					/* i2c1_scl */
+	{I2C1_SDA, (PTU | IEN | M0)},					/* i2c1_sda */
+	{I2C2_SCL, (PTU | IEN | M0)},					/* i2c2_scl */
+	{I2C2_SDA, (PTU | IEN | M0)},					/* i2c2_sda */
+	{I2C3_SCL, (PTU | IEN | M0)},					/* i2c3_scl */
+	{I2C3_SDA, (PTU | IEN | M0)},					/* i2c3_sda */
+	{I2C4_SCL, (PTU | IEN | M0)},					/* i2c4_scl */
+	{I2C4_SDA, (PTU | IEN | M0)},					/* i2c4_sda */
+	{MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_clk */
+	{MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_somi */
+	{MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_simo */
+	{MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* mcspi1_cs0 */
+	{MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* mcspi1_cs1 */
+	{MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_139 */
+	{MCSPI1_CS3, (PTU | IEN | M3)},					/* gpio_140 */
+	{UART3_CTS_RCTX, (PTU | IEN | M0)},				/* uart3_tx */
+	{UART3_RTS_SD, (M0)},						/* uart3_rts_sd */
+	{UART3_RX_IRRX, (IEN | M0)},					/* uart3_rx */
+	{UART3_TX_IRTX, (M0)},						/* uart3_tx */
+	{SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* sdmmc5_clk */
+	{SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_cmd */
+	{SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat0 */
+	{SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat1 */
+	{SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat2 */
+	{SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat3 */
+	{MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi4_clk */
+	{MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi4_simo */
+	{MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi4_somi */
+	{MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* mcspi4_cs0 */
+	{UART4_RX, (IEN | M0)},						/* uart4_rx */
+	{UART4_TX, (M0)},						/* uart4_tx */
+	{USBB2_ULPITLL_CLK, (IEN | M3)},				/* gpio_157 */
+	{USBB2_ULPITLL_STP, (IEN | M5)},				/* dispc2_data23 */
+	{USBB2_ULPITLL_DIR, (IEN | M5)},				/* dispc2_data22 */
+	{USBB2_ULPITLL_NXT, (IEN | M5)},				/* dispc2_data21 */
+	{USBB2_ULPITLL_DAT0, (IEN | M5)},				/* dispc2_data20 */
+	{USBB2_ULPITLL_DAT1, (IEN | M5)},				/* dispc2_data19 */
+	{USBB2_ULPITLL_DAT2, (IEN | M5)},				/* dispc2_data18 */
+	{USBB2_ULPITLL_DAT3, (IEN | M5)},				/* dispc2_data15 */
+	{USBB2_ULPITLL_DAT4, (IEN | M5)},				/* dispc2_data14 */
+	{USBB2_ULPITLL_DAT5, (IEN | M5)},				/* dispc2_data13 */
+	{USBB2_ULPITLL_DAT6, (IEN | M5)},				/* dispc2_data12 */
+	{USBB2_ULPITLL_DAT7, (IEN | M5)},				/* dispc2_data11 */
+	{USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_169 */
+	{USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_170 */
+	{UNIPRO_TX0, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col0 */
+	{UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col1 */
+	{UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col2 */
+	{UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col3 */
+	{UNIPRO_TX2, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col4 */
+	{UNIPRO_TY2, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col5 */
+	{UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row0 */
+	{UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row1 */
+	{UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row2 */
+	{UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row3 */
+	{UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row4 */
+	{UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row5 */
+	{USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},	/* usba0_otg_ce */
+	{USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dp */
+	{USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dm */
+	{FREF_CLK1_OUT, (M0)},						/* fref_clk1_out */
+	{FREF_CLK2_OUT, (M0)},						/* fref_clk2_out */
+	{SYS_NIRQ1, (PTU | IEN | M0)},					/* sys_nirq1 */
+	{SYS_NIRQ2, (PTU | IEN | M0)},					/* sys_nirq2 */
+	{SYS_BOOT0, (PTU | IEN | M3)},					/* gpio_184 */
+	{SYS_BOOT1, (M3)},						/* gpio_185 */
+	{SYS_BOOT2, (PTD | IEN | M3)},					/* gpio_186 */
+	{SYS_BOOT3, (M3)},						/* gpio_187 */
+	{SYS_BOOT4, (M3)},						/* gpio_188 */
+	{SYS_BOOT5, (PTD | IEN | M3)},					/* gpio_189 */
+	{DPM_EMU0, (IEN | M0)},						/* dpm_emu0 */
+	{DPM_EMU1, (IEN | M0)},						/* dpm_emu1 */
+	{DPM_EMU2, (IEN | M0)},						/* dpm_emu2 */
+	{DPM_EMU3, (IEN | M5)},						/* dispc2_data10 */
+	{DPM_EMU4, (IEN | M5)},						/* dispc2_data9 */
+	{DPM_EMU5, (IEN | M5)},						/* dispc2_data16 */
+	{DPM_EMU6, (IEN | M5)},						/* dispc2_data17 */
+	{DPM_EMU7, (IEN | M5)},						/* dispc2_hsync */
+	{DPM_EMU8, (IEN | M5)},						/* dispc2_pclk */
+	{DPM_EMU9, (IEN | M5)},						/* dispc2_vsync */
+	{DPM_EMU10, (IEN | M5)},					/* dispc2_de */
+	{DPM_EMU11, (IEN | M5)},					/* dispc2_data8 */
+	{DPM_EMU12, (IEN | M5)},					/* dispc2_data7 */
+	{DPM_EMU13, (IEN | M5)},					/* dispc2_data6 */
+	{DPM_EMU14, (IEN | M5)},					/* dispc2_data5 */
+	{DPM_EMU15, (IEN | M5)},					/* dispc2_data4 */
+	{DPM_EMU16, (M3)},						/* gpio_27 */
+	{DPM_EMU17, (IEN | M5)},					/* dispc2_data2 */
+	{DPM_EMU18, (IEN | M5)},					/* dispc2_data1 */
+	{DPM_EMU19, (IEN | M5)},					/* dispc2_data0 */
+};
+
+const struct pad_conf_entry wkup_padconf_array[] = {
+	{PAD0_SIM_IO, (IEN | M0)},		/* sim_io */
+	{PAD1_SIM_CLK, (M0)},			/* sim_clk */
+	{PAD0_SIM_RESET, (M0)},			/* sim_reset */
+	{PAD1_SIM_CD, (PTU | IEN | M0)},	/* sim_cd */
+	{PAD0_SIM_PWRCTRL, (M0)},		/* sim_pwrctrl */
+	{PAD1_SR_SCL, (PTU | IEN | M0)},	/* sr_scl */
+	{PAD0_SR_SDA, (PTU | IEN | M0)},	/* sr_sda */
+	{PAD1_FREF_XTAL_IN, (M0)},		/* # */
+	{PAD0_FREF_SLICER_IN, (M0)},		/* fref_slicer_in */
+	{PAD1_FREF_CLK_IOREQ, (M0)},		/* fref_clk_ioreq */
+	{PAD0_FREF_CLK0_OUT, (M2)},		/* sys_drm_msecure */
+	{PAD1_FREF_CLK3_REQ, (PTU | IEN | M0)},	/* # */
+	{PAD0_FREF_CLK3_OUT, (M0)},		/* fref_clk3_out */
+	{PAD1_FREF_CLK4_REQ, (PTU | IEN | M0)},	/* # */
+	{PAD0_FREF_CLK4_OUT, (M0)},		/* # */
+	{PAD1_SYS_32K, (IEN | M0)},		/* sys_32k */
+	{PAD0_SYS_NRESPWRON, (M0)},		/* sys_nrespwron */
+	{PAD1_SYS_NRESWARM, (M0)},		/* sys_nreswarm */
+	{PAD0_SYS_PWR_REQ, (PTU | M0)},		/* sys_pwr_req */
+	{PAD1_SYS_PWRON_RESET, (M3)},		/* gpio_wk29 */
+	{PAD0_SYS_BOOT6, (IEN | M3)},		/* gpio_wk9 */
+	{PAD1_SYS_BOOT7, (IEN | M3)},		/* gpio_wk10 */
+};
+
+#endif
+

common/cmd_ide.c

@@ -25,6 +25,7 @@
 /*
  * IDE support
  */
+
 #include <common.h>
 #include <config.h>
 #include <watchdog.h>
@@ -45,6 +46,12 @@
 #include <mpc5xxx.h>
 #endif
 
+#ifdef CONFIG_ORION5X
+#include <asm/arch/orion5x.h>
+#elif defined CONFIG_KIRKWOOD
+#include <asm/arch/kirkwood.h>
+#endif
+
 #include <ide.h>
 #include <ata.h>
 
@@ -847,7 +854,7 @@ input_swap_data(int dev, ulong *sect_buf, int words)
 #endif	/* __LITTLE_ENDIAN || CONFIG_AU1X00 */
 
 
-#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA) || defined(CONFIG_SH)
+#if defined(CONFIG_IDE_SWAP_IO)
 static void
 output_data(int dev, ulong *sect_buf, int words)
 {
@@ -891,15 +898,15 @@ output_data(int dev, ulong *sect_buf, int words)
 	}
 #endif
 }
-#else	/* ! __PPC__ */
+#else	/* ! CONFIG_IDE_SWAP_IO */
 static void
 output_data(int dev, ulong *sect_buf, int words)
 {
 	outsw(ATA_CURR_BASE(dev)+ATA_DATA_REG, sect_buf, words<<1);
 }
-#endif	/* __PPC__ */
+#endif	/* CONFIG_IDE_SWAP_IO */
 
-#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA) || defined(CONFIG_SH)
+#if defined(CONFIG_IDE_SWAP_IO)
 static void
 input_data(int dev, ulong *sect_buf, int words)
 {
@@ -949,14 +956,14 @@ input_data(int dev, ulong *sect_buf, int words)
 	}
 #endif
 }
-#else	/* ! __PPC__ */
+#else	/* ! CONFIG_IDE_SWAP_IO */
 static void
 input_data(int dev, ulong *sect_buf, int words)
 {
 	insw(ATA_CURR_BASE(dev)+ATA_DATA_REG, sect_buf, words << 1);
 }
 
-#endif	/* __PPC__ */
+#endif	/* CONFIG_IDE_SWAP_IO */
 
 /* -------------------------------------------------------------------------
  */
@@ -1573,7 +1580,7 @@ int ide_device_present(int dev)
  * ATAPI Support
  */
 
-#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA)
+#if defined(CONFIG_IDE_SWAP_IO)
 /* since ATAPI may use commands with not 4 bytes alligned length
  * we have our own transfer functions, 2 bytes alligned */
 static void
@@ -1640,7 +1647,7 @@ input_data_shorts(int dev, ushort *sect_buf, int shorts)
 #endif
 }
 
-#else	/* ! __PPC__ */
+#else	/* ! CONFIG_IDE_SWAP_IO */
 static void
 output_data_shorts(int dev, ushort *sect_buf, int shorts)
 {
@@ -1653,7 +1660,7 @@ input_data_shorts(int dev, ushort *sect_buf, int shorts)
 	insw(ATA_CURR_BASE(dev)+ATA_DATA_REG, sect_buf, shorts);
 }
 
-#endif	/* __PPC__ */
+#endif	/* CONFIG_IDE_SWAP_IO */
 
 /*
  * Wait until (Status & mask) == res, or timeout (in ms)

common/cmd_mmc.c

@@ -133,7 +133,7 @@ int do_mmcinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 U_BOOT_CMD(
 	mmcinfo, 2, 0, do_mmcinfo,
 	"display MMC info",
-	"<dev num>\n
+	"<dev num>\n"
         "    - device number of the device to dislay info of\n"
 	""
 );

doc/README.PXA_CF

@@ -6,6 +6,14 @@ follow the connections of the standard lubbock. Anyway just the block
 marked memory configuration should be touched since the other parameters
 are imposed by the PXA architecture.
 
+EDIT 2010-07-01: in common/cmd_ide.c, having CONFIG_PXA_PCMCIA defined
+would cause looping on inw()/outw() rather than using insw()/outsw(),
+thus making sure IDE / ATA bytes are properly swapped. This behaviour
+is now controlled by CONFIG_IDE_SWAP_IO, therefore PXA boards with
+PCMCIA should #define CONFIG_IDE_SWAP_IO.
+
+#define CONFIG_IDE_SWAP_IO
+
 #define CONFIG_PXA_PCMCIA 1
 #define CONFIG_PXA_IDE 1
 

drivers/block/Makefile

@@ -25,15 +25,16 @@ include $(TOPDIR)/config.mk
 
 LIB	:= $(obj)libblock.a
 
+COBJS-$(CONFIG_SCSI_AHCI) += ahci.o
 COBJS-$(CONFIG_ATA_PIIX) += ata_piix.o
-COBJS-$(CONFIG_CMD_MG_DISK) += mg_disk.o
 COBJS-$(CONFIG_FSL_SATA) += fsl_sata.o
-COBJS-$(CONFIG_IDE_SIL680) += sil680.o
 COBJS-$(CONFIG_LIBATA) += libata.o
+COBJS-$(CONFIG_CMD_MG_DISK) += mg_disk.o
+COBJS-$(CONFIG_MVSATA_IDE) += mvsata_ide.o
 COBJS-$(CONFIG_PATA_BFIN) += pata_bfin.o
 COBJS-$(CONFIG_SATA_DWC) += sata_dwc.o
 COBJS-$(CONFIG_SATA_SIL3114) += sata_sil3114.o
-COBJS-$(CONFIG_SCSI_AHCI) += ahci.o
+COBJS-$(CONFIG_IDE_SIL680) += sil680.o
 COBJS-$(CONFIG_SCSI_SYM53C8XX) += sym53c8xx.o
 COBJS-$(CONFIG_SYSTEMACE) += systemace.o
 

drivers/block/mvsata_ide.c

@@ -0,0 +1,140 @@
+/*
+ * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+ *
+ * Written-by: Albert ARIBAUD <albert.aribaud@free.fr>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#if defined(CONFIG_ORION5X)
+#include <asm/arch/orion5x.h>
+#elif defined(CONFIG_KIRKWOOD)
+#include <asm/arch/kirkwood.h>
+#endif
+
+/* SATA port registers */
+struct mvsata_port_registers {
+	u32 reserved1[192];
+	/* offset 0x300 : ATA Interface registers */
+	u32 sstatus;
+	u32 serror;
+	u32 scontrol;
+	u32 ltmode;
+	u32 phymode3;
+	u32 phymode4;
+	u32 reserved2[5];
+	u32 phymode1;
+	u32 phymode2;
+	u32 bist_cr;
+	u32 bist_dw1;
+	u32 bist_dw2;
+	u32 serrorintrmask;
+};
+
+/*
+ * Sanity checks:
+ * - to compile at all, we need CONFIG_SYS_ATA_BASE_ADDR.
+ * - for ide_preinit to make sense, we need at least one of
+ *   CONFIG_SYS_ATA_IDE0_OFFSET or CONFIG_SYS_ATA_IDE0_OFFSET;
+ * - for inde_preinit to be called, we need CONFIG_IDE_PREINIT.
+ * Fail with an explanation message if these conditions are not met.
+ * This is particularly important for CONFIG_IDE_PREINIT, because
+ * its lack would not cause a build error.
+ */
+
+#if !defined(CONFIG_SYS_ATA_BASE_ADDR)
+#error CONFIG_SYS_ATA_BASE_ADDR must be defined
+#elif !defined(CONFIG_SYS_ATA_IDE0_OFFSET) \
+   && !defined(CONFIG_SYS_ATA_IDE1_OFFSET)
+#error CONFIG_SYS_ATA_IDE0_OFFSET or CONFIG_SYS_ATA_IDE1_OFFSET \
+   must be defined
+#elif !defined(CONFIG_IDE_PREINIT)
+#error CONFIG_IDE_PREINIT must be defined
+#endif
+
+/*
+ * Masks and values for SControl DETection and Interface Power Management,
+ * and for SStatus DETection.
+ */
+
+#define MVSATA_SCONTROL_DET_MASK		0x0000000F
+#define MVSATA_SCONTROL_DET_NONE		0x00000000
+#define MVSATA_SCONTROL_DET_INIT		0x00000001
+#define MVSATA_SCONTROL_IPM_MASK		0x00000F00
+#define MVSATA_SCONTROL_IPM_NO_LP_ALLOWED	0x00000300
+#define MVSATA_SCONTROL_MASK \
+	(MVSATA_SCONTROL_DET_MASK|MVSATA_SCONTROL_IPM_MASK)
+#define MVSATA_PORT_INIT \
+	(MVSATA_SCONTROL_DET_INIT|MVSATA_SCONTROL_IPM_NO_LP_ALLOWED)
+#define MVSATA_PORT_USE \
+	(MVSATA_SCONTROL_DET_NONE|MVSATA_SCONTROL_IPM_NO_LP_ALLOWED)
+#define MVSATA_SSTATUS_DET_MASK			0x0000000F
+#define MVSATA_SSTATUS_DET_DEVCOMM		0x00000003
+
+/*
+ * Initialize one MVSATAHC port: set SControl's IPM to "always active"
+ * and DET to "reset", then wait for SStatus's DET to become "device and
+ * comm ok" (or time out after 50 us if no device), then set SControl's
+ * DET back to "no action".
+ */
+
+static void mvsata_ide_initialize_port(struct mvsata_port_registers *port)
+{
+	u32 control;
+	u32 status;
+	u32 tout = 50; /* wait at most 50 us for SATA reset to complete */
+
+	control = readl(&port->scontrol);
+	control = (control & ~MVSATA_SCONTROL_MASK) | MVSATA_PORT_INIT;
+	writel(control, &port->scontrol);
+	while (--tout) {
+		status = readl(&port->sstatus) & MVSATA_SSTATUS_DET_MASK;
+		if (status == MVSATA_SSTATUS_DET_DEVCOMM)
+			break;
+		udelay(1);
+	}
+	control = (control & ~MVSATA_SCONTROL_MASK) | MVSATA_PORT_USE;
+	writel(control, &port->scontrol);
+}
+
+/*
+ * ide_preinit() will be called by ide_init in cmd_ide.c and will
+ * reset the MVSTATHC ports needed by the board.
+ */
+
+int ide_preinit(void)
+{
+	/* Enable ATA port 0 (could be SATA port 0 or 1) if declared */
+#if defined(CONFIG_SYS_ATA_IDE0_OFFSET)
+	mvsata_ide_initialize_port(
+		(struct mvsata_port_registers *)
+		(CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET));
+#endif
+	/* Enable ATA port 1 (could be SATA port 0 or 1) if declared */
+#if defined(CONFIG_SYS_ATA_IDE1_OFFSET)
+	mvsata_ide_initialize_port(
+		(struct mvsata_port_registers *)
+		(CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE1_OFFSET));
+#endif
+	/* return 0 as we always succeed */
+	return 0;
+}

drivers/i2c/omap24xx_i2c.c

@@ -27,6 +27,8 @@
 
 #include "omap24xx_i2c.h"
 
+#define I2C_TIMEOUT	10
+
 static void wait_for_bb (void);
 static u16 wait_for_pin (void);
 static void flush_fifo(void);
@@ -41,6 +43,7 @@ void i2c_init (int speed, int slaveadd)
 	int psc, fsscll, fssclh;
 	int hsscll = 0, hssclh = 0;
 	u32 scll, sclh;
+	int timeout = I2C_TIMEOUT;
 
 	/* Only handle standard, fast and high speeds */
 	if ((speed != OMAP_I2C_STANDARD) &&
@@ -102,15 +105,24 @@ void i2c_init (int speed, int slaveadd)
 		sclh = (unsigned int)fssclh;
 	}
 
-	writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */
-	udelay(1000);
-	writew(0x0, &i2c_base->sysc); /* will probably self clear but */
-
 	if (readw (&i2c_base->con) & I2C_CON_EN) {
 		writew (0, &i2c_base->con);
 		udelay (50000);
 	}
 
+	writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */
+	udelay(1000);
+
+	writew(I2C_CON_EN, &i2c_base->con);
+	while (!(readw(&i2c_base->syss) & I2C_SYSS_RDONE) && timeout--) {
+		if (timeout <= 0) {
+			printf("ERROR: Timeout in soft-reset\n");
+			return;
+		}
+		udelay(1000);
+	}
+
+	writew(0, &i2c_base->con);
 	writew(psc, &i2c_base->psc);
 	writew(scll, &i2c_base->scll);
 	writew(sclh, &i2c_base->sclh);
@@ -159,15 +171,14 @@ static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
 	}
 
 	if (!i2c_error) {
-		/* free bus, otherwise we can't use a combined transction */
-		writew (0, &i2c_base->con);
-		while (readw (&i2c_base->stat) || (readw (&i2c_base->con) & I2C_CON_MST)) {
+		writew (I2C_CON_EN, &i2c_base->con);
+		while (readw(&i2c_base->stat) &
+			(I2C_STAT_XRDY | I2C_STAT_ARDY)) {
 			udelay (10000);
 			/* Have to clear pending interrupt to clear I2C_STAT */
 			writew (0xFFFF, &i2c_base->stat);
 		}
 
-		wait_for_bb ();
 		/* set slave address */
 		writew (devaddr, &i2c_base->sa);
 		/* read one byte from slave */
@@ -191,8 +202,8 @@ static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
 
 		if (!i2c_error) {
 			writew (I2C_CON_EN, &i2c_base->con);
-			while (readw (&i2c_base->stat)
-			       || (readw (&i2c_base->con) & I2C_CON_MST)) {
+			while (readw (&i2c_base->stat) &
+				(I2C_STAT_RRDY | I2C_STAT_ARDY)) {
 				udelay (10000);
 				writew (0xFFFF, &i2c_base->stat);
 			}

drivers/i2c/omap24xx_i2c.h

@@ -85,6 +85,10 @@
 #define I2C_SYSTEST_SDA_I	(1 << 1)  /* SDA line sense input value */
 #define I2C_SYSTEST_SDA_O	(1 << 0)  /* SDA line drive output value */
 
+/* I2C System Status Register (I2C_SYSS): */
+
+#define I2C_SYSS_RDONE          (1 << 0)  /* Internel reset monitoring */
+
 #define I2C_SCLL_SCLL		0
 #define I2C_SCLL_SCLL_M		0xFF
 #define I2C_SCLL_HSSCLL		8

drivers/mmc/Makefile

@@ -32,6 +32,7 @@ COBJS-$(CONFIG_OMAP3_MMC) += omap3_mmc.o
 COBJS-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
 COBJS-$(CONFIG_MXC_MMC) += mxcmmc.o
 COBJS-$(CONFIG_PXA_MMC) += pxa_mmc.o
+COBJS-$(CONFIG_S5P_MMC) += s5p_mmc.o
 
 COBJS	:= $(COBJS-y)
 SRCS	:= $(COBJS:.o=.c)

drivers/mmc/s5p_mmc.c

@@ -0,0 +1,478 @@
+/*
+ * (C) Copyright 2009 SAMSUNG Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Jaehoon Chung <jh80.chung@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <common.h>
+#include <mmc.h>
+#include <asm/io.h>
+#include <asm/arch/mmc.h>
+
+#ifdef DEBUG_S5P_HSMMC
+#define dbg(x...)       printf(x)
+#else
+#define dbg(x...)       do { } while (0)
+#endif
+
+/* support 4 mmc hosts */
+struct mmc mmc_dev[4];
+struct mmc_host mmc_host[4];
+
+static inline struct s5p_mmc *s5p_get_base_mmc(int dev_index)
+{
+	unsigned long offset = dev_index * sizeof(struct s5p_mmc);
+
+	if (cpu_is_s5pc100())
+		return (struct s5p_mmc *)(S5PC100_MMC_BASE + offset);
+	else
+		return (struct s5p_mmc *)(S5PC110_MMC_BASE + offset);
+}
+
+static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data)
+{
+	unsigned char ctrl;
+
+	dbg("data->dest: %08x\n", (u32)data->dest);
+	writel((u32)data->dest, &host->reg->sysad);
+	/*
+	 * DMASEL[4:3]
+	 * 00 = Selects SDMA
+	 * 01 = Reserved
+	 * 10 = Selects 32-bit Address ADMA2
+	 * 11 = Selects 64-bit Address ADMA2
+	 */
+	ctrl = readb(&host->reg->hostctl);
+	ctrl &= ~(3 << 3);
+	writeb(ctrl, &host->reg->hostctl);
+
+	/* We do not handle DMA boundaries, so set it to max (512 KiB) */
+	writew((7 << 12) | (512 << 0), &host->reg->blksize);
+	writew(data->blocks, &host->reg->blkcnt);
+}
+
+static void mmc_set_transfer_mode(struct mmc_host *host, struct mmc_data *data)
+{
+	unsigned short mode;
+
+	/*
+	 * TRNMOD
+	 * MUL1SIN0[5]	: Multi/Single Block Select
+	 * RD1WT0[4]	: Data Transfer Direction Select
+	 *	1 = read
+	 *	0 = write
+	 * ENACMD12[2]	: Auto CMD12 Enable
+	 * ENBLKCNT[1]	: Block Count Enable
+	 * ENDMA[0]	: DMA Enable
+	 */
+	mode = (1 << 1) | (1 << 0);
+	if (data->blocks > 1)
+		mode |= (1 << 5);
+	if (data->flags & MMC_DATA_READ)
+		mode |= (1 << 4);
+
+	writew(mode, &host->reg->trnmod);
+}
+
+static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
+			struct mmc_data *data)
+{
+	struct mmc_host *host = (struct mmc_host *)mmc->priv;
+	int flags, i;
+	unsigned int timeout;
+	unsigned int mask;
+	unsigned int retry = 0x100000;
+
+	/* Wait max 10 ms */
+	timeout = 10;
+
+	/*
+	 * PRNSTS
+	 * CMDINHDAT[1]	: Command Inhibit (DAT)
+	 * CMDINHCMD[0]	: Command Inhibit (CMD)
+	 */
+	mask = (1 << 0);
+	if ((data != NULL) || (cmd->resp_type & MMC_RSP_BUSY))
+		mask |= (1 << 1);
+
+	/*
+	 * We shouldn't wait for data inihibit for stop commands, even
+	 * though they might use busy signaling
+	 */
+	if (data)
+		mask &= ~(1 << 1);
+
+	while (readl(&host->reg->prnsts) & mask) {
+		if (timeout == 0) {
+			printf("%s: timeout error\n", __func__);
+			return -1;
+		}
+		timeout--;
+		udelay(1000);
+	}
+
+	if (data)
+		mmc_prepare_data(host, data);
+
+	dbg("cmd->arg: %08x\n", cmd->cmdarg);
+	writel(cmd->cmdarg, &host->reg->argument);
+
+	if (data)
+		mmc_set_transfer_mode(host, data);
+
+	if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
+		return -1;
+
+	/*
+	 * CMDREG
+	 * CMDIDX[13:8]	: Command index
+	 * DATAPRNT[5]	: Data Present Select
+	 * ENCMDIDX[4]	: Command Index Check Enable
+	 * ENCMDCRC[3]	: Command CRC Check Enable
+	 * RSPTYP[1:0]
+	 *	00 = No Response
+	 *	01 = Length 136
+	 *	10 = Length 48
+	 *	11 = Length 48 Check busy after response
+	 */
+	if (!(cmd->resp_type & MMC_RSP_PRESENT))
+		flags = 0;
+	else if (cmd->resp_type & MMC_RSP_136)
+		flags = (1 << 0);
+	else if (cmd->resp_type & MMC_RSP_BUSY)
+		flags = (3 << 0);
+	else
+		flags = (2 << 0);
+
+	if (cmd->resp_type & MMC_RSP_CRC)
+		flags |= (1 << 3);
+	if (cmd->resp_type & MMC_RSP_OPCODE)
+		flags |= (1 << 4);
+	if (data)
+		flags |= (1 << 5);
+
+	dbg("cmd: %d\n", cmd->cmdidx);
+
+	writew((cmd->cmdidx << 8) | flags, &host->reg->cmdreg);
+
+	for (i = 0; i < retry; i++) {
+		mask = readl(&host->reg->norintsts);
+		/* Command Complete */
+		if (mask & (1 << 0)) {
+			if (!data)
+				writel(mask, &host->reg->norintsts);
+			break;
+		}
+	}
+
+	if (i == retry) {
+		printf("%s: waiting for status update\n", __func__);
+		return TIMEOUT;
+	}
+
+	if (mask & (1 << 16)) {
+		/* Timeout Error */
+		dbg("timeout: %08x cmd %d\n", mask, cmd->cmdidx);
+		return TIMEOUT;
+	} else if (mask & (1 << 15)) {
+		/* Error Interrupt */
+		dbg("error: %08x cmd %d\n", mask, cmd->cmdidx);
+		return -1;
+	}
+
+	if (cmd->resp_type & MMC_RSP_PRESENT) {
+		if (cmd->resp_type & MMC_RSP_136) {
+			/* CRC is stripped so we need to do some shifting. */
+			for (i = 0; i < 4; i++) {
+				unsigned int offset =
+					(unsigned int)(&host->reg->rspreg3 - i);
+				cmd->response[i] = readl(offset) << 8;
+
+				if (i != 3) {
+					cmd->response[i] |=
+						readb(offset - 1);
+				}
+				dbg("cmd->resp[%d]: %08x\n",
+						i, cmd->response[i]);
+			}
+		} else if (cmd->resp_type & MMC_RSP_BUSY) {
+			for (i = 0; i < retry; i++) {
+				/* PRNTDATA[23:20] : DAT[3:0] Line Signal */
+				if (readl(&host->reg->prnsts)
+					& (1 << 20))	/* DAT[0] */
+					break;
+			}
+
+			if (i == retry) {
+				printf("%s: card is still busy\n", __func__);
+				return TIMEOUT;
+			}
+
+			cmd->response[0] = readl(&host->reg->rspreg0);
+			dbg("cmd->resp[0]: %08x\n", cmd->response[0]);
+		} else {
+			cmd->response[0] = readl(&host->reg->rspreg0);
+			dbg("cmd->resp[0]: %08x\n", cmd->response[0]);
+		}
+	}
+
+	if (data) {
+		while (1) {
+			mask = readl(&host->reg->norintsts);
+
+			if (mask & (1 << 15)) {
+				/* Error Interrupt */
+				writel(mask, &host->reg->norintsts);
+				printf("%s: error during transfer: 0x%08x\n",
+						__func__, mask);
+				return -1;
+			} else if (mask & (1 << 3)) {
+				/* DMA Interrupt */
+				dbg("DMA end\n");
+				break;
+			} else if (mask & (1 << 1)) {
+				/* Transfer Complete */
+				dbg("r/w is done\n");
+				break;
+			}
+		}
+		writel(mask, &host->reg->norintsts);
+	}
+
+	udelay(1000);
+	return 0;
+}
+
+static void mmc_change_clock(struct mmc_host *host, uint clock)
+{
+	int div;
+	unsigned short clk;
+	unsigned long timeout;
+	unsigned long ctrl2;
+
+	/*
+	 * SELBASECLK[5:4]
+	 * 00/01 = HCLK
+	 * 10 = EPLL
+	 * 11 = XTI or XEXTCLK
+	 */
+	ctrl2 = readl(&host->reg->control2);
+	ctrl2 &= ~(3 << 4);
+	ctrl2 |= (2 << 4);
+	writel(ctrl2, &host->reg->control2);
+
+	writew(0, &host->reg->clkcon);
+
+	/* XXX: we assume that clock is between 40MHz and 50MHz */
+	if (clock == 0)
+		goto out;
+	else if (clock <= 400000)
+		div = 0x100;
+	else if (clock <= 20000000)
+		div = 4;
+	else if (clock <= 26000000)
+		div = 2;
+	else
+		div = 1;
+	dbg("div: %d\n", div);
+
+	div >>= 1;
+	/*
+	 * CLKCON
+	 * SELFREQ[15:8]	: base clock divied by value
+	 * ENSDCLK[2]		: SD Clock Enable
+	 * STBLINTCLK[1]	: Internal Clock Stable
+	 * ENINTCLK[0]		: Internal Clock Enable
+	 */
+	clk = (div << 8) | (1 << 0);
+	writew(clk, &host->reg->clkcon);
+
+	/* Wait max 10 ms */
+	timeout = 10;
+	while (!(readw(&host->reg->clkcon) & (1 << 1))) {
+		if (timeout == 0) {
+			printf("%s: timeout error\n", __func__);
+			return;
+		}
+		timeout--;
+		udelay(1000);
+	}
+
+	clk |= (1 << 2);
+	writew(clk, &host->reg->clkcon);
+
+out:
+	host->clock = clock;
+}
+
+static void mmc_set_ios(struct mmc *mmc)
+{
+	struct mmc_host *host = mmc->priv;
+	unsigned char ctrl;
+	unsigned long val;
+
+	dbg("set_ios: bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock);
+
+	/*
+	 * SELCLKPADDS[17:16]
+	 * 00 = 2mA
+	 * 01 = 4mA
+	 * 10 = 7mA
+	 * 11 = 9mA
+	 */
+	writel(0x3 << 16, &host->reg->control4);
+
+	val = readl(&host->reg->control2);
+	val &= (0x3 << 4);
+
+	val |=	(1 << 31) |	/* write status clear async mode enable */
+		(1 << 30) |	/* command conflict mask enable */
+		(1 << 14) |	/* Feedback Clock Enable for Rx Clock */
+		(1 << 8);	/* SDCLK hold enable */
+
+	writel(val, &host->reg->control2);
+
+	/*
+	 * FCSEL1[15] FCSEL0[7]
+	 * FCSel[1:0] : Rx Feedback Clock Delay Control
+	 *	Inverter delay means10ns delay if SDCLK 50MHz setting
+	 *	01 = Delay1 (basic delay)
+	 *	11 = Delay2 (basic delay + 2ns)
+	 *	00 = Delay3 (inverter delay)
+	 *	10 = Delay4 (inverter delay + 2ns)
+	 */
+	writel(0x8080, &host->reg->control3);
+
+	mmc_change_clock(host, mmc->clock);
+
+	ctrl = readb(&host->reg->hostctl);
+
+	/*
+	 * WIDE4[1]
+	 * 1 = 4-bit mode
+	 * 0 = 1-bit mode
+	 */
+	if (mmc->bus_width == 4)
+		ctrl |= (1 << 1);
+	else
+		ctrl &= ~(1 << 1);
+
+	/*
+	 * OUTEDGEINV[2]
+	 * 1 = Riging edge output
+	 * 0 = Falling edge output
+	 */
+	ctrl &= ~(1 << 2);
+
+	writeb(ctrl, &host->reg->hostctl);
+}
+
+static void mmc_reset(struct mmc_host *host)
+{
+	unsigned int timeout;
+
+	/*
+	 * RSTALL[0] : Software reset for all
+	 * 1 = reset
+	 * 0 = work
+	 */
+	writeb((1 << 0), &host->reg->swrst);
+
+	host->clock = 0;
+
+	/* Wait max 100 ms */
+	timeout = 100;
+
+	/* hw clears the bit when it's done */
+	while (readb(&host->reg->swrst) & (1 << 0)) {
+		if (timeout == 0) {
+			printf("%s: timeout error\n", __func__);
+			return;
+		}
+		timeout--;
+		udelay(1000);
+	}
+}
+
+static int mmc_core_init(struct mmc *mmc)
+{
+	struct mmc_host *host = (struct mmc_host *)mmc->priv;
+	unsigned int mask;
+
+	mmc_reset(host);
+
+	host->version = readw(&host->reg->hcver);
+
+	/* mask all */
+	writel(0xffffffff, &host->reg->norintstsen);
+	writel(0xffffffff, &host->reg->norintsigen);
+
+	writeb(0xe, &host->reg->timeoutcon);	/* TMCLK * 2^27 */
+
+	/*
+	 * NORMAL Interrupt Status Enable Register init
+	 * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
+	 * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable
+	 * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
+	 * [0] ENSTACMDCMPLT : Command Complete Status Enable
+	*/
+	mask = readl(&host->reg->norintstsen);
+	mask &= ~(0xffff);
+	mask |= (1 << 5) | (1 << 4) | (1 << 1) | (1 << 0);
+	writel(mask, &host->reg->norintstsen);
+
+	/*
+	 * NORMAL Interrupt Signal Enable Register init
+	 * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable
+	 */
+	mask = readl(&host->reg->norintsigen);
+	mask &= ~(0xffff);
+	mask |= (1 << 1);
+	writel(mask, &host->reg->norintsigen);
+
+	return 0;
+}
+
+static int s5p_mmc_initialize(int dev_index)
+{
+	struct mmc *mmc;
+
+	mmc = &mmc_dev[dev_index];
+
+	sprintf(mmc->name, "SAMSUNG SD/MMC");
+	mmc->priv = &mmc_host[dev_index];
+	mmc->send_cmd = mmc_send_cmd;
+	mmc->set_ios = mmc_set_ios;
+	mmc->init = mmc_core_init;
+
+	mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
+	mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
+
+	mmc->f_min = 400000;
+	mmc->f_max = 52000000;
+
+	mmc_host[dev_index].clock = 0;
+	mmc_host[dev_index].reg = s5p_get_base_mmc(dev_index);
+	mmc_register(mmc);
+
+	return 0;
+}
+
+int s5p_mmc_init(int dev_index)
+{
+	return s5p_mmc_initialize(dev_index);
+}

drivers/power/Makefile

@@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk
 LIB 	:= $(obj)libpower.a
 
 COBJS-$(CONFIG_TWL4030_POWER)	+= twl4030.o
+COBJS-$(CONFIG_TWL6030_POWER)	+= twl6030.o
 
 COBJS	:= $(COBJS-y)
 SRCS 	:= $(COBJS:.o=.c)

drivers/power/twl6030.c

@@ -0,0 +1,78 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <config.h>
+#ifdef CONFIG_TWL6030_POWER
+
+#include <twl6030.h>
+
+/* Functions to read and write from TWL6030 */
+static inline int twl6030_i2c_write_u8(u8 chip_no, u8 val, u8 reg)
+{
+	return i2c_write(chip_no, reg, 1, &val, 1);
+}
+
+static inline int twl6030_i2c_read_u8(u8 chip_no, u8 *val, u8 reg)
+{
+	return i2c_read(chip_no, reg, 1, val, 1);
+}
+
+void twl6030_start_usb_charging(void)
+{
+	twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CHARGERUSB_VICHRG_1500,
+							CHARGERUSB_VICHRG);
+	twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CHARGERUSB_CIN_LIMIT_NONE,
+							CHARGERUSB_CINLIMIT);
+	twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, MBAT_TEMP,
+							CONTROLLER_INT_MASK);
+	twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, MASK_MCHARGERUSB_THMREG,
+							CHARGERUSB_INT_MASK);
+	twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CHARGERUSB_VOREG_4P0,
+							CHARGERUSB_VOREG);
+	twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CHARGERUSB_CTRL2_VITERM_100,
+							CHARGERUSB_CTRL2);
+	/* Enable USB charging */
+	twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CONTROLLER_CTRL1_EN_CHARGER,
+							CONTROLLER_CTRL1);
+	return;
+}
+
+void twl6030_init_battery_charging(void)
+{
+	twl6030_start_usb_charging();
+	return;
+}
+
+void twl6030_usb_device_settings()
+{
+	u8 data = 0;
+
+	/* Select APP Group and set state to ON */
+	twl6030_i2c_write_u8(TWL6030_CHIP_PM, 0x21, VUSB_CFG_STATE);
+
+	twl6030_i2c_read_u8(TWL6030_CHIP_PM, &data, MISC2);
+	data |= 0x10;
+
+	/* Select the input supply for VBUS regulator */
+	twl6030_i2c_write_u8(TWL6030_CHIP_PM, data, MISC2);
+}
+#endif

drivers/serial/serial_s5p.c

@@ -133,7 +133,7 @@ int serial_getc_dev(const int dev_index)
 			return 0;
 	}
 
-	return (int)(readl(&uart->urxh) & 0xff);
+	return (int)(readb(&uart->urxh) & 0xff);
 }
 
 /*
@@ -149,7 +149,7 @@ void serial_putc_dev(const char c, const int dev_index)
 			return;
 	}
 
-	writel(c, &uart->utxh);
+	writeb(c, &uart->utxh);
 
 	/* If \n, also do \r */
 	if (c == '\n')

drivers/usb/musb/omap3.c

@@ -31,6 +31,7 @@
  */
 
 #include <twl4030.h>
+#include <twl6030.h>
 #include "omap3.h"
 
 static int platform_needs_initialization = 1;
@@ -65,7 +66,12 @@ static struct omap3_otg_regs *otg;
 
 #define OMAP3_OTG_SYSSTATUS_RESETDONE			0x0001
 
+/* OMAP4430 has an internal PHY, use it */
+#ifdef CONFIG_OMAP4430
+#define OMAP3_OTG_INTERFSEL_OMAP			0x0000
+#else
 #define OMAP3_OTG_INTERFSEL_OMAP			0x0001
+#endif
 
 #define OMAP3_OTG_FORCESTDBY_STANDBY			0x0001
 
@@ -105,6 +111,11 @@ int musb_platform_init(void)
 			goto end;
 		}
 #endif
+
+#ifdef CONFIG_TWL6030_POWER
+		twl6030_usb_device_settings();
+#endif
+
 		otg = (struct omap3_otg_regs *)OMAP3_OTG_BASE;
 
 		/* Set OTG to always be on */
@@ -122,6 +133,11 @@ int musb_platform_init(void)
 #ifdef CONFIG_OMAP3_EVM
 		musb_cfg.extvbus = omap3_evm_need_extvbus();
 #endif
+
+#ifdef CONFIG_OMAP4430
+		u32 *usbotghs_control = (u32 *)(CTRL_BASE + 0x33C);
+		*usbotghs_control = 0x15;
+#endif
 		platform_needs_initialization = 0;
 	}
 

drivers/usb/musb/omap3.h

@@ -31,10 +31,11 @@
 #ifndef _MUSB_OMAP3_H_
 #define _MUSB_OMAP3_H_
 
+#include <asm/arch/cpu.h>
 #include "musb_core.h"
 
 /* Base address of MUSB registers */
-#define MENTOR_USB0_BASE (OMAP34XX_CORE_L4_IO_BASE + 0xAB000)
+#define MENTOR_USB0_BASE MUSB_BASE
 
 /* Base address of OTG registers */
 #define OMAP3_OTG_BASE (MENTOR_USB0_BASE + 0x400)
@@ -45,7 +46,7 @@
 int musb_platform_init(void);
 
 #ifdef CONFIG_OMAP3_EVM
-extern u8 omap3_evm_use_extvbus(void);
+extern u8 omap3_evm_need_extvbus(void);
 #endif
 
 #endif /* _MUSB_OMAP3_H */

include/configs/ap325rxa.h

@@ -138,6 +138,7 @@
 #define CONFIG_SYS_ATA_DATA_OFFSET	0x200	/* data reg offset */
 #define CONFIG_SYS_ATA_REG_OFFSET	0x200	/* reg offset */
 #define CONFIG_SYS_ATA_ALT_OFFSET	0x210	/* alternate register offset */
+#define CONFIG_IDE_SWAP_IO
 
 /* if you use all NOR Flash , you change dip-switch. Please see Manual. */
 #define CONFIG_SYS_MAX_FLASH_BANKS	1

include/configs/edminiv2.h

@@ -60,7 +60,7 @@
 
 #define ORION5X_MPP0_7		0x00000003
 #define ORION5X_MPP8_15		0x55550000
-#define ORION5X_MPP16_23	0x00000000
+#define ORION5X_MPP16_23	0x00005555
 
 /*
  * Board-specific values for Orion5x GPIO low level init:
@@ -131,6 +131,7 @@
  * Commands configuration - using default command set for now
  */
 #include <config_cmd_default.h>
+#define CONFIG_CMD_IDE
 
 /*
  * Network
@@ -149,6 +150,37 @@
 #define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
 #endif
 
+/*
+ * IDE
+ */
+#ifdef CONFIG_CMD_IDE
+#define __io
+#define CONFIG_IDE_PREINIT
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+/* ED Mini V has an IDE-compatible SATA connector for port 1 */
+#define CONFIG_MVSATA_IDE
+#define CONFIG_MVSATA_IDE_USE_PORT1
+/* Needs byte-swapping for ATA data register */
+#define CONFIG_IDE_SWAP_IO
+/* Data, registers and alternate blocks are at the same offset */
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0100)
+#define CONFIG_SYS_ATA_REG_OFFSET	(0x0100)
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x0100)
+/* Each 8-bit ATA register is aligned to a 4-bytes address */
+#define CONFIG_SYS_ATA_STRIDE		4
+/* Controller supports 48-bits LBA addressing */
+#define CONFIG_LBA48
+/* A single bus, a single device */
+#define CONFIG_SYS_IDE_MAXBUS		1
+#define CONFIG_SYS_IDE_MAXDEVICE	1
+/* ATA registers base is at SATA controller base */
+#define CONFIG_SYS_ATA_BASE_ADDR	ORION5X_SATA_BASE
+/* ATA bus 0 is orion5x port 1 on ED Mini V2 */
+#define CONFIG_SYS_ATA_IDE0_OFFSET	ORION5X_SATA_PORT1_OFFSET
+/* end of IDE defines */
+#endif /* CMD_IDE */
+
 /*
  *  Environment variables configurations
  */

include/configs/ms7720se.h

@@ -122,5 +122,6 @@
 #define CONFIG_SYS_ATA_DATA_OFFSET	0		/* data reg offset */
 #define CONFIG_SYS_ATA_REG_OFFSET	0		/* reg offset */
 #define CONFIG_SYS_ATA_ALT_OFFSET	0x200		/* alternate register offset */
+#define CONFIG_IDE_SWAP_IO
 
 #endif	/* __MS7720SE_H */

include/configs/omap4_panda.h

@@ -35,6 +35,7 @@
 #define CONFIG_OMAP44XX		1	/* which is a 44XX */
 #define CONFIG_OMAP4430		1	/* which is in a 4430 */
 #define CONFIG_PANDA		1	/* working with Panda */
+#define CONFIG_ARCH_CPU_INIT
 
 /* Get CPU defs */
 #include <asm/arch/cpu.h>
@@ -102,12 +103,29 @@
 #define CONFIG_DRIVER_OMAP34XX_I2C	1
 #define CONFIG_I2C_MULTI_BUS		1
 
+/* TWL6030 */
+#define CONFIG_TWL6030_POWER		1
+
 /* MMC */
 #define CONFIG_MMC			1
 #define CONFIG_OMAP3_MMC		1
 #define CONFIG_SYS_MMC_SET_DEV		1
 #define CONFIG_DOS_PARTITION		1
 
+/* USB */
+#define CONFIG_MUSB_UDC			1
+#define CONFIG_USB_OMAP3		1
+
+/* USB device configuration */
+#define CONFIG_USB_DEVICE		1
+#define CONFIG_USB_TTY			1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
+/* Change these to suit your needs */
+#define CONFIG_USBD_VENDORID		0x0451
+#define CONFIG_USBD_PRODUCTID		0x5678
+#define CONFIG_USBD_MANUFACTURER	"Texas Instruments"
+#define CONFIG_USBD_PRODUCT_NAME	"OMAP4 Panda"
+
 /* Flash */
 #define CONFIG_SYS_NO_FLASH	1
 
@@ -135,16 +153,21 @@
  * Environment setup
  */
 
+#define CONFIG_BOOTDELAY	3
+
 /* allow overwriting serial config and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"loadaddr=0x82000000\0" \
 	"console=ttyS2,115200n8\0" \
+	"usbtty=cdc_acm\0" \
+	"vram=16M\0" \
 	"mmcdev=1\0" \
 	"mmcroot=/dev/mmcblk0p2 rw\0" \
 	"mmcrootfstype=ext3 rootwait\0" \
 	"mmcargs=setenv bootargs console=${console} " \
+		"vram=${vram} " \
 		"root=${mmcroot} " \
 		"rootfstype=${mmcrootfstype}\0" \
 	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
@@ -162,7 +185,6 @@
 		"else " \
 			"if run loaduimage; then " \
 				"run mmcboot; " \
-			"else run nandboot; " \
 			"fi; " \
 		"fi; " \
 	"fi"
@@ -195,7 +217,7 @@
 #define CONFIG_SYS_LOAD_ADDR		0x80000000
 
 /* Use General purpose timer 1 */
-#define CONFIG_SYS_TIMERBASE		GPT1_BASE
+#define CONFIG_SYS_TIMERBASE		GPT2_BASE
 #define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
 #define CONFIG_SYS_HZ			1000
 

include/configs/omap4_sdp4430.h

@@ -36,6 +36,7 @@
 #define CONFIG_OMAP44XX		1	/* which is a 44XX */
 #define CONFIG_OMAP4430		1	/* which is in a 4430 */
 #define CONFIG_4430SDP		1	/* working with SDP */
+#define CONFIG_ARCH_CPU_INIT
 
 /* Get CPU defs */
 #include <asm/arch/cpu.h>
@@ -103,12 +104,29 @@
 #define CONFIG_DRIVER_OMAP34XX_I2C	1
 #define CONFIG_I2C_MULTI_BUS		1
 
+/* TWL6030 */
+#define CONFIG_TWL6030_POWER		1
+
 /* MMC */
 #define CONFIG_MMC			1
 #define CONFIG_OMAP3_MMC		1
 #define CONFIG_SYS_MMC_SET_DEV		1
 #define CONFIG_DOS_PARTITION		1
 
+/* USB */
+#define CONFIG_MUSB_UDC			1
+#define CONFIG_USB_OMAP3		1
+
+/* USB device configuration */
+#define CONFIG_USB_DEVICE		1
+#define CONFIG_USB_TTY			1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
+/* Change these to suit your needs */
+#define CONFIG_USBD_VENDORID		0x0451
+#define CONFIG_USBD_PRODUCTID		0x5678
+#define CONFIG_USBD_MANUFACTURER	"Texas Instruments"
+#define CONFIG_USBD_PRODUCT_NAME	"SDP4430"
+
 /* Flash */
 #define CONFIG_SYS_NO_FLASH	1
 
@@ -136,16 +154,21 @@
  * Environment setup
  */
 
+#define CONFIG_BOOTDELAY	3
+
 /* allow overwriting serial config and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"loadaddr=0x82000000\0" \
 	"console=ttyS2,115200n8\0" \
+	"usbtty=cdc_acm\0" \
+	"vram=16M\0" \
 	"mmcdev=1\0" \
 	"mmcroot=/dev/mmcblk0p2 rw\0" \
 	"mmcrootfstype=ext3 rootwait\0" \
 	"mmcargs=setenv bootargs console=${console} " \
+		"vram=${vram} " \
 		"root=${mmcroot} " \
 		"rootfstype=${mmcrootfstype}\0" \
 	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
@@ -163,7 +186,6 @@
 		"else " \
 			"if run loaduimage; then " \
 				"run mmcboot; " \
-			"else run nandboot; " \
 			"fi; " \
 		"fi; " \
 	"fi"
@@ -196,7 +218,7 @@
 #define CONFIG_SYS_LOAD_ADDR		0x80000000
 
 /* Use General purpose timer 1 */
-#define CONFIG_SYS_TIMERBASE		GPT1_BASE
+#define CONFIG_SYS_TIMERBASE		GPT2_BASE
 #define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
 #define CONFIG_SYS_HZ			1000
 

include/configs/openrd_base.h

@@ -103,6 +103,7 @@
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_USB
+#define CONFIG_CMD_IDE
 
 /*
  * NAND configuration
@@ -204,6 +205,36 @@
 #define CONFIG_SUPPORT_VFAT
 #endif /* CONFIG_CMD_USB */
 
+/*
+ * IDe Support on SATA port0
+ */
+#ifdef CONFIG_CMD_IDE
+#define __io
+#define CONFIG_CMD_EXT2
+#define CONFIG_MVSATA_IDE
+#define CONFIG_IDE_PREINIT
+#define CONFIG_MVSATA_IDE_USE_PORT1
+/* Needs byte-swapping for ATA data register */
+#define CONFIG_IDE_SWAP_IO
+/* Data, registers and alternate blocks are at the same offset */
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0100)
+#define CONFIG_SYS_ATA_REG_OFFSET	(0x0100)
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x0100)
+/* Each 8-bit ATA register is aligned to a 4-bytes address */
+#define CONFIG_SYS_ATA_STRIDE		4
+/* Controller supports 48-bits LBA addressing */
+#define CONFIG_LBA48
+/* CONFIG_CMD_IDE requires some #defines for ATA registers */
+#define CONFIG_SYS_IDE_MAXBUS		2
+#define CONFIG_SYS_IDE_MAXDEVICE	2
+/* ATA registers base is at SATA controller base */
+#define CONFIG_SYS_ATA_BASE_ADDR	KW_SATA_BASE
+/* ATA bus 0 is Kirkwood port 0 on openrd */
+#define CONFIG_SYS_ATA_IDE0_OFFSET	KW_SATA_PORT0_OFFSET
+/* ATA bus 1 is Kirkwood port 1 on openrd */
+#define CONFIG_SYS_ATA_IDE1_OFFSET	KW_SATA_PORT1_OFFSET
+#endif /* CONFIG_CMD_IDE */
+
 /*
  * File system
  */

include/configs/r2dplus.h

@@ -96,6 +96,7 @@
 #define CONFIG_SYS_ATA_DATA_OFFSET	0x1000	/* data reg offset */
 #define CONFIG_SYS_ATA_REG_OFFSET	0x1000	/* reg offset */
 #define CONFIG_SYS_ATA_ALT_OFFSET	0x800	/* alternate register offset */
+#define CONFIG_IDE_SWAP_IO
 
 /*
  * SuperH PCI Bridge Configration

include/configs/r7780mp.h

@@ -171,6 +171,7 @@
 #define CONFIG_SYS_ATA_DATA_OFFSET     0x1000          /* data reg offset */
 #define CONFIG_SYS_ATA_REG_OFFSET      0x1000          /* reg offset */
 #define CONFIG_SYS_ATA_ALT_OFFSET      0x800           /* alternate register offset */
+#define CONFIG_IDE_SWAP_IO
 #endif /* CONFIG_CMD_IDE */
 
 #endif /* __R7780RP_H */

include/configs/s5p_goni.h

@@ -67,6 +67,11 @@
 #define CONFIG_SERIAL_MULTI		1
 #define CONFIG_BAUDRATE			115200
 
+/* MMC */
+#define CONFIG_GENERIC_MMC		1
+#define CONFIG_MMC			1
+#define CONFIG_S5P_MMC			1
+
 /* It should define before config_cmd_default.h */
 #define CONFIG_SYS_NO_FLASH		1
 
@@ -82,6 +87,7 @@
 #define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_ONENAND
 #define CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_MMC
 
 #define CONFIG_BOOTDELAY		1
 #define CONFIG_ZERO_BOOTDELAY_CHECK

include/twl6030.h

@@ -0,0 +1,91 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+/* I2C chip addresses */
+#define TWL6030_CHIP_PM		0x48
+
+#define TWL6030_CHIP_USB	0x49
+#define TWL6030_CHIP_ADC	0x49
+#define TWL6030_CHIP_CHARGER	0x49
+#define TWL6030_CHIP_PWM	0x49
+
+/* Battery CHARGER REGISTERS */
+#define CONTROLLER_INT_MASK	0xE0
+#define CONTROLLER_CTRL1	0xE1
+#define CONTROLLER_WDG		0xE2
+#define CONTROLLER_STAT1	0xE3
+#define CHARGERUSB_INT_STATUS	0xE4
+#define CHARGERUSB_INT_MASK	0xE5
+#define CHARGERUSB_STATUS_INT1	0xE6
+#define CHARGERUSB_STATUS_INT2	0xE7
+#define CHARGERUSB_CTRL1	0xE8
+#define CHARGERUSB_CTRL2	0xE9
+#define CHARGERUSB_CTRL3	0xEA
+#define CHARGERUSB_STAT1	0xEB
+#define CHARGERUSB_VOREG	0xEC
+#define CHARGERUSB_VICHRG	0xED
+#define CHARGERUSB_CINLIMIT	0xEE
+#define CHARGERUSB_CTRLLIMIT1	0xEF
+
+/* CHARGERUSB_VICHRG */
+#define CHARGERUSB_VICHRG_500		0x4
+#define CHARGERUSB_VICHRG_1500		0xE
+/* CHARGERUSB_CINLIMIT */
+#define CHARGERUSB_CIN_LIMIT_100	0x1
+#define CHARGERUSB_CIN_LIMIT_300	0x5
+#define CHARGERUSB_CIN_LIMIT_500	0x9
+#define CHARGERUSB_CIN_LIMIT_NONE	0xF
+/* CONTROLLER_INT_MASK */
+#define MVAC_FAULT		(1 << 6)
+#define MAC_EOC			(1 << 5)
+#define MBAT_REMOVED		(1 << 4)
+#define MFAULT_WDG		(1 << 3)
+#define MBAT_TEMP		(1 << 2)
+#define MVBUS_DET		(1 << 1)
+#define MVAC_DET		(1 << 0)
+/* CHARGERUSB_INT_MASK */
+#define MASK_MCURRENT_TERM		(1 << 3)
+#define MASK_MCHARGERUSB_STAT		(1 << 2)
+#define MASK_MCHARGERUSB_THMREG		(1 << 1)
+#define MASK_MCHARGERUSB_FAULT		(1 << 0)
+/* CHARGERUSB_VOREG */
+#define CHARGERUSB_VOREG_3P52		0x01
+#define CHARGERUSB_VOREG_4P0		0x19
+#define CHARGERUSB_VOREG_4P2		0x23
+#define CHARGERUSB_VOREG_4P76		0x3F
+/* CHARGERUSB_CTRL2 */
+#define CHARGERUSB_CTRL2_VITERM_50	(0 << 5)
+#define CHARGERUSB_CTRL2_VITERM_100	(1 << 5)
+#define CHARGERUSB_CTRL2_VITERM_150	(2 << 5)
+/* CONTROLLER_CTRL1 */
+#define CONTROLLER_CTRL1_EN_CHARGER	(1 << 4)
+#define CONTROLLER_CTRL1_SEL_CHARGER	(1 << 3)
+
+#define VUSB_CFG_STATE		0xA2
+#define MISC2			0xE5
+
+void twl6030_init_battery_charging(void);
+void twl6030_usb_device_settings(void);