Merge branch 'next' of git://git.denx.de/u-boot

* 'next' of git://git.denx.de/u-boot:
  MPC8xx: Fixup warning in arch/powerpc/cpu/mpc8xx/cpu.c
  doc: cleanup - move board READMEs into respective board directories
  net: sh_eth: add support for SH7757's GETHER
  net: sh_eth: modify the definitions of regsiter
  net: sh_eth: add SH_ETH_TYPE_ condition
  net: sh_eth: clean up for the SH7757's code
  net: fec_mxc: Fix MDC for xMII
  net: fec_mxc: Fix setting of RCR for xMII
  net: nfs: make NFS_TIMEOUT configurable
  net: Inline the new eth_setenv_enetaddr_by_index function
  net: allow setting env enetaddr from net device setting
  net/designware: Consecutive writes to the same register to be avoided
  CACHE: net: asix: Fix asix driver to work with data cache on
  net: phy: micrel: make ksz9021 phy accessible
  net: abort network initialization if the PHY driver fails
  phylib: phy_startup() should return an error code on failure
  net: tftp: fix type of block arg to store_block

Signed-off-by: Wolfgang Denk <wd@denx.de>

README

@@ -2149,6 +2149,13 @@ The following options need to be configured:
 
 		Timeout waiting for an ARP reply in milliseconds.
 
+		CONFIG_NFS_TIMEOUT
+
+		Timeout in milliseconds used in NFS protocol.
+		If you encounter "ERROR: Cannot umount" in nfs command,
+		try longer timeout such as
+		#define CONFIG_NFS_TIMEOUT 10000UL
+
 - Command Interpreter:
 		CONFIG_AUTO_COMPLETE
 

arch/powerpc/cpu/mpc8xx/cpu.c

@@ -41,6 +41,7 @@
 #include <netdev.h>
 #include <asm/cache.h>
 #include <linux/compiler.h>
+#include <asm/io.h>
 
 #if defined(CONFIG_OF_LIBFDT)
 #include <libfdt.h>
@@ -253,7 +254,7 @@ static int check_CPU (long clock, uint pvr, uint immr)
 	if ((pvr >> 16) != 0x0050)
 		return -1;
 
-	k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
+	k = (immr << 16) | in_be16((ushort *)&immap->im_cpm.cp_dparam[0xB0]);
 	m = 0;
 
 	switch (k) {

board/qemu-mips/README

@@ -13,3 +13,170 @@ Derived from au1x00 with a lot of things cut out.
 Supports emulated flash (patch Jean-Christophe PLAGNIOL-VILLARD) with
 recent qemu versions. When using emulated flash, launch with
 -pflash <filename> and erase mips_bios.bin.
+
+
+
+Notes for the Qemu MIPS port
+----------------------------
+
+I) Example usage:
+
+# ln -s u-boot.bin mips_bios.bin
+start it:
+qemu-system-mips -L . /dev/null -nographic
+
+or
+
+if you use a qemu version after commit 4224
+
+create image:
+# dd of=flash bs=1k count=4k if=/dev/zero
+# dd of=flash bs=1k conv=notrunc if=u-boot.bin
+start it:
+# qemu-system-mips -M mips -pflash flash -monitor null -nographic
+
+2) Download kernel + initrd
+
+On ftp://ftp.denx.de/pub/contrib/Jean-Christophe_Plagniol-Villard/qemu_mips/
+you can downland
+
+#config to build the kernel
+qemu_mips_defconfig
+#patch to fix mips interrupt init on 2.6.24.y kernel
+qemu_mips_kernel.patch
+initrd.gz
+vmlinux
+vmlinux.bin
+System.map
+
+4) Generate uImage
+
+# tools/mkimage -A mips -O linux -T kernel -C gzip -a 0x80010000 -e 0x80245650 -n "Linux 2.6.24.y" -d vmlinux.bin.gz uImage
+
+5) Copy uImage to Flash
+# dd if=uImage bs=1k conv=notrunc seek=224 of=flash
+
+6) Generate Ide Disk
+
+# dd of=ide bs=1k cout=100k if=/dev/zero
+
+# sfdisk -C 261 -d ide
+# partition table of ide
+unit: sectors
+
+     ide1 : start=       63, size=    32067, Id=83
+     ide2 : start=    32130, size=    32130, Id=83
+     ide3 : start=    64260, size=  4128705, Id=83
+     ide4 : start=        0, size=        0, Id= 0
+
+7) Copy to ide
+
+# dd if=uImage bs=512 conv=notrunc seek=63 of=ide
+
+8) Generate ext2 on part 2 on Copy uImage and initrd.gz
+
+# Attached as loop device ide offset = 32130 * 512
+# losetup -o 16450560 -f ide
+# Format as ext2 ( arg2 : nb blocks)
+# mke2fs /dev/loop0 16065
+# losetup -d /dev/loop0
+# Mount and copy uImage and initrd.gz to it
+# mount -o loop,offset=16450560 -t ext2 ide /mnt
+# mkdir /mnt/boot
+# cp {initrd.gz,uImage} /mnt/boot/
+# Umount it
+# umount /mnt
+
+9) Set Environment
+
+setenv rd_start 0x80800000
+setenv rd_size 2663940
+setenv kernel BFC38000
+setenv oad_addr 80500000
+setenv load_addr2 80F00000
+setenv kernel_flash BFC38000
+setenv load_addr_hello 80200000
+setenv bootargs 'root=/dev/ram0 init=/bin/sh'
+setenv load_rd_ext2 'ide res; ext2load ide 0:2 ${rd_start} /boot/initrd.gz'
+setenv load_rd_tftp 'tftp ${rd_start} /initrd.gz'
+setenv load_kernel_hda 'ide res; diskboot ${load_addr} 0:2'
+setenv load_kernel_ext2 'ide res; ext2load ide 0:2 ${load_addr} /boot/uImage'
+setenv load_kernel_tftp 'tftp ${load_addr} /qemu_mips/uImage'
+setenv boot_ext2_ext2 'run load_rd_ext2; run load_kernel_ext2; run addmisc; bootm ${load_addr}'
+setenv boot_ext2_flash 'run load_rd_ext2; run addmisc; bootm ${kernel_flash}'
+setenv boot_ext2_hda 'run load_rd_ext2; run load_kernel_hda; run addmisc; bootm ${load_addr}'
+setenv boot_ext2_tftp 'run load_rd_ext2; run load_kernel_tftp; run addmisc; bootm ${load_addr}'
+setenv boot_tftp_hda 'run load_rd_tftp; run load_kernel_hda; run addmisc; bootm ${load_addr}'
+setenv boot_tftp_ext2 'run load_rd_tftp; run load_kernel_ext2; run addmisc; bootm ${load_addr}'
+setenv boot_tftp_flash 'run load_rd_tftp; run addmisc; bootm ${kernel_flash}'
+setenv boot_tftp_tftp 'run load_rd_tftp; run load_kernel_tftp; run addmisc; bootm ${load_addr}'
+setenv load_hello_tftp 'tftp ${load_addr_hello} /examples/hello_world.bin'
+setenv go_tftp 'run load_hello_tftp; go ${load_addr_hello}'
+setenv addmisc 'setenv bootargs ${bootargs} console=ttyS0,${baudrate} rd_start=${rd_start} rd_size=${rd_size} ethaddr=${ethaddr}'
+setenv bootcmd 'run boot_tftp_flash'
+
+10) Now you can boot from flash, ide, ide+ext2 and tfp
+
+# qemu-system-mips -M mips -pflash flash -monitor null -nographic -net nic -net user -tftp `pwd` -hda ide
+
+II) How to debug U-Boot
+
+In order to debug U-Boot you need to start qemu with gdb server support (-s)
+and waiting the connection to start the CPU (-S)
+
+# qemu-system-mips -S -s -M mips -pflash flash -monitor null -nographic -net nic -net user -tftp `pwd` -hda ide
+
+in an other console you start gdb
+
+1) Debugging of U-Boot Before Relocation
+
+Before relocation, the addresses in the ELF file can be used without any problems
+by connecting to the gdb server localhost:1234
+
+# mipsel-unknown-linux-gnu-gdb u-boot
+GNU gdb 6.6
+Copyright (C) 2006 Free Software Foundation, Inc.
+GDB is free software, covered by the GNU General Public License, and you are
+welcome to change it and/or distribute copies of it under certain conditions.
+Type "show copying" to see the conditions.
+There is absolutely no warranty for GDB.  Type "show warranty" for details.
+This GDB was configured as "--host=i486-linux-gnu --target=mipsel-unknown-linux-gnu"...
+(gdb)  target remote localhost:1234
+Remote debugging using localhost:1234
+_start () at start.S:64
+64		RVECENT(reset,0)	/* U-boot entry point */
+Current language:  auto; currently asm
+(gdb)  b board.c:289
+Breakpoint 1 at 0xbfc00cc8: file board.c, line 289.
+(gdb) c
+Continuing.
+
+Breakpoint 1, board_init_f (bootflag=<value optimized out>) at board.c:290
+290		relocate_code (addr_sp, id, addr);
+Current language:  auto; currently c
+(gdb) p/x addr
+$1 = 0x87fa0000
+
+2) Debugging of U-Boot After Relocation
+
+For debugging U-Boot after relocation we need to know the address to which
+U-Boot relocates itself to 0x87fa0000 by default.
+And replace the symbol table to this offset.
+
+(gdb) symbol-file
+Discard symbol table from `/private/u-boot-arm/u-boot'? (y or n) y
+Error in re-setting breakpoint 1:
+No symbol table is loaded.  Use the "file" command.
+No symbol file now.
+(gdb) add-symbol-file u-boot 0x87fa0000
+add symbol table from file "u-boot" at
+	.text_addr = 0x87fa0000
+(y or n) y
+Reading symbols from /private/u-boot-arm/u-boot...done.
+Breakpoint 1 at 0x87fa0cc8: file board.c, line 289.
+(gdb) c
+Continuing.
+
+Program received signal SIGINT, Interrupt.
+0xffffffff87fa0de4 in udelay (usec=<value optimized out>) at time.c:78
+78		while ((tmo - read_c0_count()) < 0x7fffffff)

board/sandpoint/README

@@ -13,3 +13,401 @@ seem to maintain it any more. I can be reached by mail as
 tkoeller@gmx.net.
 
 Thomas Koeller
+
+
+
+
+The port was tested on a Sandpoint 8240 X3 board, with U-Boot
+installed in the flash memory of the CPU card. Please use the
+following DIP switch settings:
+
+Motherboard:
+
+SW1.1: on	SW1.2: on	SW1.3: on	SW1.4: on
+SW1.5: on	SW1.6: on	SW1.7: on	SW1.8: on
+
+SW2.1: on	SW2.2: on	SW2.3: on	SW2.4: on
+SW2.5: on	SW2.6: on	SW2.7: on	SW2.8: on
+
+
+CPU Card:
+
+SW2.1: OFF	SW2.2: OFF	SW2.3: on	SW2.4: on
+SW2.5: OFF	SW2.6: OFF	SW2.7: OFF	SW2.8: OFF
+
+SW3.1: OFF	SW3.2: on	SW3.3: OFF	SW3.4: OFF
+SW3.5: on	SW3.6: OFF	SW3.7: OFF	SW3.8: on
+
+
+The followind detailed description of installation and initial steps
+with U-Boot and QNX was provided by Jim Sandoz <sandoz@lucent.com>:
+
+
+Directions for installing U-Boot on Sandpoint+Unity8240
+using the Abatron BDI2000 BDM/JTAG debugger ...
+
+Background and Reference info:
+http://u-boot.sourceforge.net/
+http://www.abatron.ch/
+http://www.abatron.ch/BDI/bdihw.html
+http://www.abatron.ch/DataSheets/BDI2000.pdf
+http://www.abatron.ch/Manuals/ManGdbCOP-2000C.pdf
+http://e-www.motorola.com/collateral/SPX3UM.pdf
+http://e-www.motorola.com/collateral/UNITYX4CONFIG.pdf
+
+
+Connection Diagram:
+					    ===========
+ ===                     =====             |-----      |
+|   | <---------------> |     |            |     |     |
+|PC |       rs232       | BDI |=============[]   |     |
+|   |                   |2000 |  BDM probe |     |     |
+|   | <---------------> |     |            |-----      |
+ ===       ethernet      =====             |           |
+					   |           |
+					    ===========
+					 Sandpoint X3 with
+					  Unity 8240 proc
+
+
+PART 1)
+  DIP Switch Settings:
+
+Sandpoint X3 8240 processor board DIP switch settings, with
+U-Boot to be installed in the flash memory of the CPU card:
+
+Motorola Sandpoint X3 Motherboard:
+SW1.1: on	SW1.2: on	SW1.3: on	SW1.4: on
+SW1.5: on	SW1.6: on	SW1.7: on	SW1.8: on
+SW2.1: on	SW2.2: on	SW2.3: on	SW2.4: on
+SW2.5: on	SW2.6: on	SW2.7: on	SW2.8: on
+
+Motorola Unity 8240 CPU Card:
+SW2.1: OFF	SW2.2: OFF	SW2.3: on	SW2.4: on
+SW2.5: OFF	SW2.6: OFF	SW2.7: OFF	SW2.8: OFF
+SW3.1: OFF	SW3.2: on	SW3.3: OFF	SW3.4: OFF
+SW3.5: on	SW3.6: OFF	SW3.7: OFF	SW3.8: on
+
+
+PART 2)
+  Connect the BDI2000 Cable to the Sandpoint/Unity 8240:
+
+BDM Pin 1 on the Unity 8240 processor board is towards the
+PCI PMC connectors, or away from the socketed SDRAM, i.e.:
+
+  ====================
+  | ---------------- |
+  | |    SDRAM     | |
+  | |              | |
+  | ---------------- |
+  | |~|              |
+  | |B|       ++++++ |
+  | |D|       + uP + |
+  | |M|       +8240+ |
+  |  ~ 1      ++++++ |
+  |                  |
+  |                  |
+  |                  |
+  | PMC conn ======  |
+  |   =====  ======  |
+  |                  |
+  ====================
+
+
+PART 3)
+  Setting up the BDI2000, and preparing for TCP/IP network comms:
+
+Connect the BDI2000 to the PC using the supplied serial cable.
+Download the BDI2000 software and install it using setup.exe.
+
+[Note: of course you  can  also  use  the  Linux  command  line  tool
+"bdisetup"  to  configure  your BDI2000 - the sources are included on
+the floppy disk that comes with your BDI2000. Just in case you  don't
+have any Windows PC's - like me :-)   -- wd ]
+
+Power up the BDI2000; then follow directions to assign the IP
+address and related network information.  Note that U-Boot
+will be loaded to the Sandpoint via tftp.  You need to either
+use the Abatron-provided tftp application or provide a tftp
+server (e.g. Linux/Solaris/*BSD) somewhere on your network.
+Once the IP address etc are assigned via the RS232 port,
+further communication with the BDI2000 will happen via the
+ethernet connection.
+
+PART 4)
+  Making a TCP/IP network connection to the Abatron BDI2000:
+
+Telnet to the Abatron BDI2000.  Assuming that all of the
+networking info was loaded via RS232 correctly, you will see
+the following (scrolling):
+
+- TARGET: waiting for target Vcc
+- TARGET: waiting for target Vcc
+
+
+PART 5)
+  Power up the target Sandpoint:
+If the BDM connections are correct, the following will now appear:
+
+- TARGET: waiting for target Vcc
+- TARGET: waiting for target Vcc
+- TARGET: processing power-up delay
+- TARGET: processing user reset request
+- BDI asserts HRESET
+- Reset JTAG controller passed
+- Bypass check: 0x55 => 0xAA
+- Bypass check: 0x55 => 0xAA
+- JTAG exists check passed
+- Target PVR is 0x00810101
+- COP status is 0x01
+- Check running state passed
+- BDI scans COP freeze command
+- BDI removes HRESET
+- COP status is 0x05
+- Check stopped state passed
+- Check LSRL length passed
+- BDI sets breakpoint at 0xFFF00100
+- BDI resumes program execution
+- Waiting for target stop passed
+- TARGET: Target PVR is 0x00810101
+- TARGET: reseting target passed
+- TARGET: processing target startup ....
+- TARGET: processing target startup passed
+BDI>
+
+
+PART 6)
+  Erase the current contents of the flash memory:
+
+BDI>era 0xFFF00000
+    Erasing flash at 0xfff00000
+    Erasing flash passed
+BDI>era 0xFFF04000
+    Erasing flash at 0xfff04000
+    Erasing flash passed
+BDI>era 0xFFF06000
+    Erasing flash at 0xfff06000
+    Erasing flash passed
+BDI>era 0xFFF08000
+    Erasing flash at 0xfff08000
+    Erasing flash passed
+BDI>era 0xFFF10000
+    Erasing flash at 0xfff10000
+    Erasing flash passed
+BDI>era 0xFFF20000
+    Erasing flash at 0xfff20000
+    Erasing flash passed
+
+
+PART 7)
+  Program the flash memory with the U-Boot image:
+
+BDI>prog 0xFFF00000 u-boot.bin bin
+    Programming u-boot.bin , please wait ....
+    Programming flash passed
+
+
+PART 8)
+  Connect PC to Sandpoint:
+Using a crossover serial cable, attach the PC serial port to the
+Sandpoint's COM1.  Set communications parameters to 8N1 / 9600 baud.
+
+
+PART 9)
+  Reset the Unity and begin U-Boot execution:
+
+BDI>reset
+- TARGET: processing user reset request
+- TARGET: Target PVR is 0x00810101
+- TARGET: reseting target passed
+- TARGET: processing target init list ....
+- TARGET: processing target init list passed
+
+BDI>go
+
+Now see output from U-Boot running, sent via serial port:
+
+U-Boot 1.1.4 (Jan 23 2002 - 18:29:19)
+
+CPU:   MPC8240 Revision 1.1 at 264 MHz: 16 kB I-Cache 16 kB D-Cache
+Board: Sandpoint 8240 Unity
+DRAM:  64 MB
+FLASH:  2 MB
+PCI:    scanning bus0 ...
+  bus dev fn venID devID class  rev MBAR0    MBAR1    IPIN ILINE
+  00  00  00 1057  0003  060000 13  00000008 00000000 01   00
+  00  0b  00 10ad  0565  060100 10  00000000 00000000 00   00
+  00  0f  00 8086  1229  020000 08  80000000 80000001 01   00
+In:    serial
+Out:   serial
+Err:   serial
+=>
+
+
+PART 10)
+  Set and save any required environmental variables, examples of some:
+
+=> setenv ethaddr 00:03:47:97:D0:79
+=> setenv bootfile your_qnx_image_here
+=> setenv hostname sandpointX
+=> setenv netmask 255.255.255.0
+=> setenv ipaddr 192.168.0.11
+=> setenv serverip 192.168.0.10
+=> setenv gatewayip=192.168.0.1
+=> saveenv
+Saving Environment to Flash...
+Un-Protected 1 sectors
+Erasing Flash...
+ done
+Erased 1 sectors
+Writing to Flash... done
+Protected 1 sectors
+=>
+
+**** Example environment: ****
+
+=> printenv
+baudrate=9600
+bootfile=telemetry
+hostname=sp1
+ethaddr=00:03:47:97:E4:6B
+load=tftp 100000 u-boot.bin
+update=protect off all;era FFF00000 FFF3FFFF;cp.b 100000 FFF00000 ${filesize};saveenv
+filesize=1f304
+gatewayip=145.17.228.1
+netmask=255.255.255.0
+ipaddr=145.17.228.42
+serverip=145.17.242.46
+stdin=serial
+stdout=serial
+stderr=serial
+
+Environment size: 332/8188 bytes
+=>
+
+here's some text useful stuff for cut-n-paste:
+setenv hostname sandpoint1
+setenv netmask 255.255.255.0
+setenv ipaddr 145.17.228.81
+setenv serverip 145.17.242.46
+setenv gatewayip 145.17.228.1
+saveenv
+
+PART 11)
+  Test U-Boot by tftp'ing new U-Boot, overwriting current:
+
+=> protect off all
+Un-Protect Flash Bank # 1
+=> tftp 100000 u-boot.bin
+eth: Intel i82559 PCI EtherExpressPro @0x80000000(bus=0, device=15, func=0)
+ARP broadcast 1
+TFTP from server 145.17.242.46; our IP address is 145.17.228.42; sending through
+ gateway 145.17.228.1
+Filename 'u-boot.bin'.
+Load address: 0x100000
+Loading: #########################
+done
+Bytes transferred = 127628 (1f28c hex)
+=> era all
+Erase Flash Bank # 1
+ done
+Erase Flash Bank # 2 - missing
+=> cp.b 0x100000 FFF00000 1f28c
+Copy to Flash... done
+=> saveenv
+Saving Environment to Flash...
+Un-Protected 1 sectors
+Erasing Flash...
+ done
+Erased 1 sectors
+Writing to Flash... done
+Protected 1 sectors
+=> reset
+
+You can put these commands into some environment variables;
+
+=> setenv load tftp 100000 u-boot.bin
+=> setenv update protect off all\;era FFF00000 FFF3FFFF\;cp.b 100000 FFF00000 \${filesize}\;saveenv
+=> saveenv
+
+Then you just have to type "run load" then "run update"
+
+=> run load
+eth: Intel i82559 PCI EtherExpressPro @0x80000000(bus=0, device=15, func=0)
+ARP broadcast 1
+TFTP from server 145.17.242.46; our IP address is 145.17.228.42; sending through
+ gateway 145.17.228.1
+Filename 'u-boot.bin'.
+Load address: 0x100000
+Loading: #########################
+done
+Bytes transferred = 127748 (1f304 hex)
+=> run update
+Un-Protect Flash Bank # 1
+Un-Protect Flash Bank # 2
+Erase Flash from 0xfff00000 to 0xfff3ffff
+ done
+Erased 7 sectors
+Copy to Flash... done
+Saving Environment to Flash...
+Un-Protected 1 sectors
+Erasing Flash...
+ done
+Erased 1 sectors
+Writing to Flash... done
+Protected 1 sectors
+=>
+
+
+PART 12)
+  Load OS image (ELF format) via U-Boot using tftp
+
+
+=> tftp 800000 sandpoint-simple.elf
+eth: Intel i82559 PCI EtherExpressPro @0x80000000(bus=0, device=15, func=0)
+ARP broadcast 1
+TFTP from server 145.17.242.46; our IP address is 145.17.228.42; sending through
+ gateway 145.17.228.1
+Filename 'sandpoint-simple.elf'.
+Load address: 0x800000
+Loading: #################################################################
+	 #################################################################
+	 #################################################################
+	 ########################
+done
+Bytes transferred = 1120284 (11181c hex)
+==>
+
+PART 13)
+  Begin OS image execution: (note that unless you have the
+serial parameters of your OS image set to 9600 (i.e. same as
+the U-Boot binary) you will get garbage here until you change
+the serial communications speed.
+
+=> bootelf 800000
+Loading  @ 0x001f0100 (1120028 bytes)
+## Starting application at 0x001f1d28 ...
+Replace init_hwinfo() with a board specific version
+
+Loading QNX6....
+
+Header size=0x0000009c, Total Size=0x000005c0, #Cpu=1, Type=1
+<...loader and kernel messages snipped...>
+
+Welcome to Neutrino on the Sandpoint
+#
+
+
+other information:
+
+CVS Retrieval Notes:
+
+U-Boot's SourceForge CVS repository can be checked out
+through anonymous (pserver) CVS with the following
+instruction set. The module you wish to check out must
+be specified as the modulename. When prompted for a
+password for anonymous, simply press the Enter key.
+
+cvs -d:pserver:anonymous@cvs.u-boot.sourceforge.net:/cvsroot/u-boot login
+
+cvs -z6 -d:pserver:anonymous@cvs.u-boot.sourceforge.net:/cvsroot/u-boot co -P u-boot

doc/README.OXC

@@ -1,24 +0,0 @@
-This document contains different information about the port
-of U-Boot for the OXC board designed by Lucent Technologies,
-Inc.
-
-1. Showing activity
-
-U-Boot for the OXC board can show its current status using
-the Active LED. This feature is configured by the following
-options:
-
-CONFIG_SHOW_ACTIVITY
-
-  When this option is on, the Active LED is blinking fast
-when U-Boot runs in the idle loop (i.e. waits for user
-commands from serial console) and blinking slow when it
-downloads an image over network. When U-Boot loads an image
-over serial line the Active LED does not blink and its state
-is random (i.e. either constant on or constant off).
-
-CONFIG_SHOW_BOOT_PROGRESS
-
-  When this option is on, U-Boot switches the Active LED
-off before booting an image and switches it on if booting
-failed due to some reasons.

doc/README.Sandpoint8240

@@ -1,394 +0,0 @@
-The port was tested on a Sandpoint 8240 X3 board, with U-Boot
-installed in the flash memory of the CPU card. Please use the
-following DIP switch settings:
-
-Motherboard:
-
-SW1.1: on	SW1.2: on	SW1.3: on	SW1.4: on
-SW1.5: on	SW1.6: on	SW1.7: on	SW1.8: on
-
-SW2.1: on	SW2.2: on	SW2.3: on	SW2.4: on
-SW2.5: on	SW2.6: on	SW2.7: on	SW2.8: on
-
-
-CPU Card:
-
-SW2.1: OFF	SW2.2: OFF	SW2.3: on	SW2.4: on
-SW2.5: OFF	SW2.6: OFF	SW2.7: OFF	SW2.8: OFF
-
-SW3.1: OFF	SW3.2: on	SW3.3: OFF	SW3.4: OFF
-SW3.5: on	SW3.6: OFF	SW3.7: OFF	SW3.8: on
-
-
-The followind detailed description of installation and initial steps
-with U-Boot and QNX was provided by Jim Sandoz <sandoz@lucent.com>:
-
-
-Directions for installing U-Boot on Sandpoint+Unity8240
-using the Abatron BDI2000 BDM/JTAG debugger ...
-
-Background and Reference info:
-http://u-boot.sourceforge.net/
-http://www.abatron.ch/
-http://www.abatron.ch/BDI/bdihw.html
-http://www.abatron.ch/DataSheets/BDI2000.pdf
-http://www.abatron.ch/Manuals/ManGdbCOP-2000C.pdf
-http://e-www.motorola.com/collateral/SPX3UM.pdf
-http://e-www.motorola.com/collateral/UNITYX4CONFIG.pdf
-
-
-Connection Diagram:
-					    ===========
- ===                     =====             |-----      |
-|   | <---------------> |     |            |     |     |
-|PC |       rs232       | BDI |=============[]   |     |
-|   |                   |2000 |  BDM probe |     |     |
-|   | <---------------> |     |            |-----      |
- ===       ethernet      =====             |           |
-					   |           |
-					    ===========
-					 Sandpoint X3 with
-					  Unity 8240 proc
-
-
-PART 1)
-  DIP Switch Settings:
-
-Sandpoint X3 8240 processor board DIP switch settings, with
-U-Boot to be installed in the flash memory of the CPU card:
-
-Motorola Sandpoint X3 Motherboard:
-SW1.1: on	SW1.2: on	SW1.3: on	SW1.4: on
-SW1.5: on	SW1.6: on	SW1.7: on	SW1.8: on
-SW2.1: on	SW2.2: on	SW2.3: on	SW2.4: on
-SW2.5: on	SW2.6: on	SW2.7: on	SW2.8: on
-
-Motorola Unity 8240 CPU Card:
-SW2.1: OFF	SW2.2: OFF	SW2.3: on	SW2.4: on
-SW2.5: OFF	SW2.6: OFF	SW2.7: OFF	SW2.8: OFF
-SW3.1: OFF	SW3.2: on	SW3.3: OFF	SW3.4: OFF
-SW3.5: on	SW3.6: OFF	SW3.7: OFF	SW3.8: on
-
-
-PART 2)
-  Connect the BDI2000 Cable to the Sandpoint/Unity 8240:
-
-BDM Pin 1 on the Unity 8240 processor board is towards the
-PCI PMC connectors, or away from the socketed SDRAM, i.e.:
-
-  ====================
-  | ---------------- |
-  | |    SDRAM     | |
-  | |              | |
-  | ---------------- |
-  | |~|              |
-  | |B|       ++++++ |
-  | |D|       + uP + |
-  | |M|       +8240+ |
-  |  ~ 1      ++++++ |
-  |                  |
-  |                  |
-  |                  |
-  | PMC conn ======  |
-  |   =====  ======  |
-  |                  |
-  ====================
-
-
-PART 3)
-  Setting up the BDI2000, and preparing for TCP/IP network comms:
-
-Connect the BDI2000 to the PC using the supplied serial cable.
-Download the BDI2000 software and install it using setup.exe.
-
-[Note: of course you  can  also  use  the  Linux  command  line  tool
-"bdisetup"  to  configure  your BDI2000 - the sources are included on
-the floppy disk that comes with your BDI2000. Just in case you  don't
-have any Windows PC's - like me :-)   -- wd ]
-
-Power up the BDI2000; then follow directions to assign the IP
-address and related network information.  Note that U-Boot
-will be loaded to the Sandpoint via tftp.  You need to either
-use the Abatron-provided tftp application or provide a tftp
-server (e.g. Linux/Solaris/*BSD) somewhere on your network.
-Once the IP address etc are assigned via the RS232 port,
-further communication with the BDI2000 will happen via the
-ethernet connection.
-
-PART 4)
-  Making a TCP/IP network connection to the Abatron BDI2000:
-
-Telnet to the Abatron BDI2000.  Assuming that all of the
-networking info was loaded via RS232 correctly, you will see
-the following (scrolling):
-
-- TARGET: waiting for target Vcc
-- TARGET: waiting for target Vcc
-
-
-PART 5)
-  Power up the target Sandpoint:
-If the BDM connections are correct, the following will now appear:
-
-- TARGET: waiting for target Vcc
-- TARGET: waiting for target Vcc
-- TARGET: processing power-up delay
-- TARGET: processing user reset request
-- BDI asserts HRESET
-- Reset JTAG controller passed
-- Bypass check: 0x55 => 0xAA
-- Bypass check: 0x55 => 0xAA
-- JTAG exists check passed
-- Target PVR is 0x00810101
-- COP status is 0x01
-- Check running state passed
-- BDI scans COP freeze command
-- BDI removes HRESET
-- COP status is 0x05
-- Check stopped state passed
-- Check LSRL length passed
-- BDI sets breakpoint at 0xFFF00100
-- BDI resumes program execution
-- Waiting for target stop passed
-- TARGET: Target PVR is 0x00810101
-- TARGET: reseting target passed
-- TARGET: processing target startup ....
-- TARGET: processing target startup passed
-BDI>
-
-
-PART 6)
-  Erase the current contents of the flash memory:
-
-BDI>era 0xFFF00000
-    Erasing flash at 0xfff00000
-    Erasing flash passed
-BDI>era 0xFFF04000
-    Erasing flash at 0xfff04000
-    Erasing flash passed
-BDI>era 0xFFF06000
-    Erasing flash at 0xfff06000
-    Erasing flash passed
-BDI>era 0xFFF08000
-    Erasing flash at 0xfff08000
-    Erasing flash passed
-BDI>era 0xFFF10000
-    Erasing flash at 0xfff10000
-    Erasing flash passed
-BDI>era 0xFFF20000
-    Erasing flash at 0xfff20000
-    Erasing flash passed
-
-
-PART 7)
-  Program the flash memory with the U-Boot image:
-
-BDI>prog 0xFFF00000 u-boot.bin bin
-    Programming u-boot.bin , please wait ....
-    Programming flash passed
-
-
-PART 8)
-  Connect PC to Sandpoint:
-Using a crossover serial cable, attach the PC serial port to the
-Sandpoint's COM1.  Set communications parameters to 8N1 / 9600 baud.
-
-
-PART 9)
-  Reset the Unity and begin U-Boot execution:
-
-BDI>reset
-- TARGET: processing user reset request
-- TARGET: Target PVR is 0x00810101
-- TARGET: reseting target passed
-- TARGET: processing target init list ....
-- TARGET: processing target init list passed
-
-BDI>go
-
-Now see output from U-Boot running, sent via serial port:
-
-U-Boot 1.1.4 (Jan 23 2002 - 18:29:19)
-
-CPU:   MPC8240 Revision 1.1 at 264 MHz: 16 kB I-Cache 16 kB D-Cache
-Board: Sandpoint 8240 Unity
-DRAM:  64 MB
-FLASH:  2 MB
-PCI:    scanning bus0 ...
-  bus dev fn venID devID class  rev MBAR0    MBAR1    IPIN ILINE
-  00  00  00 1057  0003  060000 13  00000008 00000000 01   00
-  00  0b  00 10ad  0565  060100 10  00000000 00000000 00   00
-  00  0f  00 8086  1229  020000 08  80000000 80000001 01   00
-In:    serial
-Out:   serial
-Err:   serial
-=>
-
-
-PART 10)
-  Set and save any required environmental variables, examples of some:
-
-=> setenv ethaddr 00:03:47:97:D0:79
-=> setenv bootfile your_qnx_image_here
-=> setenv hostname sandpointX
-=> setenv netmask 255.255.255.0
-=> setenv ipaddr 192.168.0.11
-=> setenv serverip 192.168.0.10
-=> setenv gatewayip=192.168.0.1
-=> saveenv
-Saving Environment to Flash...
-Un-Protected 1 sectors
-Erasing Flash...
- done
-Erased 1 sectors
-Writing to Flash... done
-Protected 1 sectors
-=>
-
-**** Example environment: ****
-
-=> printenv
-baudrate=9600
-bootfile=telemetry
-hostname=sp1
-ethaddr=00:03:47:97:E4:6B
-load=tftp 100000 u-boot.bin
-update=protect off all;era FFF00000 FFF3FFFF;cp.b 100000 FFF00000 ${filesize};saveenv
-filesize=1f304
-gatewayip=145.17.228.1
-netmask=255.255.255.0
-ipaddr=145.17.228.42
-serverip=145.17.242.46
-stdin=serial
-stdout=serial
-stderr=serial
-
-Environment size: 332/8188 bytes
-=>
-
-here's some text useful stuff for cut-n-paste:
-setenv hostname sandpoint1
-setenv netmask 255.255.255.0
-setenv ipaddr 145.17.228.81
-setenv serverip 145.17.242.46
-setenv gatewayip 145.17.228.1
-saveenv
-
-PART 11)
-  Test U-Boot by tftp'ing new U-Boot, overwriting current:
-
-=> protect off all
-Un-Protect Flash Bank # 1
-=> tftp 100000 u-boot.bin
-eth: Intel i82559 PCI EtherExpressPro @0x80000000(bus=0, device=15, func=0)
-ARP broadcast 1
-TFTP from server 145.17.242.46; our IP address is 145.17.228.42; sending through
- gateway 145.17.228.1
-Filename 'u-boot.bin'.
-Load address: 0x100000
-Loading: #########################
-done
-Bytes transferred = 127628 (1f28c hex)
-=> era all
-Erase Flash Bank # 1
- done
-Erase Flash Bank # 2 - missing
-=> cp.b 0x100000 FFF00000 1f28c
-Copy to Flash... done
-=> saveenv
-Saving Environment to Flash...
-Un-Protected 1 sectors
-Erasing Flash...
- done
-Erased 1 sectors
-Writing to Flash... done
-Protected 1 sectors
-=> reset
-
-You can put these commands into some environment variables;
-
-=> setenv load tftp 100000 u-boot.bin
-=> setenv update protect off all\;era FFF00000 FFF3FFFF\;cp.b 100000 FFF00000 \${filesize}\;saveenv
-=> saveenv
-
-Then you just have to type "run load" then "run update"
-
-=> run load
-eth: Intel i82559 PCI EtherExpressPro @0x80000000(bus=0, device=15, func=0)
-ARP broadcast 1
-TFTP from server 145.17.242.46; our IP address is 145.17.228.42; sending through
- gateway 145.17.228.1
-Filename 'u-boot.bin'.
-Load address: 0x100000
-Loading: #########################
-done
-Bytes transferred = 127748 (1f304 hex)
-=> run update
-Un-Protect Flash Bank # 1
-Un-Protect Flash Bank # 2
-Erase Flash from 0xfff00000 to 0xfff3ffff
- done
-Erased 7 sectors
-Copy to Flash... done
-Saving Environment to Flash...
-Un-Protected 1 sectors
-Erasing Flash...
- done
-Erased 1 sectors
-Writing to Flash... done
-Protected 1 sectors
-=>
-
-
-PART 12)
-  Load OS image (ELF format) via U-Boot using tftp
-
-
-=> tftp 800000 sandpoint-simple.elf
-eth: Intel i82559 PCI EtherExpressPro @0x80000000(bus=0, device=15, func=0)
-ARP broadcast 1
-TFTP from server 145.17.242.46; our IP address is 145.17.228.42; sending through
- gateway 145.17.228.1
-Filename 'sandpoint-simple.elf'.
-Load address: 0x800000
-Loading: #################################################################
-	 #################################################################
-	 #################################################################
-	 ########################
-done
-Bytes transferred = 1120284 (11181c hex)
-==>
-
-PART 13)
-  Begin OS image execution: (note that unless you have the
-serial parameters of your OS image set to 9600 (i.e. same as
-the U-Boot binary) you will get garbage here until you change
-the serial communications speed.
-
-=> bootelf 800000
-Loading  @ 0x001f0100 (1120028 bytes)
-## Starting application at 0x001f1d28 ...
-Replace init_hwinfo() with a board specific version
-
-Loading QNX6....
-
-Header size=0x0000009c, Total Size=0x000005c0, #Cpu=1, Type=1
-<...loader and kernel messages snipped...>
-
-Welcome to Neutrino on the Sandpoint
-#
-
-
-other information:
-
-CVS Retrieval Notes:
-
-U-Boot's SourceForge CVS repository can be checked out
-through anonymous (pserver) CVS with the following
-instruction set. The module you wish to check out must
-be specified as the modulename. When prompted for a
-password for anonymous, simply press the Enter key.
-
-cvs -d:pserver:anonymous@cvs.u-boot.sourceforge.net:/cvsroot/u-boot login
-
-cvs -z6 -d:pserver:anonymous@cvs.u-boot.sourceforge.net:/cvsroot/u-boot co -P u-boot

doc/README.amigaone

@@ -1,12 +0,0 @@
-AmigaOne U-Boot and the SciTech emulator
-
-The directory board/MAI/bios_emulator contains the source code
-of the SciTech x86 emulator. This emulator is normally available
-under a BSD license. However, SciTech kindly gave us permission
-to use their emulator in PPCBoot for the AmigaOne. It's available
-in this form only under GPL.
-
-Thanks to Kendall Bennett and the rest of the team at SciTech.
-See http://www.scitechsoft.com for their web site
-
-The GPL license can be found at http://www.gnu.org/licenses/gpl.html

doc/README.enetaddr

@@ -32,7 +32,11 @@ Correct flow of setting up the MAC address (summarized):
 
 1. Read from hardware in initialize() function
 2. Read from environment in net/eth.c after initialize()
-3. Give priority to the value in the environment if a conflict
+3. The environment variable will be compared to the driver initialized
+   struct eth_device->enetaddr. If they differ, a warning is printed, and the
+   environment variable will be used unchanged.
+   If the environment variable is not set, it will be initialized from
+   eth_device->enetaddr, and a warning will be printed.
 4. Program the address into hardware if the following conditions are met:
 	a) The relevant driver has a 'write_addr' function
 	b) The user hasn't set an 'ethmacskip' environment variable

doc/README.p4080ds

@@ -1,32 +0,0 @@
-Overview
---------
-The P4080DS is a Freescale reference board that hosts the eight-core P4080 SOC.
-
-SerDes hwconfig configuration
------------------------------
-The P4080 RCW includes three sets of bits the specify which SerDes lanes
-should be powered down: SRDS_LPD_B1 (for bank one), SRDS_LPD_B2 (for bank two),
-and SRDS_LPD_B3 (for bank three).  Each of these contains four bits, one for
-each lane in the bank.  SerDes Erratum SERDES8 requires that SRDS_LPD_B2 and
-SRDS_LPD_B3 be set to 0b1111.  This forces banks two and three to be powered
-down at reset.
-
-To re-enable these banks in U-Boot, two hwconfig are available:
-"fsl_srds_lpd_b2" and "fsl_srds_lpd_b3".  The value passed via fsl_srds_lpd_b2
-is written into SRDS_LPD_B2, and the value passed via fsl_srds_lpd_b3 is into
-SRDS_LPD_B3.  Each bit represents one of each bank, and a value of '1'
-indicates that the lane should be powered down.
-
-For example, to indicate that both SerDes banks 2 and 3 are powered down, add
-the following to hwconfig:
-
-	serdes:fsl_srds_lpd_b2=0xf,fsl_srds_lpd_b3=0xf
-
-The "0xf" is a mask that corresponds to the 4 lanes A-D. The most significant
-bit corresponds to lane A.  To indicate that just lane A of bank 3 is to be
-powered down, use:
-
-	serdes:fsl_srds_lpd_b3=8
-
-These options should be specified only if U-Boot does not automatically power
-on the correct lanes.

doc/README.qemu_mips

@@ -1,164 +0,0 @@
-
-Notes for the Qemu MIPS port
-
-I) Example usage:
-
-# ln -s u-boot.bin mips_bios.bin
-start it:
-qemu-system-mips -L . /dev/null -nographic
-
-or
-
-if you use a qemu version after commit 4224
-
-create image:
-# dd of=flash bs=1k count=4k if=/dev/zero
-# dd of=flash bs=1k conv=notrunc if=u-boot.bin
-start it:
-# qemu-system-mips -M mips -pflash flash -monitor null -nographic
-
-2) Download kernel + initrd
-
-On ftp://ftp.denx.de/pub/contrib/Jean-Christophe_Plagniol-Villard/qemu_mips/
-you can downland
-
-#config to build the kernel
-qemu_mips_defconfig
-#patch to fix mips interrupt init on 2.6.24.y kernel
-qemu_mips_kernel.patch
-initrd.gz
-vmlinux
-vmlinux.bin
-System.map
-
-4) Generate uImage
-
-# tools/mkimage -A mips -O linux -T kernel -C gzip -a 0x80010000 -e 0x80245650 -n "Linux 2.6.24.y" -d vmlinux.bin.gz uImage
-
-5) Copy uImage to Flash
-# dd if=uImage bs=1k conv=notrunc seek=224 of=flash
-
-6) Generate Ide Disk
-
-# dd of=ide bs=1k cout=100k if=/dev/zero
-
-# sfdisk -C 261 -d ide
-# partition table of ide
-unit: sectors
-
-     ide1 : start=       63, size=    32067, Id=83
-     ide2 : start=    32130, size=    32130, Id=83
-     ide3 : start=    64260, size=  4128705, Id=83
-     ide4 : start=        0, size=        0, Id= 0
-
-7) Copy to ide
-
-# dd if=uImage bs=512 conv=notrunc seek=63 of=ide
-
-8) Generate ext2 on part 2 on Copy uImage and initrd.gz
-
-# Attached as loop device ide offset = 32130 * 512
-# losetup -o 16450560 -f ide
-# Format as ext2 ( arg2 : nb blocks)
-# mke2fs /dev/loop0 16065
-# losetup -d /dev/loop0
-# Mount and copy uImage and initrd.gz to it
-# mount -o loop,offset=16450560 -t ext2 ide /mnt
-# mkdir /mnt/boot
-# cp {initrd.gz,uImage} /mnt/boot/
-# Umount it
-# umount /mnt
-
-9) Set Environment
-
-setenv rd_start 0x80800000
-setenv rd_size 2663940
-setenv kernel BFC38000
-setenv oad_addr 80500000
-setenv load_addr2 80F00000
-setenv kernel_flash BFC38000
-setenv load_addr_hello 80200000
-setenv bootargs 'root=/dev/ram0 init=/bin/sh'
-setenv load_rd_ext2 'ide res; ext2load ide 0:2 ${rd_start} /boot/initrd.gz'
-setenv load_rd_tftp 'tftp ${rd_start} /initrd.gz'
-setenv load_kernel_hda 'ide res; diskboot ${load_addr} 0:2'
-setenv load_kernel_ext2 'ide res; ext2load ide 0:2 ${load_addr} /boot/uImage'
-setenv load_kernel_tftp 'tftp ${load_addr} /qemu_mips/uImage'
-setenv boot_ext2_ext2 'run load_rd_ext2; run load_kernel_ext2; run addmisc; bootm ${load_addr}'
-setenv boot_ext2_flash 'run load_rd_ext2; run addmisc; bootm ${kernel_flash}'
-setenv boot_ext2_hda 'run load_rd_ext2; run load_kernel_hda; run addmisc; bootm ${load_addr}'
-setenv boot_ext2_tftp 'run load_rd_ext2; run load_kernel_tftp; run addmisc; bootm ${load_addr}'
-setenv boot_tftp_hda 'run load_rd_tftp; run load_kernel_hda; run addmisc; bootm ${load_addr}'
-setenv boot_tftp_ext2 'run load_rd_tftp; run load_kernel_ext2; run addmisc; bootm ${load_addr}'
-setenv boot_tftp_flash 'run load_rd_tftp; run addmisc; bootm ${kernel_flash}'
-setenv boot_tftp_tftp 'run load_rd_tftp; run load_kernel_tftp; run addmisc; bootm ${load_addr}'
-setenv load_hello_tftp 'tftp ${load_addr_hello} /examples/hello_world.bin'
-setenv go_tftp 'run load_hello_tftp; go ${load_addr_hello}'
-setenv addmisc 'setenv bootargs ${bootargs} console=ttyS0,${baudrate} rd_start=${rd_start} rd_size=${rd_size} ethaddr=${ethaddr}'
-setenv bootcmd 'run boot_tftp_flash'
-
-10) Now you can boot from flash, ide, ide+ext2 and tfp
-
-# qemu-system-mips -M mips -pflash flash -monitor null -nographic -net nic -net user -tftp `pwd` -hda ide
-
-II) How to debug U-Boot
-
-In order to debug U-Boot you need to start qemu with gdb server support (-s)
-and waiting the connection to start the CPU (-S)
-
-# qemu-system-mips -S -s -M mips -pflash flash -monitor null -nographic -net nic -net user -tftp `pwd` -hda ide
-
-in an other console you start gdb
-
-1) Debugging of U-Boot Before Relocation
-
-Before relocation, the addresses in the ELF file can be used without any problems
-by connecting to the gdb server localhost:1234
-
-# mipsel-unknown-linux-gnu-gdb u-boot
-GNU gdb 6.6
-Copyright (C) 2006 Free Software Foundation, Inc.
-GDB is free software, covered by the GNU General Public License, and you are
-welcome to change it and/or distribute copies of it under certain conditions.
-Type "show copying" to see the conditions.
-There is absolutely no warranty for GDB.  Type "show warranty" for details.
-This GDB was configured as "--host=i486-linux-gnu --target=mipsel-unknown-linux-gnu"...
-(gdb)  target remote localhost:1234
-Remote debugging using localhost:1234
-_start () at start.S:64
-64		RVECENT(reset,0)	/* U-boot entry point */
-Current language:  auto; currently asm
-(gdb)  b board.c:289
-Breakpoint 1 at 0xbfc00cc8: file board.c, line 289.
-(gdb) c
-Continuing.
-
-Breakpoint 1, board_init_f (bootflag=<value optimized out>) at board.c:290
-290		relocate_code (addr_sp, id, addr);
-Current language:  auto; currently c
-(gdb) p/x addr
-$1 = 0x87fa0000
-
-2) Debugging of U-Boot After Relocation
-
-For debugging U-Boot after relocation we need to know the address to which
-U-Boot relocates itself to 0x87fa0000 by default.
-And replace the symbol table to this offset.
-
-(gdb) symbol-file
-Discard symbol table from `/private/u-boot-arm/u-boot'? (y or n) y
-Error in re-setting breakpoint 1:
-No symbol table is loaded.  Use the "file" command.
-No symbol file now.
-(gdb) add-symbol-file u-boot 0x87fa0000
-add symbol table from file "u-boot" at
-	.text_addr = 0x87fa0000
-(y or n) y
-Reading symbols from /private/u-boot-arm/u-boot...done.
-Breakpoint 1 at 0x87fa0cc8: file board.c, line 289.
-(gdb) c
-Continuing.
-
-Program received signal SIGINT, Interrupt.
-0xffffffff87fa0de4 in udelay (usec=<value optimized out>) at time.c:78
-78		while ((tmo - read_c0_count()) < 0x7fffffff)

drivers/net/designware.c

@@ -171,8 +171,8 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis)
 	writel(FIXEDBURST | PRIORXTX_41 | BURST_16,
 			&dma_p->busmode);
 
-	writel(FLUSHTXFIFO | readl(&dma_p->opmode), &dma_p->opmode);
-	writel(STOREFORWARD | TXSECONDFRAME, &dma_p->opmode);
+	writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD |
+		TXSECONDFRAME, &dma_p->opmode);
 
 	conf = FRAMEBURSTENABLE | DISABLERXOWN;
 

drivers/net/fec_mxc.c

@@ -424,14 +424,12 @@ static void fec_reg_setup(struct fec_priv *fec)
 
 	/* Start with frame length = 1518, common for all modes. */
 	rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
-	if (fec->xcv_type == SEVENWIRE)
-		rcntrl |= FEC_RCNTRL_FCE;
-	else if (fec->xcv_type == RGMII)
+	if (fec->xcv_type != SEVENWIRE)		/* xMII modes */
+		rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
+	if (fec->xcv_type == RGMII)
 		rcntrl |= FEC_RCNTRL_RGMII;
 	else if (fec->xcv_type == RMII)
 		rcntrl |= FEC_RCNTRL_RMII;
-	else	/* MII mode */
-		rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
 
 	writel(rcntrl, &fec->eth->r_cntrl);
 }
@@ -510,7 +508,13 @@ static int fec_open(struct eth_device *edev)
 		fec_eth_phy_config(edev);
 	if (fec->phydev) {
 		/* Start up the PHY */
-		phy_startup(fec->phydev);
+		int ret = phy_startup(fec->phydev);
+
+		if (ret) {
+			printf("Could not initialize PHY %s\n",
+			       fec->phydev->dev->name);
+			return ret;
+		}
 		speed = fec->phydev->speed;
 	} else {
 		speed = _100BASET;
@@ -599,7 +603,7 @@ static int fec_init(struct eth_device *dev, bd_t* bd)
 
 	fec_reg_setup(fec);
 
-	if (fec->xcv_type == MII10 || fec->xcv_type == MII100)
+	if (fec->xcv_type != SEVENWIRE)
 		fec_mii_setspeed(fec);
 
 	/*

drivers/net/fm/eth.c

@@ -363,6 +363,9 @@ static int fm_eth_open(struct eth_device *dev, bd_t *bd)
 {
 	struct fm_eth *fm_eth;
 	struct fsl_enet_mac *mac;
+#ifdef CONFIG_PHYLIB
+	int ret;
+#endif
 
 	fm_eth = (struct fm_eth *)dev->priv;
 	mac = fm_eth->mac;
@@ -384,7 +387,11 @@ static int fm_eth_open(struct eth_device *dev, bd_t *bd)
 	fmc_tx_port_graceful_stop_disable(fm_eth);
 
 #ifdef CONFIG_PHYLIB
-	phy_startup(fm_eth->phydev);
+	ret = phy_startup(fm_eth->phydev);
+	if (ret) {
+		printf("%s: Could not initialize\n", fm_eth->phydev->dev->name);
+		return ret;
+	}
 #else
 	fm_eth->phydev->speed = SPEED_1000;
 	fm_eth->phydev->link = 1;

drivers/net/phy/micrel.c

@@ -35,6 +35,12 @@ static struct phy_driver KSZ804_driver = {
 	.shutdown = &genphy_shutdown,
 };
 
+#ifndef CONFIG_PHY_MICREL_KSZ9021
+/*
+ * I can't believe Micrel used the exact same part number
+ * for the KSZ9021
+ * Shame Micrel, Shame!!!!!
+ */
 static struct phy_driver KS8721_driver = {
 	.name = "Micrel KS8721BL",
 	.uid = 0x221610,
@@ -44,7 +50,9 @@ static struct phy_driver KS8721_driver = {
 	.startup = &genphy_startup,
 	.shutdown = &genphy_shutdown,
 };
+#endif
 
+#ifdef CONFIG_PHY_MICREL_KSZ9021
 /* ksz9021 PHY Registers */
 #define MII_KSZ9021_EXTENDED_CTRL	0x0b
 #define MII_KSZ9021_EXTENDED_DATAW	0x0c
@@ -127,12 +135,15 @@ static struct phy_driver ksz9021_driver = {
 	.startup = &ksz9021_startup,
 	.shutdown = &genphy_shutdown,
 };
+#endif
 
 int phy_micrel_init(void)
 {
 	phy_register(&KSZ804_driver);
-	phy_register(&KS8721_driver);
+#ifdef CONFIG_PHY_MICREL_KSZ9021
 	phy_register(&ksz9021_driver);
-
+#else
+	phy_register(&KS8721_driver);
+#endif
 	return 0;
 }

drivers/net/phy/phy.c

@@ -723,10 +723,13 @@ struct phy_device *phy_connect(struct mii_dev *bus, int addr,
 	return phydev;
 }
 
+/*
+ * Start the PHY.  Returns 0 on success, or a negative error code.
+ */
 int phy_startup(struct phy_device *phydev)
 {
 	if (phydev->drv->startup)
-		phydev->drv->startup(phydev);
+		return phydev->drv->startup(phydev);
 
 	return 0;
 }

drivers/net/sh_eth.c

@@ -1,5 +1,5 @@
 /*
- * sh_eth.c - Driver for Renesas SH7763's ethernet controler.
+ * sh_eth.c - Driver for Renesas ethernet controler.
  *
  * Copyright (C) 2008, 2011 Renesas Solutions Corp.
  * Copyright (c) 2008, 2011 Nobuhiro Iwamatsu
@@ -76,8 +76,8 @@ int sh_eth_send(struct eth_device *dev, void *packet, int len)
 		port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP;
 
 	/* Restart the transmitter if disabled */
-	if (!(inl(EDTRR(port)) & EDTRR_TRNS))
-		outl(EDTRR_TRNS, EDTRR(port));
+	if (!(sh_eth_read(eth, EDTRR) & EDTRR_TRNS))
+		sh_eth_write(eth, EDTRR_TRNS, EDTRR);
 
 	/* Wait until packet is transmitted */
 	timeout = TIMEOUT_CNT;
@@ -129,25 +129,24 @@ int sh_eth_recv(struct eth_device *dev)
 	}
 
 	/* Restart the receiver if disabled */
-	if (!(inl(EDRRR(port)) & EDRRR_R))
-		outl(EDRRR_R, EDRRR(port));
+	if (!(sh_eth_read(eth, EDRRR) & EDRRR_R))
+		sh_eth_write(eth, EDRRR_R, EDRRR);
 
 	return len;
 }
 
 static int sh_eth_reset(struct sh_eth_dev *eth)
 {
-	int port = eth->port;
-#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
+#if defined(SH_ETH_TYPE_GETHER)
 	int ret = 0, i;
 
 	/* Start e-dmac transmitter and receiver */
-	outl(EDSR_ENALL, EDSR(port));
+	sh_eth_write(eth, EDSR_ENALL, EDSR);
 
 	/* Perform a software reset and wait for it to complete */
-	outl(EDMR_SRST, EDMR(port));
+	sh_eth_write(eth, EDMR_SRST, EDMR);
 	for (i = 0; i < TIMEOUT_CNT ; i++) {
-		if (!(inl(EDMR(port)) & EDMR_SRST))
+		if (!(sh_eth_read(eth, EDMR) & EDMR_SRST))
 			break;
 		udelay(1000);
 	}
@@ -159,9 +158,9 @@ static int sh_eth_reset(struct sh_eth_dev *eth)
 
 	return ret;
 #else
-	outl(inl(EDMR(port)) | EDMR_SRST, EDMR(port));
+	sh_eth_write(eth, sh_eth_read(eth, EDMR) | EDMR_SRST, EDMR);
 	udelay(3000);
-	outl(inl(EDMR(port)) & ~EDMR_SRST, EDMR(port));
+	sh_eth_write(eth, sh_eth_read(eth, EDMR) & ~EDMR_SRST, EDMR);
 
 	return 0;
 #endif
@@ -207,11 +206,11 @@ static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
 
 	/* Point the controller to the tx descriptor list. Must use physical
 	   addresses */
-	outl(ADDR_TO_PHY(port_info->tx_desc_base), TDLAR(port));
-#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
-	outl(ADDR_TO_PHY(port_info->tx_desc_base), TDFAR(port));
-	outl(ADDR_TO_PHY(cur_tx_desc), TDFXR(port));
-	outl(0x01, TDFFR(port));/* Last discriptor bit */
+	sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR);
+#if defined(SH_ETH_TYPE_GETHER)
+	sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR);
+	sh_eth_write(eth, ADDR_TO_PHY(cur_tx_desc), TDFXR);
+	sh_eth_write(eth, 0x01, TDFFR);/* Last discriptor bit */
 #endif
 
 err:
@@ -275,11 +274,11 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
 	cur_rx_desc->rd0 |= RD_RDLE;
 
 	/* Point the controller to the rx descriptor list */
-	outl(ADDR_TO_PHY(port_info->rx_desc_base), RDLAR(port));
-#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
-	outl(ADDR_TO_PHY(port_info->rx_desc_base), RDFAR(port));
-	outl(ADDR_TO_PHY(cur_rx_desc), RDFXR(port));
-	outl(RDFFR_RDLF, RDFFR(port));
+	sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
+#if defined(SH_ETH_TYPE_GETHER)
+	sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR);
+	sh_eth_write(eth, ADDR_TO_PHY(cur_rx_desc), RDFXR);
+	sh_eth_write(eth, RDFFR_RDLF, RDFFR);
 #endif
 
 	return ret;
@@ -364,49 +363,39 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
 	struct phy_device *phy;
 
 	/* Configure e-dmac registers */
-	outl((inl(EDMR(port)) & ~EMDR_DESC_R) | EDMR_EL, EDMR(port));
-	outl(0, EESIPR(port));
-	outl(0, TRSCER(port));
-	outl(0, TFTR(port));
-	outl((FIFO_SIZE_T | FIFO_SIZE_R), FDR(port));
-	outl(RMCR_RST, RMCR(port));
-#if !defined(CONFIG_CPU_SH7757) && !defined(CONFIG_CPU_SH7724)
-	outl(0, RPADIR(port));
+	sh_eth_write(eth, (sh_eth_read(eth, EDMR) & ~EMDR_DESC_R) | EDMR_EL,
+		     EDMR);
+	sh_eth_write(eth, 0, EESIPR);
+	sh_eth_write(eth, 0, TRSCER);
+	sh_eth_write(eth, 0, TFTR);
+	sh_eth_write(eth, (FIFO_SIZE_T | FIFO_SIZE_R), FDR);
+	sh_eth_write(eth, RMCR_RST, RMCR);
+#if defined(SH_ETH_TYPE_GETHER)
+	sh_eth_write(eth, 0, RPADIR);
 #endif
-	outl((FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR(port));
+	sh_eth_write(eth, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR);
 
 	/* Configure e-mac registers */
-#if defined(CONFIG_CPU_SH7757)
-	outl(ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP |
-		ECSIPR_MPDIP | ECSIPR_ICDIP, ECSIPR(port));
-#else
-	outl(0, ECSIPR(port));
-#endif
+	sh_eth_write(eth, 0, ECSIPR);
 
 	/* Set Mac address */
 	val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 |
 	    dev->enetaddr[2] << 8 | dev->enetaddr[3];
-	outl(val, MAHR(port));
+	sh_eth_write(eth, val, MAHR);
 
 	val = dev->enetaddr[4] << 8 | dev->enetaddr[5];
-	outl(val, MALR(port));
-
-	outl(RFLR_RFL_MIN, RFLR(port));
-#if !defined(CONFIG_CPU_SH7757) && !defined(CONFIG_CPU_SH7724)
-	outl(0, PIPR(port));
-#endif
-#if !defined(CONFIG_CPU_SH7724)
-	outl(APR_AP, APR(port));
-	outl(MPR_MP, MPR(port));
-#endif
-#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
-	outl(TPAUSER_TPAUSE, TPAUSER(port));
-#elif defined(CONFIG_CPU_SH7757)
-	outl(TPAUSER_UNLIMITED, TPAUSER(port));
+	sh_eth_write(eth, val, MALR);
+
+	sh_eth_write(eth, RFLR_RFL_MIN, RFLR);
+#if defined(SH_ETH_TYPE_GETHER)
+	sh_eth_write(eth, 0, PIPR);
+	sh_eth_write(eth, APR_AP, APR);
+	sh_eth_write(eth, MPR_MP, MPR);
+	sh_eth_write(eth, TPAUSER_TPAUSE, TPAUSER);
 #endif
 
 #if defined(CONFIG_CPU_SH7734)
-	outl(CONFIG_SH_ETHER_SH7734_MII, RMII_MII(port));
+	sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
 #endif
 	/* Configure phy */
 	ret = sh_eth_phy_config(eth);
@@ -415,42 +404,47 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
 		goto err_phy_cfg;
 	}
 	phy = port_info->phydev;
-	phy_startup(phy);
+	ret = phy_startup(phy);
+	if (ret) {
+		printf(SHETHER_NAME ": phy startup failure\n");
+		return ret;
+	}
 
 	val = 0;
 
 	/* Set the transfer speed */
 	if (phy->speed == 100) {
 		printf(SHETHER_NAME ": 100Base/");
-#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
-		outl(GECMR_100B, GECMR(port));
+#if defined(SH_ETH_TYPE_GETHER)
+		sh_eth_write(eth, GECMR_100B, GECMR);
 #elif defined(CONFIG_CPU_SH7757)
-		outl(1, RTRATE(port));
+		sh_eth_write(eth, 1, RTRATE);
 #elif defined(CONFIG_CPU_SH7724)
 		val = ECMR_RTM;
 #endif
 	} else if (phy->speed == 10) {
 		printf(SHETHER_NAME ": 10Base/");
-#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
-		outl(GECMR_10B, GECMR(port));
+#if defined(SH_ETH_TYPE_GETHER)
+		sh_eth_write(eth, GECMR_10B, GECMR);
 #elif defined(CONFIG_CPU_SH7757)
-		outl(0, RTRATE(port));
+		sh_eth_write(eth, 0, RTRATE);
 #endif
 	}
-#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
+#if defined(SH_ETH_TYPE_GETHER)
 	else if (phy->speed == 1000) {
 		printf(SHETHER_NAME ": 1000Base/");
-		outl(GECMR_1000B, GECMR(port));
+		sh_eth_write(eth, GECMR_1000B, GECMR);
 	}
 #endif
 
 	/* Check if full duplex mode is supported by the phy */
 	if (phy->duplex) {
 		printf("Full\n");
-		outl(val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM), ECMR(port));
+		sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM),
+			     ECMR);
 	} else {
 		printf("Half\n");
-		outl(val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE),  ECMR(port));
+		sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR);
 	}
 
 	return ret;
@@ -465,12 +459,12 @@ static void sh_eth_start(struct sh_eth_dev *eth)
 	 * Enable the e-dmac receiver only. The transmitter will be enabled when
 	 * we have something to transmit
 	 */
-	outl(EDRRR_R, EDRRR(eth->port));
+	sh_eth_write(eth, EDRRR_R, EDRRR);
 }
 
 static void sh_eth_stop(struct sh_eth_dev *eth)
 {
-	outl(~EDRRR_R, EDRRR(eth->port));
+	sh_eth_write(eth, ~EDRRR_R, EDRRR);
 }
 
 int sh_eth_init(struct eth_device *dev, bd_t *bd)
@@ -574,9 +568,8 @@ static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
 static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
 {
 	struct sh_eth_dev *eth = bus->priv;
-	int port = eth->port;
 
-	outl(inl(PIR(port)) | PIR_MMD, PIR(port));
+	sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MMD, PIR);
 
 	return 0;
 }
@@ -584,9 +577,8 @@ static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
 static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
 {
 	struct sh_eth_dev *eth = bus->priv;
-	int port = eth->port;
 
-	outl(inl(PIR(port)) & ~PIR_MMD, PIR(port));
+	sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MMD, PIR);
 
 	return 0;
 }
@@ -594,12 +586,11 @@ static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
 static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
 {
 	struct sh_eth_dev *eth = bus->priv;
-	int port = eth->port;
 
 	if (v)
-		outl(inl(PIR(port)) | PIR_MDO, PIR(port));
+		sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDO, PIR);
 	else
-		outl(inl(PIR(port)) & ~PIR_MDO, PIR(port));
+		sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDO, PIR);
 
 	return 0;
 }
@@ -607,9 +598,8 @@ static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
 static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
 {
 	struct sh_eth_dev *eth = bus->priv;
-	int port = eth->port;
 
-	*v = (inl(PIR(port)) & PIR_MDI) >> 3;
+	*v = (sh_eth_read(eth, PIR) & PIR_MDI) >> 3;
 
 	return 0;
 }
@@ -617,12 +607,11 @@ static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
 static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
 {
 	struct sh_eth_dev *eth = bus->priv;
-	int port = eth->port;
 
 	if (v)
-		outl(inl(PIR(port)) | PIR_MDC, PIR(port));
+		sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDC, PIR);
 	else
-		outl(inl(PIR(port)) & ~PIR_MDC, PIR(port));
+		sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDC, PIR);
 
 	return 0;
 }

drivers/net/sh_eth.h

@@ -97,143 +97,208 @@ struct sh_eth_dev {
 	struct sh_eth_info port_info[MAX_PORT_NUM];
 };
 
-/* Register Address */
-#ifdef CONFIG_CPU_SH7763
-#define BASE_IO_ADDR	0xfee00000
+/* from linux/drivers/net/ethernet/renesas/sh_eth.h */
+enum {
+	/* E-DMAC registers */
+	EDSR = 0,
+	EDMR,
+	EDTRR,
+	EDRRR,
+	EESR,
+	EESIPR,
+	TDLAR,
+	TDFAR,
+	TDFXR,
+	TDFFR,
+	RDLAR,
+	RDFAR,
+	RDFXR,
+	RDFFR,
+	TRSCER,
+	RMFCR,
+	TFTR,
+	FDR,
+	RMCR,
+	EDOCR,
+	TFUCR,
+	RFOCR,
+	FCFTR,
+	RPADIR,
+	TRIMD,
+	RBWAR,
+	TBRAR,
+
+	/* Ether registers */
+	ECMR,
+	ECSR,
+	ECSIPR,
+	PIR,
+	PSR,
+	RDMLR,
+	PIPR,
+	RFLR,
+	IPGR,
+	APR,
+	MPR,
+	PFTCR,
+	PFRCR,
+	RFCR,
+	RFCF,
+	TPAUSER,
+	TPAUSECR,
+	BCFR,
+	BCFRR,
+	GECMR,
+	BCULR,
+	MAHR,
+	MALR,
+	TROCR,
+	CDCR,
+	LCCR,
+	CNDCR,
+	CEFCR,
+	FRECR,
+	TSFRCR,
+	TLFRCR,
+	CERCR,
+	CEECR,
+	MAFCR,
+	RTRATE,
+	CSMR,
+	RMII_MII,
+
+	/* This value must be written at last. */
+	SH_ETH_MAX_REGISTER_OFFSET,
+};
 
-#define EDSR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0000)
-
-#define TDLAR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0010)
-#define TDFAR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0014)
-#define TDFXR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0018)
-#define TDFFR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x001c)
-
-#define RDLAR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0030)
-#define RDFAR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0034)
-#define RDFXR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0038)
-#define RDFFR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x003c)
-
-#define EDMR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0400)
-#define EDTRR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0408)
-#define EDRRR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0410)
-#define EESR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0428)
-#define EESIPR(port)	(BASE_IO_ADDR + 0x800 * (port) + 0x0430)
-#define TRSCER(port)	(BASE_IO_ADDR + 0x800 * (port) + 0x0438)
-#define TFTR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0448)
-#define FDR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0450)
-#define RMCR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0458)
-#define RPADIR(port)	(BASE_IO_ADDR + 0x800 * (port) + 0x0460)
-#define FCFTR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0468)
-#define ECMR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0500)
-#define RFLR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0508)
-#define ECSIPR(port)	(BASE_IO_ADDR + 0x800 * (port) + 0x0518)
-#define PIR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0520)
-#define PIPR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x052c)
-#define APR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0554)
-#define MPR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0558)
-#define TPAUSER(port)	(BASE_IO_ADDR + 0x800 * (port) + 0x0564)
-#define GECMR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x05b0)
-#define MALR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x05c8)
-#define MAHR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x05c0)
+static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
+	[EDSR]	= 0x0000,
+	[EDMR]	= 0x0400,
+	[EDTRR]	= 0x0408,
+	[EDRRR]	= 0x0410,
+	[EESR]	= 0x0428,
+	[EESIPR]	= 0x0430,
+	[TDLAR]	= 0x0010,
+	[TDFAR]	= 0x0014,
+	[TDFXR]	= 0x0018,
+	[TDFFR]	= 0x001c,
+	[RDLAR]	= 0x0030,
+	[RDFAR]	= 0x0034,
+	[RDFXR]	= 0x0038,
+	[RDFFR]	= 0x003c,
+	[TRSCER]	= 0x0438,
+	[RMFCR]	= 0x0440,
+	[TFTR]	= 0x0448,
+	[FDR]	= 0x0450,
+	[RMCR]	= 0x0458,
+	[RPADIR]	= 0x0460,
+	[FCFTR]	= 0x0468,
+	[CSMR] = 0x04E4,
+
+	[ECMR]	= 0x0500,
+	[ECSR]	= 0x0510,
+	[ECSIPR]	= 0x0518,
+	[PIR]	= 0x0520,
+	[PSR]	= 0x0528,
+	[PIPR]	= 0x052c,
+	[RFLR]	= 0x0508,
+	[APR]	= 0x0554,
+	[MPR]	= 0x0558,
+	[PFTCR]	= 0x055c,
+	[PFRCR]	= 0x0560,
+	[TPAUSER]	= 0x0564,
+	[GECMR]	= 0x05b0,
+	[BCULR]	= 0x05b4,
+	[MAHR]	= 0x05c0,
+	[MALR]	= 0x05c8,
+	[TROCR]	= 0x0700,
+	[CDCR]	= 0x0708,
+	[LCCR]	= 0x0710,
+	[CEFCR]	= 0x0740,
+	[FRECR]	= 0x0748,
+	[TSFRCR]	= 0x0750,
+	[TLFRCR]	= 0x0758,
+	[RFCR]	= 0x0760,
+	[CERCR]	= 0x0768,
+	[CEECR]	= 0x0770,
+	[MAFCR]	= 0x0778,
+	[RMII_MII] =  0x0790,
+};
 
+static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
+	[ECMR]	= 0x0100,
+	[RFLR]	= 0x0108,
+	[ECSR]	= 0x0110,
+	[ECSIPR]	= 0x0118,
+	[PIR]	= 0x0120,
+	[PSR]	= 0x0128,
+	[RDMLR]	= 0x0140,
+	[IPGR]	= 0x0150,
+	[APR]	= 0x0154,
+	[MPR]	= 0x0158,
+	[TPAUSER]	= 0x0164,
+	[RFCF]	= 0x0160,
+	[TPAUSECR]	= 0x0168,
+	[BCFRR]	= 0x016c,
+	[MAHR]	= 0x01c0,
+	[MALR]	= 0x01c8,
+	[TROCR]	= 0x01d0,
+	[CDCR]	= 0x01d4,
+	[LCCR]	= 0x01d8,
+	[CNDCR]	= 0x01dc,
+	[CEFCR]	= 0x01e4,
+	[FRECR]	= 0x01e8,
+	[TSFRCR]	= 0x01ec,
+	[TLFRCR]	= 0x01f0,
+	[RFCR]	= 0x01f4,
+	[MAFCR]	= 0x01f8,
+	[RTRATE]	= 0x01fc,
+
+	[EDMR]	= 0x0000,
+	[EDTRR]	= 0x0008,
+	[EDRRR]	= 0x0010,
+	[TDLAR]	= 0x0018,
+	[RDLAR]	= 0x0020,
+	[EESR]	= 0x0028,
+	[EESIPR]	= 0x0030,
+	[TRSCER]	= 0x0038,
+	[RMFCR]	= 0x0040,
+	[TFTR]	= 0x0048,
+	[FDR]	= 0x0050,
+	[RMCR]	= 0x0058,
+	[TFUCR]	= 0x0064,
+	[RFOCR]	= 0x0068,
+	[FCFTR]	= 0x0070,
+	[RPADIR]	= 0x0078,
+	[TRIMD]	= 0x007c,
+	[RBWAR]	= 0x00c8,
+	[RDFAR]	= 0x00cc,
+	[TBRAR]	= 0x00d4,
+	[TDFAR]	= 0x00d8,
+};
+
+/* Register Address */
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
+#define SH_ETH_TYPE_GETHER
+#define BASE_IO_ADDR	0xfee00000
 #elif defined(CONFIG_CPU_SH7757)
+#if defined(CONFIG_SH_ETHER_USE_GETHER)
+#define SH_ETH_TYPE_GETHER
+#define BASE_IO_ADDR	0xfee00000
+#else
+#define SH_ETH_TYPE_ETHER
 #define BASE_IO_ADDR	0xfef00000
-
-#define TDLAR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0018)
-#define RDLAR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0020)
-
-#define EDMR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0000)
-#define EDTRR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0008)
-#define EDRRR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0010)
-#define EESR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0028)
-#define EESIPR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0030)
-#define TRSCER(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0038)
-#define TFTR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0048)
-#define FDR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0050)
-#define RMCR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0058)
-#define FCFTR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0070)
-#define ECMR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0100)
-#define RFLR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0108)
-#define ECSIPR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0118)
-#define PIR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0120)
-#define APR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0154)
-#define MPR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0158)
-#define TPAUSER(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0164)
-#define MAHR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x01c0)
-#define MALR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x01c8)
-#define RTRATE(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x01fc)
-
+#endif
 #elif defined(CONFIG_CPU_SH7724)
+#define SH_ETH_TYPE_ETHER
 #define BASE_IO_ADDR	0xA4600000
-
-#define TDLAR(port)		(BASE_IO_ADDR + 0x0018)
-#define RDLAR(port)		(BASE_IO_ADDR + 0x0020)
-
-#define EDMR(port)		(BASE_IO_ADDR + 0x0000)
-#define EDTRR(port)		(BASE_IO_ADDR + 0x0008)
-#define EDRRR(port)		(BASE_IO_ADDR + 0x0010)
-#define EESR(port)		(BASE_IO_ADDR + 0x0028)
-#define EESIPR(port)	(BASE_IO_ADDR + 0x0030)
-#define TRSCER(port)	(BASE_IO_ADDR + 0x0038)
-#define TFTR(port)		(BASE_IO_ADDR + 0x0048)
-#define FDR(port)		(BASE_IO_ADDR + 0x0050)
-#define RMCR(port)		(BASE_IO_ADDR + 0x0058)
-#define FCFTR(port)		(BASE_IO_ADDR + 0x0070)
-#define ECMR(port)		(BASE_IO_ADDR + 0x0100)
-#define RFLR(port)		(BASE_IO_ADDR + 0x0108)
-#define ECSIPR(port)	(BASE_IO_ADDR + 0x0118)
-#define PIR(port)		(BASE_IO_ADDR + 0x0120)
-#define APR(port)		(BASE_IO_ADDR + 0x0154)
-#define MPR(port)		(BASE_IO_ADDR + 0x0158)
-#define TPAUSER(port)	(BASE_IO_ADDR + 0x0164)
-#define MAHR(port)		(BASE_IO_ADDR + 0x01c0)
-#define MALR(port)		(BASE_IO_ADDR + 0x01c8)
-
-#elif defined(CONFIG_CPU_SH7734)
-#define BASE_IO_ADDR	0xFEE00000
-
-#define EDSR(port)		(BASE_IO_ADDR)
-
-#define TDLAR(port)		(BASE_IO_ADDR + 0x0010)
-#define TDFAR(port)		(BASE_IO_ADDR + 0x0014)
-#define TDFXR(port)		(BASE_IO_ADDR + 0x0018)
-#define TDFFR(port)		(BASE_IO_ADDR + 0x001c)
-#define RDLAR(port)		(BASE_IO_ADDR + 0x0030)
-#define RDFAR(port)		(BASE_IO_ADDR + 0x0034)
-#define RDFXR(port)		(BASE_IO_ADDR + 0x0038)
-#define RDFFR(port)		(BASE_IO_ADDR + 0x003c)
-
-#define EDMR(port)		(BASE_IO_ADDR + 0x0400)
-#define EDTRR(port)		(BASE_IO_ADDR + 0x0408)
-#define EDRRR(port)		(BASE_IO_ADDR + 0x0410)
-#define EESR(port)		(BASE_IO_ADDR + 0x0428)
-#define EESIPR(port)	(BASE_IO_ADDR + 0x0430)
-#define TRSCER(port)	(BASE_IO_ADDR + 0x0438)
-#define TFTR(port)		(BASE_IO_ADDR + 0x0448)
-#define FDR(port)		(BASE_IO_ADDR + 0x0450)
-#define RMCR(port)		(BASE_IO_ADDR + 0x0458)
-#define RPADIR(port)	(BASE_IO_ADDR + 0x0460)
-#define FCFTR(port)		(BASE_IO_ADDR + 0x0468)
-#define ECMR(port)		(BASE_IO_ADDR + 0x0500)
-#define RFLR(port)		(BASE_IO_ADDR + 0x0508)
-#define ECSIPR(port)	(BASE_IO_ADDR + 0x0518)
-#define PIR(port)		(BASE_IO_ADDR + 0x0520)
-#define PIPR(port)		(BASE_IO_ADDR + 0x052c)
-#define APR(port)		(BASE_IO_ADDR + 0x0554)
-#define MPR(port)		(BASE_IO_ADDR + 0x0558)
-#define TPAUSER(port)	(BASE_IO_ADDR + 0x0564)
-#define GECMR(port)		(BASE_IO_ADDR + 0x05b0)
-#define MAHR(port)		(BASE_IO_ADDR + 0x05C0)
-#define MALR(port)		(BASE_IO_ADDR + 0x05C8)
-#define RMII_MII(port)  (BASE_IO_ADDR + 0x0790)
-
 #endif
 
 /*
  * Register's bits
  * Copy from Linux driver source code
  */
-#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
+#if defined(SH_ETH_TYPE_GETHER)
 /* EDSR */
 enum EDSR_BIT {
 	EDSR_ENT = 0x01, EDSR_ENR = 0x02,
@@ -244,15 +309,15 @@ enum EDSR_BIT {
 /* EDMR */
 enum DMAC_M_BIT {
 	EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
-#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
+#if defined(SH_ETH_TYPE_GETHER)
 	EDMR_SRST	= 0x03, /* Receive/Send reset */
 	EMDR_DESC_R	= 0x30, /* Descriptor reserve size */
 	EDMR_EL		= 0x40, /* Litte endian */
-#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7724)
+#elif defined(SH_ETH_TYPE_ETHER)
 	EDMR_SRST	= 0x01,
 	EMDR_DESC_R	= 0x30, /* Descriptor reserve size */
 	EDMR_EL		= 0x40, /* Litte endian */
-#else /* CONFIG_CPU_SH7763 */
+#else
 	EDMR_SRST = 0x01,
 #endif
 };
@@ -262,7 +327,7 @@ enum DMAC_M_BIT {
 
 /* EDTRR */
 enum DMAC_T_BIT {
-#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
+#if defined(SH_ETH_TYPE_GETHER)
 	EDTRR_TRNS = 0x03,
 #else
 	EDTRR_TRNS = 0x01,
@@ -271,7 +336,11 @@ enum DMAC_T_BIT {
 
 /* GECMR */
 enum GECMR_BIT {
+#if defined(CONFIG_CPU_SH7757)
+	GECMR_1000B = 0x20, GECMR_100B = 0x01, GECMR_10B = 0x00,
+#else
 	GECMR_1000B = 0x01, GECMR_100B = 0x04, GECMR_10B = 0x00,
+#endif
 };
 
 /* EDRRR*/
@@ -302,7 +371,7 @@ enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
 /* EESR */
 enum EESR_BIT {
 
-#if defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7757)
+#if defined(SH_ETH_TYPE_ETHER)
 	EESR_TWB  = 0x40000000,
 #else
 	EESR_TWB  = 0xC0000000,
@@ -312,14 +381,14 @@ enum EESR_BIT {
 #endif
 	EESR_TABT = 0x04000000,
 	EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000,
-#if defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7757)
+#if defined(SH_ETH_TYPE_ETHER)
 	EESR_ADE  = 0x00800000,
 #endif
 	EESR_ECI  = 0x00400000,
 	EESR_FTC  = 0x00200000, EESR_TDE  = 0x00100000,
 	EESR_TFE  = 0x00080000, EESR_FRC  = 0x00040000,
 	EESR_RDE  = 0x00020000, EESR_RFE  = 0x00010000,
-#if defined(CONFIG_CPU_SH7724) && !defined(CONFIG_CPU_SH7757)
+#if defined(SH_ETH_TYPE_ETHER)
 	EESR_CND  = 0x00000800,
 #endif
 	EESR_DLC  = 0x00000400,
@@ -331,7 +400,7 @@ enum EESR_BIT {
 };
 
 
-#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
+#if defined(SH_ETH_TYPE_GETHER)
 # define TX_CHECK (EESR_TC1 | EESR_FTC)
 # define EESR_ERR_CHECK	(EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
 		| EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI)
@@ -391,8 +460,7 @@ enum FCFTR_BIT {
 
 /* Transfer descriptor bit */
 enum TD_STS_BIT {
-#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7757) \
-		|| defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7734)
+#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_ETHER)
 	TD_TACT = 0x80000000,
 #else
 	TD_TACT = 0x7fffffff,
@@ -408,7 +476,7 @@ enum TD_STS_BIT {
 enum RECV_RST_BIT { RMCR_RST = 0x01, };
 /* ECMR */
 enum FELIC_MODE_BIT {
-#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
+#if defined(SH_ETH_TYPE_GETHER)
 	ECMR_TRCCM=0x04000000, ECMR_RCSC= 0x00800000, ECMR_DPAD= 0x00200000,
 	ECMR_RZPF = 0x00100000,
 #endif
@@ -423,12 +491,10 @@ enum FELIC_MODE_BIT {
 
 };
 
-#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
+#if defined(SH_ETH_TYPE_GETHER)
 #define ECMR_CHG_DM	(ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | ECMR_RXF | \
 						ECMR_TXF | ECMR_MCT)
-#elif CONFIG_CPU_SH7757
-#define ECMR_CHG_DM	(ECMR_ZPF)
-#elif CONFIG_CPU_SH7724
+#elif defined(SH_ETH_TYPE_ETHER)
 #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF)
 #else
 #define ECMR_CHG_DM	(ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT)
@@ -436,14 +502,14 @@ enum FELIC_MODE_BIT {
 
 /* ECSR */
 enum ECSR_STATUS_BIT {
-#if defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7757)
+#if defined(SH_ETH_TYPE_ETHER)
 	ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
 #endif
 	ECSR_LCHNG = 0x04,
 	ECSR_MPD = 0x02, ECSR_ICD = 0x01,
 };
 
-#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
+#if defined(SH_ETH_TYPE_GETHER)
 # define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP)
 #else
 # define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \
@@ -452,10 +518,10 @@ enum ECSR_STATUS_BIT {
 
 /* ECSIPR */
 enum ECSIPR_STATUS_MASK_BIT {
-#if defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7757)
+#if defined(SH_ETH_TYPE_ETHER)
 	ECSIPR_BRCRXIP = 0x20,
 	ECSIPR_PSRTOIP = 0x10,
-#elif defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
+#elif defined(SH_ETY_TYPE_GETHER)
 	ECSIPR_PSRTOIP = 0x10,
 	ECSIPR_PHYIP = 0x08,
 #endif
@@ -464,7 +530,7 @@ enum ECSIPR_STATUS_MASK_BIT {
 	ECSIPR_ICDIP = 0x01,
 };
 
-#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
+#if defined(SH_ETH_TYPE_GETHER)
 # define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
 #else
 # define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \
@@ -473,20 +539,12 @@ enum ECSIPR_STATUS_MASK_BIT {
 
 /* APR */
 enum APR_BIT {
-#ifdef CONFIG_CPU_SH7757
-	APR_AP = 0x00000001,
-#else
 	APR_AP = 0x00000004,
-#endif
 };
 
 /* MPR */
 enum MPR_BIT {
-#ifdef CONFIG_CPU_SH7757
-	MPR_MP = 0x00000001,
-#else
 	MPR_MP = 0x00000006,
-#endif
 };
 
 /* TRSCER */
@@ -503,7 +561,7 @@ enum RPADIR_BIT {
 	RPADIR_PADR = 0x0003f,
 };
 
-#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
+#if defined(SH_ETH_TYPE_GETHER)
 # define RPADIR_INIT (0x00)
 #else
 # define RPADIR_INIT (RPADIR_PADS1)
@@ -513,3 +571,28 @@ enum RPADIR_BIT {
 enum FIFO_SIZE_BIT {
 	FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007,
 };
+
+static inline unsigned long sh_eth_reg_addr(struct sh_eth_dev *eth,
+					    int enum_index)
+{
+#if defined(SH_ETH_TYPE_GETHER)
+	const u16 *reg_offset = sh_eth_offset_gigabit;
+#elif defined(SH_ETH_TYPE_ETHER)
+	const u16 *reg_offset = sh_eth_offset_fast_sh4;
+#else
+#error
+#endif
+	return BASE_IO_ADDR + reg_offset[enum_index] + 0x800 * eth->port;
+}
+
+static inline void sh_eth_write(struct sh_eth_dev *eth, unsigned long data,
+				int enum_index)
+{
+	outl(data, sh_eth_reg_addr(eth, enum_index));
+}
+
+static inline unsigned long sh_eth_read(struct sh_eth_dev *eth,
+					int enum_index)
+{
+	return inl(sh_eth_reg_addr(eth, enum_index));
+}

drivers/net/tsec.c

@@ -480,6 +480,7 @@ static int tsec_init(struct eth_device *dev, bd_t * bd)
 	int i;
 	struct tsec_private *priv = (struct tsec_private *)dev->priv;
 	tsec_t *regs = priv->regs;
+	int ret;
 
 	/* Make sure the controller is stopped */
 	tsec_halt(dev);
@@ -511,7 +512,12 @@ static int tsec_init(struct eth_device *dev, bd_t * bd)
 	startup_tsec(dev);
 
 	/* Start up the PHY */
-	phy_startup(priv->phydev);
+	ret = phy_startup(priv->phydev);
+	if (ret) {
+		printf("Could not initialize PHY %s\n",
+		       priv->phydev->dev->name);
+		return ret;
+	}
 
 	adjust_link(priv, priv->phydev);
 

drivers/net/xilinx_axi_emac.c

@@ -272,7 +272,11 @@ static int setup_phy(struct eth_device *dev)
 	phydev->advertising = phydev->supported;
 	priv->phydev = phydev;
 	phy_config(phydev);
-	phy_startup(phydev);
+	if (phy_startup(phydev)) {
+		printf("axiemac: could not initialize PHY %s\n",
+		       phydev->dev->name);
+		return 0;
+	}
 
 	switch (phydev->speed) {
 	case 1000:

drivers/net/xilinx_ll_temac.c

@@ -232,6 +232,7 @@ static void ll_temac_halt(struct eth_device *dev)
 static int ll_temac_init(struct eth_device *dev, bd_t *bis)
 {
 	struct ll_temac *ll_temac = dev->priv;
+	int ret;
 
 	printf("%s: Xilinx XPS LocalLink Tri-Mode Ether MAC #%d at 0x%08X.\n",
 		dev->name, dev->index, dev->iobase);
@@ -240,7 +241,12 @@ static int ll_temac_init(struct eth_device *dev, bd_t *bis)
 		return -1;
 
 	/* Start up the PHY */
-	phy_startup(ll_temac->phydev);
+	ret = phy_startup(ll_temac->phydev);
+	if (ret) {
+		printf("%s: Could not initialize PHY %s\n",
+		       dev->name, ll_temac->phydev->dev->name);
+		return ret;
+	}
 
 	if (!ll_temac_adjust_link(dev)) {
 		ll_temac_halt(dev);

drivers/usb/eth/asix.c

@@ -168,27 +168,28 @@ static inline int asix_set_hw_mii(struct ueth_data *dev)
 
 static int asix_mdio_read(struct ueth_data *dev, int phy_id, int loc)
 {
-	__le16 res;
+	ALLOC_CACHE_ALIGN_BUFFER(__le16, res, 1);
 
 	asix_set_sw_mii(dev);
-	asix_read_cmd(dev, AX_CMD_READ_MII_REG, phy_id, (__u16)loc, 2, &res);
+	asix_read_cmd(dev, AX_CMD_READ_MII_REG, phy_id, (__u16)loc, 2, res);
 	asix_set_hw_mii(dev);
 
 	debug("asix_mdio_read() phy_id=0x%02x, loc=0x%02x, returns=0x%04x\n",
-			phy_id, loc, le16_to_cpu(res));
+			phy_id, loc, le16_to_cpu(*res));
 
-	return le16_to_cpu(res);
+	return le16_to_cpu(*res);
 }
 
 static void
 asix_mdio_write(struct ueth_data *dev, int phy_id, int loc, int val)
 {
-	__le16 res = cpu_to_le16(val);
+	ALLOC_CACHE_ALIGN_BUFFER(__le16, res, 1);
+	*res = cpu_to_le16(val);
 
 	debug("asix_mdio_write() phy_id=0x%02x, loc=0x%02x, val=0x%04x\n",
 			phy_id, loc, val);
 	asix_set_sw_mii(dev);
-	asix_write_cmd(dev, AX_CMD_WRITE_MII_REG, phy_id, (__u16)loc, 2, &res);
+	asix_write_cmd(dev, AX_CMD_WRITE_MII_REG, phy_id, (__u16)loc, 2, res);
 	asix_set_hw_mii(dev);
 }
 
@@ -210,7 +211,8 @@ static int asix_sw_reset(struct ueth_data *dev, u8 flags)
 
 static inline int asix_get_phy_addr(struct ueth_data *dev)
 {
-	u8 buf[2];
+	ALLOC_CACHE_ALIGN_BUFFER(u8, buf, 2);
+
 	int ret = asix_read_cmd(dev, AX_CMD_READ_PHY_ID, 0, 0, 2, buf);
 
 	debug("asix_get_phy_addr()\n");
@@ -242,13 +244,14 @@ static int asix_write_medium_mode(struct ueth_data *dev, u16 mode)
 
 static u16 asix_read_rx_ctl(struct ueth_data *dev)
 {
-	__le16 v;
-	int ret = asix_read_cmd(dev, AX_CMD_READ_RX_CTL, 0, 0, 2, &v);
+	ALLOC_CACHE_ALIGN_BUFFER(__le16, v, 1);
+
+	int ret = asix_read_cmd(dev, AX_CMD_READ_RX_CTL, 0, 0, 2, v);
 
 	if (ret < 0)
 		debug("Error reading RX_CTL register: %02x\n", ret);
 	else
-		ret = le16_to_cpu(v);
+		ret = le16_to_cpu(*v);
 	return ret;
 }
 
@@ -313,7 +316,7 @@ static int mii_nway_restart(struct ueth_data *dev)
 static int asix_init(struct eth_device *eth, bd_t *bd)
 {
 	int embd_phy;
-	unsigned char buf[ETH_ALEN];
+	ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, ETH_ALEN);
 	u16 rx_ctl;
 	struct ueth_data	*dev = (struct ueth_data *)eth->priv;
 	int timeout = 0;
@@ -425,7 +428,8 @@ static int asix_send(struct eth_device *eth, void *packet, int length)
 	int err;
 	u32 packet_len;
 	int actual_len;
-	unsigned char msg[PKTSIZE + sizeof(packet_len)];
+	ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg,
+		PKTSIZE + sizeof(packet_len));
 
 	debug("** %s(), len %d\n", __func__, length);
 
@@ -452,7 +456,7 @@ static int asix_send(struct eth_device *eth, void *packet, int length)
 static int asix_recv(struct eth_device *eth)
 {
 	struct ueth_data *dev = (struct ueth_data *)eth->priv;
-	static unsigned char  recv_buf[AX_RX_URB_SIZE];
+	ALLOC_CACHE_ALIGN_BUFFER(unsigned char, recv_buf, AX_RX_URB_SIZE);
 	unsigned char *buf_ptr;
 	int err;
 	int actual_len;

include/configs/mx6qsabrelite.h

@@ -104,6 +104,7 @@
 #define CONFIG_FEC_MXC_PHYADDR		6
 #define CONFIG_PHYLIB
 #define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9021
 
 /* USB Configs */
 #define CONFIG_CMD_USB

net/eth.c

@@ -62,6 +62,15 @@ int eth_getenv_enetaddr_by_index(const char *base_name, int index,
 	return eth_getenv_enetaddr(enetvar, enetaddr);
 }
 
+static inline int eth_setenv_enetaddr_by_index(const char *base_name, int index,
+				 uchar *enetaddr)
+{
+	char enetvar[32];
+	sprintf(enetvar, index ? "%s%daddr" : "%saddr", base_name, index);
+	return eth_setenv_enetaddr(enetvar, enetaddr);
+}
+
+
 static int eth_mac_skip(int index)
 {
 	char enetvar[15];
@@ -205,6 +214,11 @@ int eth_write_hwaddr(struct eth_device *dev, const char *base_name,
 		}
 
 		memcpy(dev->enetaddr, env_enetaddr, 6);
+	} else if (is_valid_ether_addr(dev->enetaddr)) {
+		eth_setenv_enetaddr_by_index(base_name, eth_number,
+					     dev->enetaddr);
+		printf("\nWarning: %s using MAC address from net device\n",
+			dev->name);
 	}
 
 	if (dev->write_hwaddr &&

net/nfs.c

@@ -31,7 +31,11 @@
 
 #define HASHES_PER_LINE 65	/* Number of "loading" hashes per line	*/
 #define NFS_RETRY_COUNT 30
-#define NFS_TIMEOUT 2000UL
+#ifndef CONFIG_NFS_TIMEOUT
+# define NFS_TIMEOUT 2000UL
+#else
+# define NFS_TIMEOUT CONFIG_NFS_TIMEOUT
+#endif
 
 static int fs_mounted;
 static unsigned long rpc_id;