Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'

arch/arm/cpu/armv7/mx5/clock.c

@@ -928,7 +928,9 @@ int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	printf("IPG        %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
 	printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
 	printf("DDR        %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
-
+#ifdef CONFIG_MXC_SPI
+	printf("CSPI       %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
+#endif
 	return 0;
 }
 

arch/arm/cpu/armv7/mx5/lowlevel_init.S

@@ -396,7 +396,7 @@ ENTRY(lowlevel_init)
 	mov r10, lr
 	mov r4, #0	/* Fix R4 to 0 */
 
-#if defined(CONFIG_MX51)
+#if defined(CONFIG_SYS_MAIN_PWR_ON)
 	ldr r0, =GPIO1_BASE_ADDR
 	ldr r1, [r0, #0x0]
 	orr r1, r1, #1 << 23

arch/arm/cpu/armv7/mx6/clock.c

@@ -404,7 +404,9 @@ int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	printf("\n");
 	printf("IPG        %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
 	printf("UART       %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
+#ifdef CONFIG_MXC_SPI
 	printf("CSPI       %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
+#endif
 	printf("AHB        %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
 	printf("AXI        %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
 	printf("DDR        %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);

arch/arm/include/asm/arch-mx25/imx-regs.h

@@ -241,6 +241,7 @@ struct aips_regs {
 #define IMX_RTIC_BASE		(0x53FEC000)
 #define IMX_IIM_BASE		(0x53FF0000)
 #define IMX_USB_BASE		(0x53FF4000)
+#define IMX_USB_PORT_OFFSET	0x200
 #define IMX_CSI_BASE		(0x53FF8000)
 #define IMX_DRYICE_BASE		(0x53FFC000)
 

arch/arm/include/asm/arch-mx31/imx-regs.h

@@ -895,32 +895,7 @@ struct esdc_regs {
 
 #define MX31_AIPS1_BASE_ADDR	0x43f00000
 #define IMX_USB_BASE		(MX31_AIPS1_BASE_ADDR + 0x88000)
-
-/* USB portsc */
-/* values for portsc field */
-#define MXC_EHCI_PHY_LOW_POWER_SUSPEND	(1 << 23)
-#define MXC_EHCI_FORCE_FS		(1 << 24)
-#define MXC_EHCI_UTMI_8BIT		(0 << 28)
-#define MXC_EHCI_UTMI_16BIT		(1 << 28)
-#define MXC_EHCI_SERIAL			(1 << 29)
-#define MXC_EHCI_MODE_UTMI		(0 << 30)
-#define MXC_EHCI_MODE_PHILIPS		(1 << 30)
-#define MXC_EHCI_MODE_ULPI		(2 << 30)
-#define MXC_EHCI_MODE_SERIAL		(3 << 30)
-
-/* values for flags field */
-#define MXC_EHCI_INTERFACE_DIFF_UNI	(0 << 0)
-#define MXC_EHCI_INTERFACE_DIFF_BI	(1 << 0)
-#define MXC_EHCI_INTERFACE_SINGLE_UNI	(2 << 0)
-#define MXC_EHCI_INTERFACE_SINGLE_BI	(3 << 0)
-#define MXC_EHCI_INTERFACE_MASK		(0xf)
-
-#define MXC_EHCI_POWER_PINS_ENABLED	(1 << 5)
-#define MXC_EHCI_TTL_ENABLED		(1 << 6)
-
-#define MXC_EHCI_INTERNAL_PHY		(1 << 7)
-#define MXC_EHCI_IPPUE_DOWN		(1 << 8)
-#define MXC_EHCI_IPPUE_UP		(1 << 9)
+#define IMX_USB_PORT_OFFSET	0x200
 
 /*
  * CSPI register definitions

arch/arm/include/asm/arch-mx35/imx-regs.h

@@ -84,6 +84,8 @@
 #define PWM_BASE_ADDR		0x53FE0000
 #define RTIC_BASE_ADDR		0x53FEC000
 #define IIM_BASE_ADDR		0x53FF0000
+#define IMX_USB_BASE		0x53FF4000
+#define IMX_USB_PORT_OFFSET	0x400
 
 #define IMX_CCM_BASE		CCM_BASE_ADDR
 

arch/arm/include/asm/arch-mx5/mx5x_pins.h

@@ -802,22 +802,22 @@ typedef enum iomux_input_select {
 	MX53_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT,
 	MX53_CSPI_IPP_IND_MISO_SELECT_INPUT,
 	MX53_CSPI_IPP_IND_MOSI_SELECT_INPUT,
+	MX53_CSPI_IPP_IND_SS_B_0_SELECT_INPUT,
 	MX53_CSPI_IPP_IND_SS_B_1_SELECT_INPUT,
 	MX53_CSPI_IPP_IND_SS_B_2_SELECT_INPUT,
 	MX53_CSPI_IPP_IND_SS_B_3_SELECT_INPUT,
-	MX53_CSPI_IPP_IND_SS_B_4_SELECT_INPUT,
 	MX53_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT,
 	MX53_ECSPI1_IPP_IND_MISO_SELECT_INPUT,
 	MX53_ECSPI1_IPP_IND_MOSI_SELECT_INPUT,
+	MX53_ECSPI1_IPP_IND_SS_B_0_SELECT_INPUT,
 	MX53_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT,
 	MX53_ECSPI1_IPP_IND_SS_B_2_SELECT_INPUT,
 	MX53_ECSPI1_IPP_IND_SS_B_3_SELECT_INPUT,
-	MX53_ECSPI1_IPP_IND_SS_B_4_SELECT_INPUT,
 	MX53_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT,
 	MX53_ECSPI2_IPP_IND_MISO_SELECT_INPUT,
 	MX53_ECSPI2_IPP_IND_MOSI_SELECT_INPUT,
+	MX53_ECSPI2_IPP_IND_SS_B_0_SELECT_INPUT,
 	MX53_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT,
-	MX53_ECSPI2_IPP_IND_SS_B_2_SELECT_INPUT,
 	MX53_ESAI1_IPP_IND_FSR_SELECT_INPUT,
 	MX53_ESAI1_IPP_IND_FST_SELECT_INPUT,
 	MX53_ESAI1_IPP_IND_HCKR_SELECT_INPUT,

arch/arm/include/asm/arch-mxs/regs-power.h

@@ -128,7 +128,7 @@ struct mxs_power_regs {
 #define	POWER_MINPWR_PWD_ANA_CMPS			(1 << 10)
 #define	POWER_MINPWR_ENABLE_OSC				(1 << 9)
 #define	POWER_MINPWR_SELECT_OSC				(1 << 8)
-#define	POWER_MINPWR_FBG_OFF				(1 << 7)
+#define	POWER_MINPWR_VBG_OFF				(1 << 7)
 #define	POWER_MINPWR_DOUBLE_FETS			(1 << 6)
 #define	POWER_MINPWR_HALFFETS				(1 << 5)
 #define	POWER_MINPWR_LESSANA_I				(1 << 4)
@@ -268,7 +268,7 @@ struct mxs_power_regs {
 #define	POWER_DCLIMITS_POSLIMIT_BUCK_MASK		(0x7f << 8)
 #define	POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET		8
 #define	POWER_DCLIMITS_NEGLIMIT_MASK			0x7f
-#define	POWER_DCLIMITS_NETLIMIT_OFFSET			0
+#define	POWER_DCLIMITS_NEGLIMIT_OFFSET			0
 
 #define	POWER_LOOPCTRL_TOGGLE_DIF			(1 << 20)
 #define	POWER_LOOPCTRL_HYST_SIGN			(1 << 19)

board/freescale/mx35pdk/lowlevel_init.S

@@ -94,6 +94,10 @@
 	orr r1, r1, #0x00000C00
 	orr r1, r1, #0x00000003
 	str r1, [r0, #CLKCTL_CGR1]
+
+	ldr r1, [r0, #CLKCTL_CGR2]
+	orr r1, r1, #0x00C00000
+	str r1, [r0, #CLKCTL_CGR2]
 .endm
 
 .macro setup_sdram

board/freescale/mx35pdk/mx35pdk.c

@@ -98,6 +98,26 @@ static void setup_iomux_spi(void)
 	mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION);
 }
 
+static void setup_iomux_usbotg(void)
+{
+	int in_pad, out_pad;
+
+	/* Set up pins for USBOTG. */
+	mxc_request_iomux(MX35_PIN_USBOTG_PWR,
+			  MUX_CONFIG_SION | MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_USBOTG_OC,
+			  MUX_CONFIG_SION | MUX_CONFIG_FUNC);
+
+	in_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE |
+		PAD_CTL_PUE_PUD | PAD_CTL_100K_PD | PAD_CTL_ODE_CMOS |
+		PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW;
+	out_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_CMOS | PAD_CTL_PKE_NONE |
+		PAD_CTL_ODE_CMOS | PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW;
+
+	mxc_iomux_set_pad(MX35_PIN_USBOTG_PWR, out_pad);
+	mxc_iomux_set_pad(MX35_PIN_USBOTG_OC, in_pad);
+}
+
 static void setup_iomux_fec(void)
 {
 	int pad;
@@ -189,6 +209,7 @@ int board_early_init_f(void)
 	__raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
 
 	setup_iomux_i2c();
+	setup_iomux_usbotg();
 	setup_iomux_fec();
 	setup_iomux_spi();
 

doc/README.imx5

@@ -15,3 +15,8 @@ i.MX5x SoCs.
     mode), which causes the effect of this failure to be much lower (in terms
     of frequency deviation), avoiding system failure, or at least decreasing
     the likelihood of system failure.
+
+1.2 CONFIG_SYS_MAIN_PWR_ON: Trigger MAIN_PWR_ON upon startup.
+    This option should be enabled for boards having a SYS_ON_OFF_CTL signal
+    connected to GPIO1[23] and triggering the MAIN_PWR_ON signal like in the
+    reference designs.

drivers/spi/mxc_spi.c

@@ -140,8 +140,8 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
 	reg_ctrl = reg_read(&regs->ctrl);
 
 	/* Reset spi */
-	reg_write(&regs->ctrl, 0);
-	reg_write(&regs->ctrl, (reg_ctrl | 0x1));
+	reg_write(&regs->ctrl, (reg_ctrl & ~MXC_CSPICTRL_EN));
+	reg_write(&regs->ctrl, (reg_ctrl | MXC_CSPICTRL_EN));
 
 	/*
 	 * The following computation is taken directly from Freescale's code.
@@ -387,7 +387,7 @@ static int decode_cs(struct mxc_spi_slave *mxcs, unsigned int cs)
 	if (cs > 3) {
 		mxcs->gpio = cs >> 8;
 		cs &= 3;
-		ret = gpio_direction_output(mxcs->gpio, 0);
+		ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol));
 		if (ret) {
 			printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
 			return -EINVAL;
@@ -414,6 +414,8 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 		return NULL;
 	}
 
+	mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
+
 	ret = decode_cs(mxcs, cs);
 	if (ret < 0) {
 		free(mxcs);
@@ -425,7 +427,6 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 	mxcs->slave.bus = bus;
 	mxcs->slave.cs = cs;
 	mxcs->base = spi_bases[bus];
-	mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
 
 	ret = spi_cfg_mxc(mxcs, cs, max_hz, mode);
 	if (ret) {

drivers/usb/host/ehci-mx5.c

@@ -29,34 +29,63 @@
 #define MX5_USBOTHER_REGS_OFFSET 0x800
 
 
-#define MXC_OTG_OFFSET		0
-#define MXC_H1_OFFSET		0x200
-#define MXC_H2_OFFSET		0x400
+#define MXC_OTG_OFFSET			0
+#define MXC_H1_OFFSET			0x200
+#define MXC_H2_OFFSET			0x400
+#define MXC_H3_OFFSET			0x600
 
 #define MXC_USBCTRL_OFFSET		0
 #define MXC_USB_PHY_CTR_FUNC_OFFSET	0x8
 #define MXC_USB_PHY_CTR_FUNC2_OFFSET	0xc
 #define MXC_USB_CTRL_1_OFFSET		0x10
 #define MXC_USBH2CTRL_OFFSET		0x14
+#define MXC_USBH3CTRL_OFFSET		0x18
 
 /* USB_CTRL */
-#define MXC_OTG_UCTRL_OWIE_BIT	(1 << 27) /* OTG wakeup intr enable */
-#define MXC_OTG_UCTRL_OPM_BIT	(1 << 24) /* OTG power mask */
-#define MXC_H1_UCTRL_H1UIE_BIT	(1 << 12) /* Host1 ULPI interrupt enable */
-#define MXC_H1_UCTRL_H1WIE_BIT	(1 << 11) /* HOST1 wakeup intr enable */
-#define MXC_H1_UCTRL_H1PM_BIT	(1 << 8) /* HOST1 power mask */
+/* OTG wakeup intr enable */
+#define MXC_OTG_UCTRL_OWIE_BIT		(1 << 27)
+/* OTG power mask */
+#define MXC_OTG_UCTRL_OPM_BIT		(1 << 24)
+/* OTG power pin polarity */
+#define MXC_OTG_UCTRL_O_PWR_POL_BIT	(1 << 24)
+/* Host1 ULPI interrupt enable */
+#define MXC_H1_UCTRL_H1UIE_BIT		(1 << 12)
+/* HOST1 wakeup intr enable */
+#define MXC_H1_UCTRL_H1WIE_BIT		(1 << 11)
+/* HOST1 power mask */
+#define MXC_H1_UCTRL_H1PM_BIT		(1 << 8)
+/* HOST1 power pin polarity */
+#define MXC_H1_UCTRL_H1_PWR_POL_BIT	(1 << 8)
 
 /* USB_PHY_CTRL_FUNC */
-#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */
-#define MXC_H1_OC_DIS_BIT	(1 << 5) /* UH1 Disable Overcurrent Event */
+/* OTG Polarity of Overcurrent */
+#define MXC_OTG_PHYCTRL_OC_POL_BIT	(1 << 9)
+/* OTG Disable Overcurrent Event */
+#define MXC_OTG_PHYCTRL_OC_DIS_BIT	(1 << 8)
+/* UH1 Polarity of Overcurrent */
+#define MXC_H1_OC_POL_BIT		(1 << 6)
+/* UH1 Disable Overcurrent Event */
+#define MXC_H1_OC_DIS_BIT		(1 << 5)
+/* OTG Power Pin Polarity */
+#define MXC_OTG_PHYCTRL_PWR_POL_BIT	(1 << 3)
 
 /* USBH2CTRL */
-#define MXC_H2_UCTRL_H2UIE_BIT	(1 << 8)
-#define MXC_H2_UCTRL_H2WIE_BIT	(1 << 7)
-#define MXC_H2_UCTRL_H2PM_BIT	(1 << 4)
+#define MXC_H2_UCTRL_H2_OC_POL_BIT	(1 << 31)
+#define MXC_H2_UCTRL_H2_OC_DIS_BIT	(1 << 30)
+#define MXC_H2_UCTRL_H2UIE_BIT		(1 << 8)
+#define MXC_H2_UCTRL_H2WIE_BIT		(1 << 7)
+#define MXC_H2_UCTRL_H2PM_BIT		(1 << 4)
+#define MXC_H2_UCTRL_H2_PWR_POL_BIT	(1 << 4)
+
+/* USBH3CTRL */
+#define MXC_H3_UCTRL_H3_OC_POL_BIT	(1 << 31)
+#define MXC_H3_UCTRL_H3_OC_DIS_BIT	(1 << 30)
+#define MXC_H3_UCTRL_H3UIE_BIT		(1 << 8)
+#define MXC_H3_UCTRL_H3WIE_BIT		(1 << 7)
+#define MXC_H3_UCTRL_H3_PWR_POL_BIT	(1 << 4)
 
 /* USB_CTRL_1 */
-#define MXC_USB_CTRL_UH1_EXT_CLK_EN		(1 << 25)
+#define MXC_USB_CTRL_UH1_EXT_CLK_EN	(1 << 25)
 
 /* USB pin configuration */
 #define USB_PAD_CONFIG	(PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST | \
@@ -143,24 +172,42 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 		if (flags & MXC_EHCI_INTERNAL_PHY) {
 			v = __raw_readl(usbother_base +
 					MXC_USB_PHY_CTR_FUNC_OFFSET);
+			if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
+				v |= MXC_OTG_PHYCTRL_OC_POL_BIT;
+			else
+				v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT;
 			if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+				/* OC/USBPWR is used */
+				v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
+			else
 				/* OC/USBPWR is not used */
 				v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
+#ifdef CONFIG_MX51
+			if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+				v |= MXC_OTG_PHYCTRL_PWR_POL_BIT;
 			else
-				/* OC/USBPWR is used */
-				v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
+				v &= ~MXC_OTG_PHYCTRL_PWR_POL_BIT;
+#endif
 			__raw_writel(v, usbother_base +
 					MXC_USB_PHY_CTR_FUNC_OFFSET);
 
 			v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
+#ifdef CONFIG_MX51
 			if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+				v &= ~MXC_OTG_UCTRL_OPM_BIT;
+			else
 				v |= MXC_OTG_UCTRL_OPM_BIT;
+#endif
+#ifdef CONFIG_MX53
+			if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+				v |= MXC_OTG_UCTRL_O_PWR_POL_BIT;
 			else
-				v &= ~MXC_OTG_UCTRL_OPM_BIT;
+				v &= ~MXC_OTG_UCTRL_O_PWR_POL_BIT;
+#endif
 			__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
 		}
 		break;
-	case 1:	/* Host 1 Host ULPI */
+	case 1:	/* Host 1 ULPI */
 #ifdef CONFIG_MX51
 		/* The clock for the USBH1 ULPI port will come externally
 		   from the PHY. */
@@ -170,13 +217,25 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 #endif
 
 		v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
+#ifdef CONFIG_MX51
 		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-			v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used */
+			v &= ~MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask unused */
 		else
-			v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used */
+			v |= MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask used */
+#endif
+#ifdef CONFIG_MX53
+		if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+			v |= MXC_H1_UCTRL_H1_PWR_POL_BIT;
+		else
+			v &= ~MXC_H1_UCTRL_H1_PWR_POL_BIT;
+#endif
 		__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
 
 		v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
+		if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
+			v |= MXC_H1_OC_POL_BIT;
+		else
+			v &= ~MXC_H1_OC_POL_BIT;
 		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
 			v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
 		else
@@ -186,24 +245,59 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 		break;
 	case 2: /* Host 2 ULPI */
 		v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
+#ifdef CONFIG_MX51
 		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-			v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used */
+			v &= ~MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask unused */
 		else
-			v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used */
-
+			v |= MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask used */
+#endif
+#ifdef CONFIG_MX53
+		if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
+			v |= MXC_H2_UCTRL_H2_OC_POL_BIT;
+		else
+			v &= ~MXC_H2_UCTRL_H2_OC_POL_BIT;
+		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+			v &= ~MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is used */
+		else
+			v |= MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is not used */
+		if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+			v |= MXC_H2_UCTRL_H2_PWR_POL_BIT;
+		else
+			v &= ~MXC_H2_UCTRL_H2_PWR_POL_BIT;
+#endif
 		__raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
 		break;
+#ifdef CONFIG_MX53
+	case 3: /* Host 3 ULPI */
+		v = __raw_readl(usbother_base + MXC_USBH3CTRL_OFFSET);
+		if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
+			v |= MXC_H3_UCTRL_H3_OC_POL_BIT;
+		else
+			v &= ~MXC_H3_UCTRL_H3_OC_POL_BIT;
+		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+			v &= ~MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is used */
+		else
+			v |= MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is not used */
+		if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+			v |= MXC_H3_UCTRL_H3_PWR_POL_BIT;
+		else
+			v &= ~MXC_H3_UCTRL_H3_PWR_POL_BIT;
+		__raw_writel(v, usbother_base + MXC_USBH3CTRL_OFFSET);
+		break;
+#endif
 	}
 
 	return ret;
 }
 
-void __board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
+int __weak board_ehci_hcd_init(int port)
 {
+	return 0;
 }
 
-void board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
-	__attribute((weak, alias("__board_ehci_hcd_postinit")));
+void __weak board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
+{
+}
 
 int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {

drivers/usb/host/ehci-mx6.c

@@ -159,6 +159,11 @@ static void usbh1_oc_config(void)
 	__raw_writel(val, usbother_base + USB_H1_CTRL_OFFSET);
 }
 
+int __weak board_ehci_hcd_init(int port)
+{
+	return 0;
+}
+
 int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
 	struct usb_ehci *ehci;

drivers/usb/host/ehci-mxc.c

@@ -28,14 +28,22 @@
 
 #define USBCTRL_OTGBASE_OFFSET	0x600
 
-#ifdef CONFIG_MX25
-#define MX25_USB_CTRL_IP_PUE_DOWN_BIT	(1<<6)
-#define MX25_USB_CTRL_HSTD_BIT		(1<<5)
-#define MX25_USB_CTRL_USBTE_BIT		(1<<4)
-#define MX25_USB_CTRL_OCPOL_OTG_BIT	(1<<3)
-#endif
+#define MX25_OTG_SIC_SHIFT	29
+#define MX25_OTG_SIC_MASK	(0x3 << MX25_OTG_SIC_SHIFT)
+#define MX25_OTG_PM_BIT		(1 << 24)
+#define MX25_OTG_PP_BIT		(1 << 11)
+#define MX25_OTG_OCPOL_BIT	(1 << 3)
+
+#define MX25_H1_SIC_SHIFT	21
+#define MX25_H1_SIC_MASK	(0x3 << MX25_H1_SIC_SHIFT)
+#define MX25_H1_PP_BIT		(1 << 18)
+#define MX25_H1_PM_BIT		(1 << 16)
+#define MX25_H1_IPPUE_UP_BIT	(1 << 7)
+#define MX25_H1_IPPUE_DOWN_BIT	(1 << 6)
+#define MX25_H1_TLL_BIT		(1 << 5)
+#define MX25_H1_USBTE_BIT	(1 << 4)
+#define MX25_H1_OCPOL_BIT	(1 << 2)
 
-#ifdef CONFIG_MX31
 #define MX31_OTG_SIC_SHIFT	29
 #define MX31_OTG_SIC_MASK	(0x3 << MX31_OTG_SIC_SHIFT)
 #define MX31_OTG_PM_BIT		(1 << 24)
@@ -49,59 +57,166 @@
 #define MX31_H1_SIC_MASK	(0x3 << MX31_H1_SIC_SHIFT)
 #define MX31_H1_PM_BIT		(1 << 8)
 #define MX31_H1_DT_BIT		(1 << 4)
-#endif
+
+#define MX35_OTG_SIC_SHIFT	29
+#define MX35_OTG_SIC_MASK	(0x3 << MX35_OTG_SIC_SHIFT)
+#define MX35_OTG_PM_BIT		(1 << 24)
+#define MX35_OTG_PP_BIT		(1 << 11)
+#define MX35_OTG_OCPOL_BIT	(1 << 3)
+
+#define MX35_H1_SIC_SHIFT	21
+#define MX35_H1_SIC_MASK	(0x3 << MX35_H1_SIC_SHIFT)
+#define MX35_H1_PP_BIT		(1 << 18)
+#define MX35_H1_PM_BIT		(1 << 16)
+#define MX35_H1_IPPUE_UP_BIT	(1 << 7)
+#define MX35_H1_IPPUE_DOWN_BIT	(1 << 6)
+#define MX35_H1_TLL_BIT		(1 << 5)
+#define MX35_H1_USBTE_BIT	(1 << 4)
+#define MX35_H1_OCPOL_BIT	(1 << 2)
 
 static int mxc_set_usbcontrol(int port, unsigned int flags)
 {
 	unsigned int v;
 
-#ifdef CONFIG_MX25
-	v = MX25_USB_CTRL_IP_PUE_DOWN_BIT | MX25_USB_CTRL_HSTD_BIT |
-		MX25_USB_CTRL_USBTE_BIT | MX25_USB_CTRL_OCPOL_OTG_BIT;
-#endif
+	v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
+#if defined(CONFIG_MX25)
+	switch (port) {
+	case 0:	/* OTG port */
+		v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT | MX25_OTG_PP_BIT |
+				MX25_OTG_OCPOL_BIT);
+		v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT;
 
-#ifdef CONFIG_MX31
-		v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
-
-		switch (port) {
-		case 0:	/* OTG port */
-			v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
-			v |= (flags & MXC_EHCI_INTERFACE_MASK)
-					<< MX31_OTG_SIC_SHIFT;
-			if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-				v |= MX31_OTG_PM_BIT;
-
-			break;
-		case 1: /* H1 port */
-			v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT |
-				MX31_H1_DT_BIT);
-			v |= (flags & MXC_EHCI_INTERFACE_MASK)
-						<< MX31_H1_SIC_SHIFT;
-			if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-				v |= MX31_H1_PM_BIT;
-
-			if (!(flags & MXC_EHCI_TTL_ENABLED))
-				v |= MX31_H1_DT_BIT;
-
-			break;
-		case 2:	/* H2 port */
-			v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT |
-				MX31_H2_DT_BIT);
-			v |= (flags & MXC_EHCI_INTERFACE_MASK)
-						<< MX31_H2_SIC_SHIFT;
-			if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-				v |= MX31_H2_PM_BIT;
-
-			if (!(flags & MXC_EHCI_TTL_ENABLED))
-				v |= MX31_H2_DT_BIT;
-
-			break;
-		default:
-			return -EINVAL;
-		}
-#endif
+		if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+			v |= MX25_OTG_PM_BIT;
+
+		if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+			v |= MX25_OTG_PP_BIT;
+
+		if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
+			v |= MX25_OTG_OCPOL_BIT;
+
+		break;
+	case 1: /* H1 port */
+		v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_PP_BIT |
+				MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT |
+				MX25_H1_USBTE_BIT | MX25_H1_IPPUE_DOWN_BIT |
+				MX25_H1_IPPUE_UP_BIT);
+		v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT;
+
+		if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+			v |= MX25_H1_PM_BIT;
+
+		if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+			v |= MX25_H1_PP_BIT;
+
+		if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
+			v |= MX25_H1_OCPOL_BIT;
+
+		if (!(flags & MXC_EHCI_TTL_ENABLED))
+			v |= MX25_H1_TLL_BIT;
+
+		if (flags & MXC_EHCI_INTERNAL_PHY)
+			v |= MX25_H1_USBTE_BIT;
+
+		if (flags & MXC_EHCI_IPPUE_DOWN)
+			v |= MX25_H1_IPPUE_DOWN_BIT;
+
+		if (flags & MXC_EHCI_IPPUE_UP)
+			v |= MX25_H1_IPPUE_UP_BIT;
+
+		break;
+	default:
+		return -EINVAL;
+	}
+#elif defined(CONFIG_MX31)
+	switch (port) {
+	case 0:	/* OTG port */
+		v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
+		v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_OTG_SIC_SHIFT;
+
+		if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+			v |= MX31_OTG_PM_BIT;
 
+		break;
+	case 1: /* H1 port */
+		v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT);
+		v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H1_SIC_SHIFT;
+
+		if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+			v |= MX31_H1_PM_BIT;
+
+		if (!(flags & MXC_EHCI_TTL_ENABLED))
+			v |= MX31_H1_DT_BIT;
+
+		break;
+	case 2:	/* H2 port */
+		v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT);
+		v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H2_SIC_SHIFT;
+
+		if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+			v |= MX31_H2_PM_BIT;
+
+		if (!(flags & MXC_EHCI_TTL_ENABLED))
+			v |= MX31_H2_DT_BIT;
+
+		break;
+	default:
+		return -EINVAL;
+	}
+#elif defined(CONFIG_MX35)
+	switch (port) {
+	case 0:	/* OTG port */
+		v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT | MX35_OTG_PP_BIT |
+				MX35_OTG_OCPOL_BIT);
+		v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT;
+
+		if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+			v |= MX35_OTG_PM_BIT;
+
+		if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+			v |= MX35_OTG_PP_BIT;
+
+		if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
+			v |= MX35_OTG_OCPOL_BIT;
+
+		break;
+	case 1: /* H1 port */
+		v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_PP_BIT |
+				MX35_H1_OCPOL_BIT | MX35_H1_TLL_BIT |
+				MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT |
+				MX35_H1_IPPUE_UP_BIT);
+		v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT;
+
+		if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+			v |= MX35_H1_PM_BIT;
+
+		if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+			v |= MX35_H1_PP_BIT;
+
+		if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
+			v |= MX35_H1_OCPOL_BIT;
+
+		if (!(flags & MXC_EHCI_TTL_ENABLED))
+			v |= MX35_H1_TLL_BIT;
+
+		if (flags & MXC_EHCI_INTERNAL_PHY)
+			v |= MX35_H1_USBTE_BIT;
+
+		if (flags & MXC_EHCI_IPPUE_DOWN)
+			v |= MX35_H1_IPPUE_DOWN_BIT;
+
+		if (flags & MXC_EHCI_IPPUE_UP)
+			v |= MX35_H1_IPPUE_UP_BIT;
+
+		break;
+	default:
+		return -EINVAL;
+	}
+#else
+#error MXC EHCI USB driver not supported on this platform
+#endif
 	writel(v, IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
+
 	return 0;
 }
 
@@ -119,13 +234,17 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 	udelay(80);
 
 	ehci = (struct usb_ehci *)(IMX_USB_BASE +
-		(0x200 * CONFIG_MXC_USB_PORT));
+			IMX_USB_PORT_OFFSET * CONFIG_MXC_USB_PORT);
 	*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
 	*hcor = (struct ehci_hcor *)((uint32_t) *hccr +
 			HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
 	setbits_le32(&ehci->usbmode, CM_HOST);
 	__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
 	mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
+#ifdef CONFIG_MX35
+	/* Workaround for ENGcm11601 */
+	__raw_writel(0, &ehci->sbuscfg);
+#endif
 
 	udelay(10000);
 

include/configs/mx25pdk.h

@@ -130,7 +130,7 @@
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NET
 
-#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTDELAY	1
 
 #define CONFIG_LOADADDR		0x81000000	/* loadaddr env var */
 #define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR

include/configs/mx28evk.h

@@ -238,7 +238,7 @@
  */
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTDELAY	1
 #define CONFIG_BOOTFILE	"uImage"
 #define CONFIG_LOADADDR	0x42000000
 #define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR

include/configs/mx31pdk.h

@@ -106,7 +106,7 @@
 
 #define CONFIG_BOARD_LATE_INIT
 
-#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTDELAY	1
 
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
 	"bootargs_base=setenv bootargs console=ttymxc0,115200\0"	\

include/configs/mx35pdk.h

@@ -112,13 +112,15 @@
 #define CONFIG_NET_RETRY_COUNT	100
 #define CONFIG_CMD_DATE
 
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
 #define CONFIG_CMD_MMC
 #define CONFIG_DOS_PARTITION
 #define CONFIG_EFI_PARTITION
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_FAT
 
-#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTDELAY	1
 
 #define CONFIG_LOADADDR		0x80800000	/* loadaddr env var */
 
@@ -244,6 +246,18 @@
 #define CONFIG_MXC_NAND_HWECC
 #define CONFIG_SYS_NAND_LARGEPAGE
 
+/* EHCI driver */
+#define CONFIG_USB_EHCI
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	1
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_MXC
+#define CONFIG_MXC_USB_PORT	0
+#define CONFIG_MXC_USB_FLAGS	(MXC_EHCI_INTERFACE_DIFF_UNI | \
+				 MXC_EHCI_POWER_PINS_ENABLED | \
+				 MXC_EHCI_OC_PIN_ACTIVE_LOW)
+#define CONFIG_MXC_USB_PORTSC	(MXC_EHCI_UTMI_16BIT | MXC_EHCI_MODE_UTMI)
+
 /* mmc driver */
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC

include/configs/mx51_efikamx.h

@@ -261,5 +261,6 @@
 
 #define CONFIG_SYS_DDR_CLKSEL		0
 #define CONFIG_SYS_CLKTL_CBCDR		0x59E35145
+#define CONFIG_SYS_MAIN_PWR_ON
 
 #endif

include/configs/mx51evk.h

@@ -149,7 +149,7 @@
 
 #define CONFIG_CMD_DATE
 
-#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTDELAY	1
 
 #define CONFIG_ETHPRIME		"FEC0"
 
@@ -235,6 +235,7 @@
 
 #define CONFIG_SYS_DDR_CLKSEL	0
 #define CONFIG_SYS_CLKTL_CBCDR	0x59E35100
+#define CONFIG_SYS_MAIN_PWR_ON
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization

include/configs/mx53loco.h

@@ -108,7 +108,7 @@
 
 #undef CONFIG_CMD_IMLS
 
-#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTDELAY	1
 
 #define CONFIG_ETHPRIME		"FEC0"
 

include/configs/mx6qsabre_common.h

@@ -76,7 +76,7 @@
 #define CONFIG_CMD_BOOTZ
 #undef CONFIG_CMD_IMLS
 
-#define CONFIG_BOOTDELAY               3
+#define CONFIG_BOOTDELAY               1
 
 #define CONFIG_LOADADDR                        0x10800000
 #define CONFIG_SYS_TEXT_BASE           0x17800000

include/configs/mx6qsabrelite.h

@@ -144,7 +144,7 @@
 
 #undef CONFIG_CMD_IMLS
 
-#define CONFIG_BOOTDELAY	       3
+#define CONFIG_BOOTDELAY	       1
 
 #define CONFIG_PREBOOT                 ""
 

include/configs/vision2.h

@@ -196,6 +196,7 @@
 /* 166 MHz DDR RAM */
 #define CONFIG_SYS_DDR_CLKSEL		0
 #define CONFIG_SYS_CLKTL_CBCDR		0x19239100
+#define CONFIG_SYS_MAIN_PWR_ON
 
 #define CONFIG_SYS_NO_FLASH
 

include/configs/zmx25.h

@@ -109,9 +109,9 @@
 #define CONFIG_USB_EHCI			/* Enable EHCI USB support */
 #define CONFIG_USB_EHCI_MXC
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_MXC_USB_PORT	2
-#define CONFIG_MXC_USB_PORTSC	0xC0000000
-#define CONFIG_MXC_USB_FLAGS	0
+#define CONFIG_MXC_USB_PORT	1
+#define CONFIG_MXC_USB_PORTSC	MXC_EHCI_MODE_SERIAL
+#define CONFIG_MXC_USB_FLAGS	(MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN)
 #define CONFIG_EHCI_IS_TDI
 #define CONFIG_USB_STORAGE
 #define CONFIG_DOS_PARTITION

include/usb/ehci-fsl.h

@@ -246,9 +246,33 @@ struct usb_ehci {
 /*
  * For MXC SOCs
  */
+
+/* values for portsc field */
+#define MXC_EHCI_PHY_LOW_POWER_SUSPEND	(1 << 23)
+#define MXC_EHCI_FORCE_FS		(1 << 24)
+#define MXC_EHCI_UTMI_8BIT		(0 << 28)
+#define MXC_EHCI_UTMI_16BIT		(1 << 28)
+#define MXC_EHCI_SERIAL			(1 << 29)
+#define MXC_EHCI_MODE_UTMI		(0 << 30)
+#define MXC_EHCI_MODE_PHILIPS		(1 << 30)
+#define MXC_EHCI_MODE_ULPI		(2 << 30)
+#define MXC_EHCI_MODE_SERIAL		(3 << 30)
+
+/* values for flags field */
+#define MXC_EHCI_INTERFACE_DIFF_UNI	(0 << 0)
+#define MXC_EHCI_INTERFACE_DIFF_BI	(1 << 0)
+#define MXC_EHCI_INTERFACE_SINGLE_UNI	(2 << 0)
+#define MXC_EHCI_INTERFACE_SINGLE_BI	(3 << 0)
+#define MXC_EHCI_INTERFACE_MASK		(0xf)
+
 #define MXC_EHCI_POWER_PINS_ENABLED	(1 << 5)
-#define MXC_EHCI_TTL_ENABLED		(1 << 6)
-#define MXC_EHCI_INTERNAL_PHY		(1 << 7)
+#define MXC_EHCI_PWR_PIN_ACTIVE_HIGH	(1 << 6)
+#define MXC_EHCI_OC_PIN_ACTIVE_LOW	(1 << 7)
+#define MXC_EHCI_TTL_ENABLED		(1 << 8)
+
+#define MXC_EHCI_INTERNAL_PHY		(1 << 9)
+#define MXC_EHCI_IPPUE_DOWN		(1 << 10)
+#define MXC_EHCI_IPPUE_UP		(1 << 11)
 
 /* Board-specific initialization */
 int board_ehci_hcd_init(int port);