Add support for TB5200 board

The TB5200 ("Tinybox") is a small baseboard for the TQM5200 module
integrated in a little aluminium case.
Patch by Martin Krause, 8 Jun 2006

Some code cleanup

CHANGELOG

@@ -2,6 +2,11 @@
 Changes since U-Boot 1.1.4:
 ======================================================================
 
+* Add support for TB5200 board
+  The TB5200 ("Tinybox") is a small baseboard for the TQM5200 module
+  integrated in a little aluminium case.
+  Patch by Martin Krause, 8 Jun 2006
+
 * Enable buffered flash writes for TQM5200 board.
 
 * Fix problems with SanDisk Corporation Cruzer Micro USB memory stick.
@@ -18,7 +23,7 @@ Changes since U-Boot 1.1.4:
 
 * Add support for SPC1920 board.
   Patch by Markus Klotzbuecher, 12 Jul 2006
-  
+
 * MCC200 board: support console on any one of the Quad UART ports.
 
 * Fix error in flash protection calculation on MCC200 board.
@@ -60,14 +65,14 @@ Changes since U-Boot 1.1.4:
 * VoiceBlue update: use new MTD flash partitioning methods, use more
   reasonable TEXT_BASE, update default environment and enable keyed
   autoboot.
-  Patch by Ladislav Michl, 16. Aug 2005 
+  Patch by Ladislav Michl, 16. Aug 2005
 
 * Add forgotten changes for the PLEB 2 Board.
   Patch by David Snowdon, 13. Aug 2005
 
 * Add support for wrPPMC7xx/74xx boards
   Patch by Richard Danter, 12 Aug 2005
- 
+
 * Add support for gth2 board
   Patch by Thomas Lange, Aug 11 2005
 
@@ -89,7 +94,7 @@ Changes since U-Boot 1.1.4:
   With this fix pin I2CSCL (PG6) is really configured as GPIO
   so the clock pulses are really generated.
   Patch by Martin Krause, 04 Apr 2006
-  
+
 * Fix DDR6 errata on TQM834x boards
   Patch by Thomas Waehner, 07 Mar 2006
 
@@ -106,7 +111,7 @@ Changes since U-Boot 1.1.4:
   has been programmed. Jumper Settings: X66 1-2, 9-10; X61 2-3
 
 * Fix TRAB channel switching delay for trab_fkt.bin standalone applikation
-  In tsc2000_read_channel() the delay after setting the multiplexer 
+  In tsc2000_read_channel() the delay after setting the multiplexer
   to a temperature channel is increased from 1,5 ms to 10 ms. This
   is to allow the multiplexer inputs to stabilize after huge steps
   of the input signal level.

Makefile

@@ -360,6 +360,11 @@ spieval_config:	unconfig
 	@echo "... with automatic CS configuration"
 	@./mkconfig -a spieval ppc mpc5xxx tqm5200
 
+TB5200_config:	unconfig
+	@echo "#define CONFIG_CS_AUTOCONF">>include/config.h
+	@echo "... with automatic CS configuration"
+	@./mkconfig -a TB5200 ppc mpc5xxx tqm5200
+
 MINI5200_config	\
 EVAL5200_config	\
 TOP5200_config:	unconfig
@@ -1461,7 +1466,7 @@ ZUMA_config:	unconfig
 
 ppmc7xx_config: unconfig
 	@./mkconfig $(@:_config=) ppc 74xx_7xx ppmc7xx
-	
+
 #========================================================================
 # ARM
 #========================================================================

board/amcc/yucca/cmd_yucca.c

@@ -30,7 +30,7 @@
 #include <asm/byteorder.h>
 
 extern void print_evb440spe_info(void);
-static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, 
+static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag,
 		int flag, int argc, char *argv[]);
 
 extern int cmd_get_data_size(char* arg, int default_size);

board/amcc/yucca/flash.c

@@ -1004,7 +1004,7 @@ unsigned long flash_init(void)
 		}
 	} /*else if (index == 0) {*/
 /*		if (in8(FPGA_SETTING_REG) & FPGA_SET_REG_OP_CODE_FLASH_ABOVE)*/
-/*			index = 8;*//* sram below op code flash -> new index 8*/
+/*			index = 8;*/ /* sram below op code flash -> new index 8*/
 /*	}*/
 
 	DEBUGF("\n");

board/amcc/yucca/init.S

@@ -102,4 +102,3 @@ tlbtab:
 	tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
 	tlbtab_end
-

board/amcc/yucca/yucca.c

@@ -1094,4 +1094,3 @@ unsigned long ppcMfsdr(unsigned long sdr_reg)
 
 	return (sdr_value);
 }
-

board/gth2/config.mk

@@ -39,4 +39,3 @@ TEXT_BASE = 0x90000000
 endif
 endif
 endif
-

board/gth2/ee_access.c

@@ -8,7 +8,7 @@
    For documentaion, see data sheet for DS2438, 2438.pdf
 
    By Thomas.Lange@corelatus.com 001025
-   
+
    Copyright (C) 2000-2005 Corelatus AB */
 
 /* This program is free software; you can redistribute it and/or
@@ -105,7 +105,7 @@ static u8 make_new_crc( u8 Old_crc, u8 New_value ){
 	/* Compute a new checksum with new byte, using previous checksum as input
 	   See DS app note 17, understanding and using cyclic redundancy checks...
 	   Also see DS2438, page 11 */
-	return( crc_lookup[Old_crc ^ New_value ]); 
+	return( crc_lookup[Old_crc ^ New_value ]);
 }
 
 int ee_crc_ok( u8 *Buffer, int Len, u8 Crc ){
@@ -119,16 +119,16 @@ int ee_crc_ok( u8 *Buffer, int Len, u8 Crc ){
 		Curr_byte++;
 	}
 	E_DEBUG("Calculated CRC = 0x%x, read = 0x%x\n", Curr_crc, Crc);
-  
+
 	if(Curr_crc == Crc){
-		/* Good */ 
+		/* Good */
 		return(TRUE);
 	}
 	printk(KERN_ERR"EE checksum error, Calculated CRC = 0x%x, read = 0x%x\n", Curr_crc, Crc);
 	return(FALSE);
 }
 
-static void 
+static void
 set_idle(void){
 	/* Send idle and keep start time
 	   Continous 1 is idle */
@@ -136,7 +136,7 @@ set_idle(void){
 }
 
 
-static int 
+static int
 do_cpu_reset(void){
 	/* Release reset and verify that chip responds with presence pulse */
 	int Retries=0;
@@ -146,10 +146,10 @@ do_cpu_reset(void){
 		/* Send reset */
 		WRITE_PORT(0);
 		udelay(RESET_LOW_TIME);
-    
+
 		/* Release reset */
 		WRITE_PORT(1);
-    
+
 		/* Wait for EEPROM to drive output */
 		udelay(PRESENCE_TIMEOUT);
 		if(!READ_PORT){
@@ -166,17 +166,17 @@ do_cpu_reset(void){
 	}
 
 	printk(KERN_ERR"eeprom did not respond when releasing reset\n");
-    
+
 	/* Make sure chip releases pin */
 	udelay(PRESENCE_LOW_TIME);
 
 	/* Set to idle again */
 	set_idle();
- 
+
 	return(-EIO);
 }
 
-static u8 
+static u8
 read_cpu_byte(void){
 	/* Read a single byte from EEPROM
 	   Read LSb first */
@@ -186,36 +186,36 @@ read_cpu_byte(void){
 	u32 Flags;
 
 	E_DEBUG("Reading byte\n");
-  
+
 	for(i=0;i<8;i++){
 		/* Small delay between pulses */
 		udelay(1);
 
-#ifdef __KERNEL__  
-		/* Disable irq */ 
+#ifdef __KERNEL__
+		/* Disable irq */
 		save_flags(Flags);
 		cli();
-#endif    
+#endif
 
 		/* Pull down pin short time to start read
 		   See page 26 in data sheet */
-    
+
 		WRITE_PORT(0);
 		udelay(READ_LOW);
 		WRITE_PORT(1);
-        
+
 		/* Wait for chip to drive pin */
 		udelay(READ_TIMEOUT);
-    
+
 		Value = READ_PORT;
 		if(Value)
 			Value=1;
 
 #ifdef __KERNEL__
-		/* Enable irq */ 
+		/* Enable irq */
 		restore_flags(Flags);
 #endif
-    
+
 		/* Wait for chip to release pin */
 		udelay(TOTAL_READ_LOW-READ_TIMEOUT);
 
@@ -230,30 +230,30 @@ read_cpu_byte(void){
 	return(Result);
 }
 
-static void 
+static void
 write_cpu_byte(u8 Byte){
 	/* Write a single byte to EEPROM
 	   Write LSb first */
 	int i;
 	int Value;
 	u32 Flags;
-  
+
 	E_DEBUG("Writing byte 0x%x\n",Byte);
-  
+
 	for(i=0;i<8;i++){
 		/* Small delay between pulses */
 		udelay(1);
 		Value = Byte&1;
-    
+
 #ifdef __KERNEL__
-		/* Disable irq */ 
+		/* Disable irq */
 		save_flags(Flags);
 		cli();
-#endif    
+#endif
 
 		/* Pull down pin short time for a 1, long time for a 0
 		   See page 26 in data sheet */
-    
+
 		WRITE_PORT(0);
 		if(Value){
 			/* Write a 1 */
@@ -267,54 +267,54 @@ write_cpu_byte(u8 Byte){
 		WRITE_PORT(1);
 
 #ifdef __KERNEL__
-		/* Enable irq */ 
+		/* Enable irq */
 		restore_flags(Flags);
 #endif
 
 		if(Value)
 			/* Wait for chip to read the 1 */
 			udelay(TOTAL_WRITE_LOW-WRITE_1_LOW);
-        
+
 		/* E_DEBUG("Wrote %d\n",Value); */
 		Byte>>=1;
 	}
 }
 
 int ee_do_cpu_command( u8 *Tx, int Tx_len, u8 *Rx, int Rx_len, int Send_skip ){
-	/* Execute this command string, including 
+	/* Execute this command string, including
 	   giving reset and setting to idle after command
-	   if Rx_len is set, we read out data from EEPROM */ 
+	   if Rx_len is set, we read out data from EEPROM */
 	int i;
 
 	E_DEBUG("Command, Tx_len %d, Rx_len %d\n", Tx_len, Rx_len );
-  
+
 	if(do_cpu_reset()){
 		/* Failed! */
 		return(-EIO);
 	}
 
 	if(Send_skip)
-		/* Always send SKIP_ROM first to tell chip we are sending a command, 
+		/* Always send SKIP_ROM first to tell chip we are sending a command,
 		   except when we read out rom data for chip */
 		write_cpu_byte(SKIP_ROM);
-  
+
 	/* Always have Tx data */
 	for(i=0;i<Tx_len;i++){
 		write_cpu_byte(Tx[i]);
 	}
-  
+
 	if(Rx_len){
 		for(i=0;i<Rx_len;i++){
 			Rx[i]=read_cpu_byte();
 		}
 	}
-  
+
 	set_idle();
 
 	E_DEBUG("Command done\n");
 
 	return(0);
-} 
+}
 
 int ee_init_cpu_data(void){
 	int i;
@@ -323,7 +323,7 @@ int ee_init_cpu_data(void){
 	/* Leave it floting since altera is driving the same pin */
 	set_idle();
 
-	/* Copy all User EEPROM data to scratchpad */ 
+	/* Copy all User EEPROM data to scratchpad */
 	for(i=0;i<USER_PAGES;i++){
 		Tx[0]=RECALL_MEMORY;
 		Tx[1]=EE_USER_PAGE_0+i;
@@ -332,16 +332,16 @@ int ee_init_cpu_data(void){
 
 	/* Make sure chip doesnt store measurements in NVRAM */
 	Tx[0]=WRITE_SCRATCHPAD;
-	Tx[1]=0; /* Page */ 
+	Tx[1]=0; /* Page */
 	Tx[2]=9;
 	if(ee_do_cpu_command(Tx,3,NULL,0,TRUE)) return(-EIO);
 
 	Tx[0]=COPY_SCRATCHPAD;
 	if(ee_do_cpu_command(Tx,2,NULL,0,TRUE)) return(-EIO);
-  
+
 	for(i=0;i<10;i++){
 		udelay(1000);
 	}
-  
+
 	return(0);
 }

board/gth2/ee_access.h

@@ -21,7 +21,7 @@ int ee_crc_ok( u8 *Buffer, int Len, u8 Crc );
 #define EE_BUSY  0x40000000
 #define EE_ERROR 0x20000000
 
-/* Commands */ 
+/* Commands */
 #define EE_CMD_NOP      0
 #define EE_CMD_INIT_RES 1
 #define EE_CMD_WR_BYTE  2

board/gth2/ee_dev.h

@@ -21,7 +21,7 @@
 #ifndef INCeedevh
 #define INCeedevh
 
-#define E_DEBUG(fmt,args...) if( Debug ) printk(KERN_DEBUG"EE: " fmt, ##args) 
+#define E_DEBUG(fmt,args...) if( Debug ) printk(KERN_DEBUG"EE: " fmt, ##args)
 
 /* MIPS */
 #define WRITE_PORT(Value) write_gpio_data(Value)

board/gth2/gth2.c

@@ -61,13 +61,13 @@ void init_log_serial(void){
 	u32 *serial_log_offsetp = (u32*)SERIAL_LOG_BUFFER;
 
 	/* Copy buffer from last run */
-	memcpy(serial_log_buffer + 4096, 
-	       serial_log_buffer, 
+	memcpy(serial_log_buffer + 4096,
+	       serial_log_buffer,
 	       4096);
 
 	memset(serial_log_buffer, 0, 4096);
 
-	*serial_log_offsetp = 4;	
+	*serial_log_offsetp = 4;
 }
 
 
@@ -118,7 +118,7 @@ void set_ledcard(u32 value){
 		udelay(1);
 		*sys_outputclr = GPIO_LEDCLK;
 		udelay(1);
-		
+
 		value<<=1;
 	}
 	/* Data is enable output */
@@ -228,7 +228,7 @@ static void write_bootdata (volatile u16 * addr, u8 System, u8 Count)
 		printf ("Invalid boot count %u, setting 1\n", Count);
 		Count = 1;
 	}
-	
+
 	printf ("Boot attempt %d\n", Count);
 
 	data = (System << 8) | Count;
@@ -241,9 +241,9 @@ static void write_bootdata (volatile u16 * addr, u8 System, u8 Count)
 }
 
 static int random_system(void){
-	/* EEPROM read failed. Just try to choose one 
+	/* EEPROM read failed. Just try to choose one
 	   system release and hope it works */
-	
+
 	/* FIXME */
 	return(SYSTEM_BOOT);
 }
@@ -320,8 +320,8 @@ static void check_boot_tries (void)
 			data = *addr;
 			system = data >> 8;
 			count = data & 0xFF;
-			if ((system != SYSTEM_BOOT) & 
-			    (system != SYSTEM2_BOOT) & 
+			if ((system != SYSTEM_BOOT) &
+			    (system != SYSTEM2_BOOT) &
 			    (system != FAILSAFE_BOOT)) {
 				printf ("*** Wrong system %d\n", system);
 				system = FAILSAFE_BOOT;

board/gth2/lowlevel_init.S

@@ -197,11 +197,11 @@ noCacheJump:
 
 	/* RCE2 CP Altera */
 	li	t0, MEM_STCFG2
-	li	t1, 0x00000280 /* BE, EW */ 
+	li	t1, 0x00000280 /* BE, EW */
 	sw	t1, 0(t0)
 
 	li	t0, MEM_STTIME2
-	li	t1, 0x0303000c 
+	li	t1, 0x0303000c
 	sw	t1, 0(t0)
 
 	li	t0, MEM_STADDR2
@@ -210,11 +210,11 @@ noCacheJump:
 
 	/* RCE3 DP Altera */
 	li	t0, MEM_STCFG3
-	li	t1, 0x00000280 /* BE, EW */ 
+	li	t1, 0x00000280 /* BE, EW */
 	sw	t1, 0(t0)
 
 	li	t0, MEM_STTIME3
-	li	t1, 0x0303000c 
+	li	t1, 0x0303000c
 	sw	t1, 0(t0)
 
 	li	t0, MEM_STADDR3
@@ -428,14 +428,14 @@ mt0:	sw	t0, 0(t0)
 	li	t0, 0x80000000
 	li	t1, 0xFFF000 /* 64 MB */
 mt1:	lw	t2, 0(t0)
-	bne	t0, t2, memhang	
+	bne	t0, t2, memhang
 	add	t1, -1
 	add	t0, 4
 	bne	t1, zero, mt1
 	nop
 	nop
 	.globl	clearmem
-clearmem:		
+clearmem:
 		/* Clear memory */
 	li	t0, 0x80000000
 	li	t1, 0xFFF000 /* 64 MB */
@@ -445,10 +445,10 @@ mtc:	sw	zero, 0(t0)
 	bne	t1, zero, mtc
 	nop
 	nop
-memtestend:		
+memtestend:
 	j	ra
 	nop
-	
-memhang:	
+
+memhang:
 	b	memhang
 	nop

board/ppmc7xx/config.mk

@@ -1,6 +1,6 @@
 #
 # (C) Copyright 2005
-# Richard Danter, Wind River Systems 
+# Richard Danter, Wind River Systems
 #
 # (C) Copyright 2000
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -24,10 +24,6 @@
 # MA 02111-1307 USA
 #
 
-#
-# 
-#
-
 TEXT_BASE = 0xFFF00000
 TEXT_END  = 0xFFF40000
 PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)

board/ppmc7xx/flash.c

@@ -1,10 +1,10 @@
 /*
  * flash.c
  * -------
- * 
+ *
  * Flash programming routines for the Wind River PPMC 74xx/7xx
  * based on flash.c from the TQM8260 board.
- * 
+ *
  * By Richard Danter (richard.danter@windriver.com)
  * Copyright (C) 2005 Wind River Systems
  */
@@ -27,13 +27,13 @@ void flash_reset (void)
 {
 	unsigned long msr;
 	DWORD cmd_reset = 0x00F000F000F000F0LL;
-	
+
 	if (flash_info[0].flash_id != FLASH_UNKNOWN) {
 		msr = get_msr ();
 		set_msr (msr | MSR_FP);
 
 		write_via_fpu ((DWORD*)flash_info[0].start[0], &cmd_reset );
-		
+
 		set_msr (msr);
 	}
 }
@@ -50,16 +50,16 @@ ulong flash_get_size (ulong baseaddr, flash_info_t * info)
 
 	/* Enable FPU */
 	msr = get_msr ();
-	set_msr (msr | MSR_FP);	
-							
+	set_msr (msr | MSR_FP);
+
 	/* Write auto-select command sequence */
 	write_via_fpu ((DWORD*)(baseaddr + (0x0555 << 3)), &cmd_select[0] );
 	write_via_fpu ((DWORD*)(baseaddr + (0x02AA << 3)), &cmd_select[1] );
 	write_via_fpu ((DWORD*)(baseaddr + (0x0555 << 3)), &cmd_select[2] );
-	
+
 	/* Restore FPU */
 	set_msr (msr);
-	
+
 	/* Read manufacturer ID */
 	flashtest = *(volatile DWORD*)baseaddr;
 	switch ((int)flashtest) {
@@ -70,7 +70,7 @@ ulong flash_get_size (ulong baseaddr, flash_info_t * info)
 		info->flash_id = FLASH_MAN_FUJ;
 		break;
 	default:
-		/* No, faulty or unknown flash */ 
+		/* No, faulty or unknown flash */
 		info->flash_id = FLASH_UNKNOWN;
 		info->sector_count = 0;
 		info->size = 0;
@@ -291,7 +291,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 	DWORD cmd_erase[6] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL,
 						   0x0080008000800080LL, 0x00AA00AA00AA00AALL,
 						   0x0055005500550055LL, 0x0030003000300030LL };
-	
+
 	if ((s_first < 0) || (s_first > s_last)) {
 		if (info->flash_id == FLASH_UNKNOWN) {
 			printf ("- missing\n");
@@ -319,7 +319,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 	/* Enable FPU */
 	msr = get_msr();
 	set_msr ( msr | MSR_FP );
-						   
+
 	/* Disable interrupts which might cause a timeout here */
 	flag = disable_interrupts ();
 
@@ -344,7 +344,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 
 	/* Restore FPU */
 	set_msr (msr);
-	
+
 	/* wait at least 80us - let's wait 1 ms */
 	udelay (1000);
 
@@ -373,7 +373,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
   DONE:
 	/* reset to read mode */
 	flash_reset ();
-	
+
 	printf (" done\n");
 	return 0;
 }
@@ -446,7 +446,7 @@ static int write_dword (flash_info_t * info, ulong dest, unsigned char *pdata)
 	DWORD data;
 	DWORD cmd_write[3] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL,
 						   0x00A000A000A000A0LL };
-						   
+
 	for (data = 0, i = 0; i < 8; i++)
 		data = (data << 8) + *pdata++;
 
@@ -454,11 +454,11 @@ static int write_dword (flash_info_t * info, ulong dest, unsigned char *pdata)
 	if ((*(DWORD*)dest & data) != data) {
 		return (2);
 	}
-	
+
 	/* Enable FPU */
 	msr = get_msr();
 	set_msr( msr | MSR_FP );
-	
+
 	/* Disable interrupts which might cause a timeout here */
 	flag = disable_interrupts ();
 
@@ -473,7 +473,7 @@ static int write_dword (flash_info_t * info, ulong dest, unsigned char *pdata)
 
 	/* Restore FPU */
 	set_msr(msr);
-	
+
 	/* data polling for D7 */
 	start = get_timer (0);
 	while (*(volatile DWORD*)dest != data ) {

board/ppmc7xx/init.S

@@ -21,314 +21,314 @@ board_asm_init:
       ori    r4,r4,0x0000
       lis    r5,0xFEE0
       ori    r5,r5,0x0000
-      lis    r3,0x8000          # ADDR_00                        
+      lis    r3,0x8000          # ADDR_00
       ori    r3,r3,0x0000
       stwbrx    r3,0,r4
-      li     r3,0x1057          # VENDOR                         
+      li     r3,0x1057          # VENDOR
       li    r8, 0x0
       sthbrx    r3,r8,r5
-      lis    r3,0x8000          # ADDR_02                        
+      lis    r3,0x8000          # ADDR_02
       ori    r3,r3,0x0002
       stwbrx    r3,0,r4
-      li     r3,0x0004          # ID                             
+      li     r3,0x0004          # ID
       li    r8, 0x2
       sthbrx    r3,r8,r5
-      lis    r3,0x8000          # ADDR_04                        
+      lis    r3,0x8000          # ADDR_04
       ori    r3,r3,0x0004
       stwbrx    r3,0,r4
-      li     r3,0x0006          # PCICMD                         
+      li     r3,0x0006          # PCICMD
       li    r8, 0x0
       sthbrx    r3,r8,r5
-      lis    r3,0x8000          # ADDR_06                        
+      lis    r3,0x8000          # ADDR_06
       ori    r3,r3,0x0006
       stwbrx    r3,0,r4
-      li     r3,0x00A0          # PCISTAT                        
+      li     r3,0x00A0          # PCISTAT
       li    r8, 0x2
       sthbrx    r3,r8,r5
-      lis    r3,0x8000          # ADDR_08                        
+      lis    r3,0x8000          # ADDR_08
       ori    r3,r3,0x0008
       stwbrx    r3,0,r4
-      li     r3,0x10            # REVID                          
+      li     r3,0x10            # REVID
       stb    r3,0x0(r5)
-      lis    r3,0x8000          # ADDR_09                        
+      lis    r3,0x8000          # ADDR_09
       ori    r3,r3,0x0009
       stwbrx    r3,0,r4
-      li     r3,0x00            # PROGIR                         
+      li     r3,0x00            # PROGIR
       stb    r3,0x1(r5)
-      lis    r3,0x8000          # ADDR_0A                        
+      lis    r3,0x8000          # ADDR_0A
       ori    r3,r3,0x000A
       stwbrx    r3,0,r4
-      li     r3,0x00            # SUBCCODE                       
+      li     r3,0x00            # SUBCCODE
       stb    r3,0x2(r5)
-      lis    r3,0x8000          # ADDR_0B                        
+      lis    r3,0x8000          # ADDR_0B
       ori    r3,r3,0x000B
       stwbrx    r3,0,r4
-      li     r3,0x06            # PBCCR                          
+      li     r3,0x06            # PBCCR
       stb    r3,0x3(r5)
-      lis    r3,0x8000          # ADDR_0C                        
+      lis    r3,0x8000          # ADDR_0C
       ori    r3,r3,0x000C
       stwbrx    r3,0,r4
-      li     r3,0x08            # PCLSR                          
+      li     r3,0x08            # PCLSR
       stb    r3,0x0(r5)
-      lis    r3,0x8000          # ADDR_0D                        
+      lis    r3,0x8000          # ADDR_0D
       ori    r3,r3,0x000D
       stwbrx    r3,0,r4
-      li     r3,0x00            # PLTR                           
+      li     r3,0x00            # PLTR
       stb    r3,0x1(r5)
-      lis    r3,0x8000          # ADDR_0E                        
+      lis    r3,0x8000          # ADDR_0E
       ori    r3,r3,0x000E
       stwbrx    r3,0,r4
-      li     r3,0x00            # HEADTYPE                       
+      li     r3,0x00            # HEADTYPE
       stb    r3,0x2(r5)
-      lis    r3,0x8000          # ADDR_0F                        
+      lis    r3,0x8000          # ADDR_0F
       ori    r3,r3,0x000F
       stwbrx    r3,0,r4
-      li     r3,0x00            # BISTCTRL                       
+      li     r3,0x00            # BISTCTRL
       stb    r3,0x3(r5)
-      lis    r3,0x8000          # ADDR_10                        
+      lis    r3,0x8000          # ADDR_10
       ori    r3,r3,0x0010
       stwbrx    r3,0,r4
-      lis    r3,0x0000          # LMBAR                          
+      lis    r3,0x0000          # LMBAR
       ori    r3,r3,0x0008
       li    r8, 0x0
       stwbrx    r3,r8,r5
-      lis    r3,0x8000          # ADDR_14                        
+      lis    r3,0x8000          # ADDR_14
       ori    r3,r3,0x0014
       stwbrx    r3,0,r4
-      lis    r3,0xF000          # PCSRBAR                        
+      lis    r3,0xF000          # PCSRBAR
       ori    r3,r3,0x0000
       li    r8, 0x0
       stwbrx    r3,r8,r5
-      lis    r3,0x8000          # ADDR_3C                        
+      lis    r3,0x8000          # ADDR_3C
       ori    r3,r3,0x003C
       stwbrx    r3,0,r4
-      li     r3,0x00            # ILR                            
+      li     r3,0x00            # ILR
       stb    r3,0x0(r5)
-      lis    r3,0x8000          # ADDR_3D                        
+      lis    r3,0x8000          # ADDR_3D
       ori    r3,r3,0x003D
       stwbrx    r3,0,r4
-      li     r3,0x01            # INTPIN                         
+      li     r3,0x01            # INTPIN
       stb    r3,0x1(r5)
-      lis    r3,0x8000          # ADDR_3E                        
+      lis    r3,0x8000          # ADDR_3E
       ori    r3,r3,0x003E
       stwbrx    r3,0,r4
-      li     r3,0x00            # MIN_GNT                        
+      li     r3,0x00            # MIN_GNT
       stb    r3,0x2(r5)
-      lis    r3,0x8000          # ADDR_3F                        
+      lis    r3,0x8000          # ADDR_3F
       ori    r3,r3,0x003F
       stwbrx    r3,0,r4
-      li     r3,0x00            # MAX_LAT                        
+      li     r3,0x00            # MAX_LAT
       stb    r3,0x3(r5)
-      lis    r3,0x8000          # ADDR_40                        
+      lis    r3,0x8000          # ADDR_40
       ori    r3,r3,0x0040
       stwbrx    r3,0,r4
-      li     r3,0x00            # BUSNB                          
+      li     r3,0x00            # BUSNB
       stb    r3,0x0(r5)
-      lis    r3,0x8000          # ADDR_41                        
+      lis    r3,0x8000          # ADDR_41
       ori    r3,r3,0x0041
       stwbrx    r3,0,r4
-      li     r3,0x00            # SBUSNB                         
+      li     r3,0x00            # SBUSNB
       stb    r3,0x1(r5)
-      lis    r3,0x8000          # ADDR_46                        
+      lis    r3,0x8000          # ADDR_46
       ori    r3,r3,0x0046
       stwbrx    r3,0,r4
-#      li     r3,0xE080          # PCIARB                         
-      li     r3,-0x1F80          # PCIARB                         
+#      li     r3,0xE080          # PCIARB
+      li     r3,-0x1F80          # PCIARB
       li    r8, 0x2
       sthbrx    r3,r8,r5
-      lis    r3,0x8000          # ADDR_70                        
+      lis    r3,0x8000          # ADDR_70
       ori    r3,r3,0x0070
       stwbrx    r3,0,r4
-      li     r3,0x0000          # PMCR1                          
+      li     r3,0x0000          # PMCR1
       li    r8, 0x0
       sthbrx    r3,r8,r5
-      lis    r3,0x8000          # ADDR_72                        
+      lis    r3,0x8000          # ADDR_72
       ori    r3,r3,0x0072
       stwbrx    r3,0,r4
-      li     r3,0xC0            # PMCR2                          
+      li     r3,0xC0            # PMCR2
       stb    r3,0x2(r5)
-      lis    r3,0x8000          # ADDR_73                        
+      lis    r3,0x8000          # ADDR_73
       ori    r3,r3,0x0073
       stwbrx    r3,0,r4
-      li     r3,0xEF            # ODCR                           
+      li     r3,0xEF            # ODCR
       stb    r3,0x3(r5)
-      lis    r3,0x8000          # ADDR_74                        
+      lis    r3,0x8000          # ADDR_74
       ori    r3,r3,0x0074
       stwbrx    r3,0,r4
-      li     r3,0x7D00          # CLKDCR                         
+      li     r3,0x7D00          # CLKDCR
       li    r8, 0x0
       sthbrx    r3,r8,r5
-      lis    r3,0x8000          # ADDR_76                        
+      lis    r3,0x8000          # ADDR_76
       ori    r3,r3,0x0076
       stwbrx    r3,0,r4
-      li     r3,0x00            # MDCR                           
+      li     r3,0x00            # MDCR
       stb    r3,0x2(r5)
       lis    r6,0xFCE0
       ori    r6,r6,0x0000       # r6 is the EUMBAR Base Address
-      lis    r3,0x8000          # ADDR_78                        
+      lis    r3,0x8000          # ADDR_78
       ori    r3,r3,0x0078
       stwbrx    r3,0,r4
-      lis    r3,0xFCE0          # EUMBBAR                        
+      lis    r3,0xFCE0          # EUMBBAR
       ori    r3,r3,0x0000
       li    r8, 0x0
       stwbrx    r3,r8,r5
-      lis    r3,0x8000          # ADDR_80                        
+      lis    r3,0x8000          # ADDR_80
       ori    r3,r3,0x0080
       stwbrx    r3,0,r4
-      lis    r3,0xFFFF          # MSADDR1                        
+      lis    r3,0xFFFF          # MSADDR1
       ori    r3,r3,0x4000
       li    r8, 0x0
       stwbrx    r3,r8,r5
-      lis    r3,0x8000          # ADDR_84                        
+      lis    r3,0x8000          # ADDR_84
       ori    r3,r3,0x0084
       stwbrx    r3,0,r4
-      lis    r3,0xFFFF          # MSADDR2                        
+      lis    r3,0xFFFF          # MSADDR2
       ori    r3,r3,0xFFFF
       li    r8, 0x0
       stwbrx    r3,r8,r5
-      lis    r3,0x8000          # ADDR_88                        
+      lis    r3,0x8000          # ADDR_88
       ori    r3,r3,0x0088
       stwbrx    r3,0,r4
-      lis    r3,0x0303          # EMSADDR1                       
+      lis    r3,0x0303          # EMSADDR1
       ori    r3,r3,0x0000
       li    r8, 0x0
       stwbrx    r3,r8,r5
-      lis    r3,0x8000          # ADDR_8C                        
+      lis    r3,0x8000          # ADDR_8C
       ori    r3,r3,0x008C
       stwbrx    r3,0,r4
-      lis    r3,0x0303          # EMSADDR2                       
+      lis    r3,0x0303          # EMSADDR2
       ori    r3,r3,0x0303
       li    r8, 0x0
       stwbrx    r3,r8,r5
-      lis    r3,0x8000          # ADDR_90                        
+      lis    r3,0x8000          # ADDR_90
       ori    r3,r3,0x0090
       stwbrx    r3,0,r4
-      lis    r3,0xFFFF          # EMEADDR1                       
+      lis    r3,0xFFFF          # EMEADDR1
       ori    r3,r3,0x7F3F
       li    r8, 0x0
       stwbrx    r3,r8,r5
-      lis    r3,0x8000          # ADDR_94                        
+      lis    r3,0x8000          # ADDR_94
       ori    r3,r3,0x0094
       stwbrx    r3,0,r4
-      lis    r3,0xFFFF          # EMEADDR2                       
+      lis    r3,0xFFFF          # EMEADDR2
       ori    r3,r3,0xFFFF
       li    r8, 0x0
       stwbrx    r3,r8,r5
-      lis    r3,0x8000          # ADDR_98                        
+      lis    r3,0x8000          # ADDR_98
       ori    r3,r3,0x0098
       stwbrx    r3,0,r4
-      lis    r3,0x0303          # EXTEMEM1                       
+      lis    r3,0x0303          # EXTEMEM1
       ori    r3,r3,0x0000
       li    r8, 0x0
       stwbrx    r3,r8,r5
-      lis    r3,0x8000          # ADDR_9C                        
+      lis    r3,0x8000          # ADDR_9C
       ori    r3,r3,0x009C
       stwbrx    r3,0,r4
-      lis    r3,0x0303          # EXTEMEM2                       
+      lis    r3,0x0303          # EXTEMEM2
       ori    r3,r3,0x0303
       li    r8, 0x0
       stwbrx    r3,r8,r5
-      lis    r3,0x8000          # ADDR_A0                        
+      lis    r3,0x8000          # ADDR_A0
       ori    r3,r3,0x00A0
       stwbrx    r3,0,r4
-      li     r3,0x03            # MEMBNKEN                       
+      li     r3,0x03            # MEMBNKEN
       stb    r3,0x0(r5)
-      lis    r3,0x8000          # ADDR_A3                        
+      lis    r3,0x8000          # ADDR_A3
       ori    r3,r3,0x00A3
       stwbrx    r3,0,r4
-      li     r3,0x00            # MEMPMODE                       
+      li     r3,0x00            # MEMPMODE
       stb    r3,0x3(r5)
-      lis    r3,0x8000          # ADDR_B8                        
+      lis    r3,0x8000          # ADDR_B8
       ori    r3,r3,0x00B8
       stwbrx    r3,0,r4
-      li     r3,0x00            # ECCCNT                         
+      li     r3,0x00            # ECCCNT
       stb    r3,0x0(r5)
-      lis    r3,0x8000          # ADDR_B9                        
+      lis    r3,0x8000          # ADDR_B9
       ori    r3,r3,0x00B9
       stwbrx    r3,0,r4
-      li     r3,0x00            # ECCTRG                         
+      li     r3,0x00            # ECCTRG
       stb    r3,0x1(r5)
-      lis    r3,0x8000          # ADDR_C0                        
+      lis    r3,0x8000          # ADDR_C0
       ori    r3,r3,0x00C0
       stwbrx    r3,0,r4
-      li     r3,0xFF            # ERRENR1                        
+      li     r3,0xFF            # ERRENR1
       stb    r3,0x0(r5)
-      lis    r3,0x8000          # ADDR_C1                        
+      lis    r3,0x8000          # ADDR_C1
       ori    r3,r3,0x00C1
       stwbrx    r3,0,r4
-      li     r3,0x00            # ERRDR1                         
+      li     r3,0x00            # ERRDR1
       stb    r3,0x1(r5)
-      lis    r3,0x8000          # ADDR_C3                        
+      lis    r3,0x8000          # ADDR_C3
       ori    r3,r3,0x00C3
       stwbrx    r3,0,r4
-      li     r3,0x50            # IPBESR                         
+      li     r3,0x50            # IPBESR
       stb    r3,0x3(r5)
-      lis    r3,0x8000          # ADDR_C4                        
+      lis    r3,0x8000          # ADDR_C4
       ori    r3,r3,0x00C4
       stwbrx    r3,0,r4
-      li     r3,0xBF            # ERRENR2                        
+      li     r3,0xBF            # ERRENR2
       stb    r3,0x0(r5)
-      lis    r3,0x8000          # ADDR_C5                        
+      lis    r3,0x8000          # ADDR_C5
       ori    r3,r3,0x00C5
       stwbrx    r3,0,r4
-      li     r3,0x00            # ERRDR2                         
+      li     r3,0x00            # ERRDR2
       stb    r3,0x1(r5)
-      lis    r3,0x8000          # ADDR_C7                        
+      lis    r3,0x8000          # ADDR_C7
       ori    r3,r3,0x00C7
       stwbrx    r3,0,r4
-      li     r3,0x00            # PCIBESR                        
+      li     r3,0x00            # PCIBESR
       stb    r3,0x3(r5)
-      lis    r3,0x8000          # ADDR_C8                        
+      lis    r3,0x8000          # ADDR_C8
       ori    r3,r3,0x00C8
       stwbrx    r3,0,r4
-      lis    r3,0x0000          # BERRADDR                       
+      lis    r3,0x0000          # BERRADDR
       ori    r3,r3,0xE0FE
       li    r8, 0x0
       stwbrx    r3,r8,r5
-      lis    r3,0x8000          # ADDR_E0                        
+      lis    r3,0x8000          # ADDR_E0
       ori    r3,r3,0x00E0
       stwbrx    r3,0,r4
-      li     r3,0xC0            # AMBOR                          
+      li     r3,0xC0            # AMBOR
       stb    r3,0x0(r5)
-      lis    r3,0x8000          # ADDR_F4                        
+      lis    r3,0x8000          # ADDR_F4
       ori    r3,r3,0x00F4
       stwbrx    r3,0,r4
-      lis    r3,0x0000          # MCCR2                          
+      lis    r3,0x0000          # MCCR2
       ori    r3,r3,0x020C
       li    r8, 0x0
       stwbrx    r3,r8,r5
-      lis    r3,0x8000          # ADDR_F8                        
+      lis    r3,0x8000          # ADDR_F8
       ori    r3,r3,0x00F8
       stwbrx    r3,0,r4
-      lis    r3,0x0230          # MCCR3                          
+      lis    r3,0x0230          # MCCR3
       ori    r3,r3,0x0000
       li    r8, 0x0
       stwbrx    r3,r8,r5
-      lis    r3,0x8000          # ADDR_FC                        
+      lis    r3,0x8000          # ADDR_FC
       ori    r3,r3,0x00FC
       stwbrx    r3,0,r4
-      lis    r3,0x2532          # MCCR4                          
+      lis    r3,0x2532          # MCCR4
       ori    r3,r3,0x2220
       li    r8, 0x0
       stwbrx    r3,r8,r5
-      lis    r3,0x8000          # ADDR_F0                        
+      lis    r3,0x8000          # ADDR_F0
       ori    r3,r3,0x00F0
       stwbrx    r3,0,r4
-      lis    r3,0xFFC8          # MCCR1                          
+      lis    r3,0xFFC8          # MCCR1
       ori    r3,r3,0x0000
       li    r8, 0x0
       stwbrx    r3,r8,r5
-      lis    r3,0x8000          # ADDR_A8                        
+      lis    r3,0x8000          # ADDR_A8
       ori    r3,r3,0x00A8
       stwbrx    r3,0,r4
-      lis    r3,0xFF14          # PICR1                          
+      lis    r3,0xFF14          # PICR1
       ori    r3,r3,0x1CC8
       li    r8, 0x0
       stwbrx    r3,r8,r5
-      lis    r3,0x8000          # ADDR_AC                        
+      lis    r3,0x8000          # ADDR_AC
       ori    r3,r3,0x00AC
       stwbrx    r3,0,r4
-      lis    r3,0x0000          # PICR2                          
+      lis    r3,0x0000          # PICR2
       ori    r3,r3,0x0000
       li    r8, 0x0
       stwbrx    r3,r8,r5

board/ppmc7xx/ppmc7xx.c

@@ -1,9 +1,9 @@
 /*
  * ppmc7xx.c
  * ---------
- * 
+ *
  * Main board-specific routines for Wind River PPMC 7xx/74xx board.
- * 
+ *
  * By Richard Danter (richard.danter@windriver.com)
  * Copyright (C) 2005 Wind River Systems
  */
@@ -24,7 +24,7 @@ extern void _start_warm(void);
 
 /*
  * initdram()
- * 
+ *
  * This function normally initialises the (S)DRAM of the system. For this board
  * the SDRAM was already initialised by board_asm_init (see init.S) so we just
  * return the size of RAM.
@@ -37,12 +37,12 @@ long initdram( int board_type )
 
 /*
  * after_reloc()
- * 
+ *
  * This is called after U-Boot has been copied from Flash/ROM to RAM. It gives
  * us an opportunity to do some additional setup before the rest of the system
  * is initialised. We don't need to do anything, so we just call board_init_r()
  * which should never return.
- */ 
+ */
 void after_reloc( ulong dest_addr, gd_t* gd )
 {
 	/* Jump to the main U-Boot board init code */
@@ -52,7 +52,7 @@ void after_reloc( ulong dest_addr, gd_t* gd )
 
 /*
  * checkboard()
- * 
+ *
  * We could do some board level checks here, such as working out what version
  * it is, but for this board we simply display it's name (on the console).
  */
@@ -65,7 +65,7 @@ int checkboard( void )
 
 /*
  * misc_init_r
- * 
+ *
  * Used for other setup which needs to be done late in the bring-up phase.
  */
 int misc_init_r( void )
@@ -78,27 +78,27 @@ int misc_init_r( void )
 
 	/* Enable the I-Cache */
 	icache_enable();
-	
+
 	return 0;
 }
 
 
 /*
  * do_reset()
- * 
+ *
  * Shell command to reset the board.
  */
 void do_reset( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] )
 {
 	printf( "Resetting...\n" );
-	
+
 	/* Disabe and invalidate cache */
 	icache_disable();
 	dcache_disable();
 
 	/* Jump to warm start (in RAM) */
 	_start_warm();
-	
+
 	/* Should never get here */
 	while(1);
 }

board/tqm5200/Makefile

@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= lib$(BOARD).a
 
-OBJS	:= $(BOARD).o cmd_stk52xx.o
+OBJS	:= $(BOARD).o cmd_stk52xx.o cmd_tb5200.o
 
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS)

board/tqm5200/cmd_stk52xx.c

@@ -30,6 +30,7 @@
 #include <command.h>
 
 #if (CONFIG_COMMANDS & CFG_CMD_BSP)
+#if defined (CONFIG_STK52XX)
 
 #define DEFAULT_VOL	45
 #define DEFAULT_FREQ	500
@@ -60,7 +61,6 @@ static int spi_transmit(unsigned char data);
 static void pcm1772_write_reg(unsigned char addr, unsigned char data);
 static void set_attenuation(unsigned char attenuation);
 
-#ifdef CONFIG_STK52XX
 static void spi_init(void)
 {
 	struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI;

board/tqm5200/cmd_tb5200.c

@@ -0,0 +1,104 @@
+/*
+ * (C) Copyright 2005 - 2006
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * TB5200 specific functions
+ */
+/*#define DEBUG*/
+
+#include <common.h>
+#include <command.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_BSP)
+#if defined (CONFIG_TB5200)
+
+#define SM501_PANEL_DISPLAY_CONTROL	0x00080000UL
+
+static void led_init(void)
+{
+	struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
+
+	/* configure timer 4 for simple GPIO output */
+	gpt->gpt4.emsr |=  0x00000024;
+}
+
+int cmd_led(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
+
+	led_init();
+
+	if (strcmp (argv[1], "on") == 0) {
+		debug ("switch status LED on\n");
+		gpt->gpt4.emsr |=  (1 << 4);
+	} else if (strcmp (argv[1], "off") == 0) {
+		debug ("switch status LED off\n");
+		gpt->gpt4.emsr &=  ~(1 << 4);
+	} else {
+		printf ("Usage:\nled on/off\n");
+		return 1;
+	}
+
+	return 0;
+}
+
+static void sm501_backlight (unsigned int state)
+{
+	if (state == 1) {
+		*(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) |=
+			(1 << 26) | (1 << 27);
+	} else if (state == 0)
+		*(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) &=
+			~((1 << 26) | (1 << 27));
+}
+
+int cmd_backlight(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	if (strcmp (argv[1], "on") == 0) {
+		debug ("switch backlight on\n");
+		sm501_backlight (1);
+	} else if (strcmp (argv[1], "off") == 0) {
+		debug ("switch backlight off\n");
+		sm501_backlight (0);
+	} else {
+		printf ("Usage:\nbacklight on/off\n");
+		return 1;
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	led ,	2,	1,	cmd_led,
+	"led     - switch status LED on or off\n",
+	"on/off\n"
+);
+
+U_BOOT_CMD(
+	backlight ,	2,	1,	cmd_backlight,
+	"backlight - switch backlight on or off\n",
+	"on/off\n"
+	);
+
+#endif /* CONFIG_STK52XX */
+#endif /* CFG_CMD_BSP */

board/tqm5200/tqm5200.c

@@ -260,6 +260,9 @@ int checkboard (void)
 #if defined (CONFIG_STK52XX)
 	puts ("       on a STK52XX baseboard\n");
 #endif
+#if defined (CONFIG_TB5200)
+	puts ("       on a TB5200 baseboard\n");
+#endif
 
 	return 0;
 }
@@ -567,9 +570,14 @@ void video_get_info_str (int line_number, char *info)
 {
 	if (line_number == 1) {
 	strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
-#if defined (CONFIG_STK52XX)
+#if defined (CONFIG_STK52XX) || defined (CONFIG_TB5200)
 	} else if (line_number == 2) {
+#if defined (CONFIG_STK52XX)
 		strcpy (info, "        on a STK52XX baseboard");
+#endif
+#if defined (CONFIG_TB5200)
+		strcpy (info, "        on a TB5200 baseboard");
+#endif
 #endif
 	}
 	else {

board/tqm85xx/tqm85xx.c

@@ -423,4 +423,3 @@ int board_early_init_r (void)
 	return (0);
 }
 #endif /* CONFIG_BOARD_EARLY_INIT_R */
-

cpu/ppc4xx/serial.c

@@ -635,7 +635,7 @@ void serial_setbrg (void)
 
 	tmp = gd->baudrate * udiv * 16;
 	bdiv = (clk + tmp / 2) / tmp;
-#endif /* !defined(CFG_EXT_SERIAL_CLOCK) && (...) */ 
+#endif /* !defined(CFG_EXT_SERIAL_CLOCK) && (...) */
 
 #if defined(CONFIG_SERIAL_MULTI)
 	out8 (dev_base + UART_LCR, 0x80);	/* set DLAB bit */

cpu/ppc4xx/start.S

@@ -159,7 +159,7 @@ _start_440:
 	| Core bug fix.  Clear the esr
 	+-----------------------------------------------------------------*/
 	li	r0,0
-        mtspr	esr,r0
+	mtspr	esr,r0
 	/*----------------------------------------------------------------*/
 	/* Clear and set up some registers. */
 	/*----------------------------------------------------------------*/

drivers/Makefile

@@ -50,7 +50,7 @@ OBJS	= 3c589.o 5701rls.o ali512x.o \
 	  videomodes.o w83c553f.o \
 	  ks8695eth.o \
 	  pxa_pcmcia.o mpc8xx_pcmcia.o tqm8xx_pcmcia.o	\
-	  rpx_pcmcia.o 
+	  rpx_pcmcia.o
 
 all:	$(LIB)
 

drivers/tqm8xx_pcmcia.c

@@ -191,7 +191,7 @@ int pcmcia_hardware_enable(int slot)
 	udelay(10000);
 	debug ("[%d] %s: PIPR(%p)=0x%x\n", __LINE__,__FUNCTION__,
 	       &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
-	
+
 	if (check_card_is_absent(slot)) {
 		printf ("   No Card found\n");
 		return (1);
@@ -206,7 +206,7 @@ int pcmcia_hardware_enable(int slot)
 	       reg,
 	       (reg&PCMCIA_VS1(slot))?"n":"ff",
 	       (reg&PCMCIA_VS2(slot))?"n":"ff");
-	
+
 	if ((reg & mask) == mask) {
 		power_on_5_0(slot);
 		puts (" 5.0V card found: ");
@@ -228,7 +228,7 @@ int pcmcia_hardware_enable(int slot)
 	reg &= ~__MY_PCMCIA_GCRX_CXRESET;	/* active high */
 	reg |= __MY_PCMCIA_GCRX_CXOE;		/* active low  */
 	reg &= ~NSCU_GCRX_CXOE;
-	
+
 	PCMCIA_PGCRX(slot) = reg;
 
 	udelay(250000);	/* some cards need >150 ms to come up :-( */
@@ -285,7 +285,7 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp)
 	reg |= __MY_PCMCIA_GCRX_CXRESET;	/* active high */
 	reg &= ~__MY_PCMCIA_GCRX_CXOE;		/* active low  */
 	reg |= NSCU_GCRX_CXOE;			/* active low  */
-	
+
 	PCMCIA_PGCRX(slot) = reg;
 	udelay(500);
 

include/configs/TB5200.h

@@ -0,0 +1,470 @@
+/*
+ * (C) Copyright 2003-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004-2006
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
+#define CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU) */
+#define CONFIG_TQM5200		1	/* ... on TQM5200 module */
+#define CONFIG_TB5200		1	/* ... on a TB5200 base board */
+
+#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
+
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
+#define BOOTFLAG_WARM		0x02	/* Software reboot	     */
+
+#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* default console is on PSC1 */
+#define CONFIG_SERIAL_MULTI	1	/* support multiple consoles */
+#define CONFIG_PSC_CONSOLE2	6	/* second console is on PSC6 */
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * Video console
+ */
+#if 1
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_SM501
+#define CONFIG_VIDEO_SM501_32BPP
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_CONSOLE_EXTRA_INFO
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_SPLASH_SCREEN
+#define CFG_CONSOLE_IS_IN_ENV
+#endif
+
+#ifdef CONFIG_VIDEO
+#define ADD_BMP_CMD		CFG_CMD_BMP
+#else
+#define ADD_BMP_CMD		0
+#endif
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+/* USB */
+#define CONFIG_USB_OHCI
+#define ADD_USB_CMD		CFG_CMD_USB | CFG_CMD_FAT
+#define CONFIG_USB_STORAGE
+
+/* POST support */
+#define CONFIG_POST		(CFG_POST_MEMORY   | \
+				 CFG_POST_CPU	   | \
+				 CFG_POST_I2C)
+
+#ifdef CONFIG_POST
+#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
+/* preserve space for the post_word at end of on-chip SRAM */
+#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
+#else
+#define CFG_CMD_POST_DIAG 0
+#endif
+
+/* IDE */
+#define ADD_IDE_CMD		(CFG_CMD_IDE | CFG_CMD_FAT | CFG_CMD_EXT2)
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				ADD_BMP_CMD	| \
+				ADD_IDE_CMD	| \
+				ADD_PCI_CMD	| \
+				ADD_USB_CMD	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_ECHO	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_JFFS2	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_POST_DIAG | \
+				CFG_CMD_REGINFO | \
+				CFG_CMD_SNTP	| \
+				CFG_CMD_BSP)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define	CONFIG_TIMESTAMP		/* display image timestamps */
+
+#if (TEXT_BASE == 0xFC000000)		/* Boot low */
+#   define CFG_LOWBOOT		1
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT	"echo;" \
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"rootpath=/opt/eldk/ppc_6xx\0"					\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"bootfile=/tftpboot/tqm5200/uImage\0"				\
+	"load=tftp 200000 $(u-boot)\0"					\
+	"u-boot=/tftpboot/tqm5200/u-boot.bin\0"				\
+	"update=protect off FC000000 FC05FFFF;"				\
+		"erase FC000000 FC05FFFF;"				\
+		"cp.b 200000 FC000000 ${filesize};"			\
+		"protect on FC000000 FC05FFFF\0"			\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run net_nfs"
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#define CFG_IPBSPEED_133		/* define for 133MHz speed */
+
+#if defined(CFG_IPBSPEED_133)
+/*
+ * PCI Bus clocking configuration
+ *
+ * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
+ * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
+ * been tested with a IPB Bus Clock of 66 MHz.
+ */
+#define CFG_PCISPEED_66			/* define for 66MHz speed */
+#endif
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#define CFG_I2C_MODULE		2	/* Select I2C module #2 */
+
+/*
+ * I2C clock frequency
+ *
+ * Please notice, that the resulting clock frequency could differ from the
+ * configured value. This is because the I2C clock is derived from system
+ * clock over a frequency divider with only a few divider values. U-boot
+ * calculates the best approximation for CFG_I2C_SPEED. However the calculated
+ * approximation allways lies below the configured value, never above.
+ */
+#define CFG_I2C_SPEED		100000 /* 100 kHz */
+#define CFG_I2C_SLAVE		0x7F
+
+/*
+ * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
+ * also). For other EEPROMs configuration should be verified. On Mini-FAP the
+ * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
+ * same configuration could be used.
+ */
+#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x */
+#define CFG_I2C_EEPROM_ADDR_LEN		2
+#define CFG_EEPROM_PAGE_WRITE_BITS	5	/* =32 Bytes per write */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	20
+
+/* List of I2C addresses to be verified by POST */
+#undef I2C_ADDR_LIST
+#define I2C_ADDR_LIST	{	CFG_I2C_EEPROM_ADDR,	\
+				CFG_I2C_RTC_ADDR,	\
+				CFG_I2C_SLAVE }
+
+/*
+ * Flash configuration
+ */
+#define CFG_FLASH_BASE		TEXT_BASE /* 0xFC000000 */
+
+/* use CFI flash driver if no module variant is spezified */
+#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER	1	/* Use the common driver */
+#define CFG_FLASH_BANKS_LIST	{ CFG_BOOTCS_START }
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_SIZE		0x04000000 /* 64 MByte */
+#define CFG_MAX_FLASH_SECT	512	/* max num of sects on one chip */
+#undef CFG_FLASH_USE_BUFFER_WRITE	/* not supported yet for AMD */
+
+#if !defined(CFG_LOWBOOT)
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00760000 + 0x00800000)
+#else	/* CFG_LOWBOOT */
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00060000)
+#endif	/* CFG_LOWBOOT */
+#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks
+					   (= chip selects) */
+#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
+
+/* Dynamic MTD partition support */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor0=TQM5200-0"
+#define MTDPARTS_DEFAULT	"mtdparts=TQM5200-0:640k(firmware),"	\
+						"1408k(kernel),"	\
+						"2m(initrd),"		\
+						"4m(small-fs),"		\
+						"16m(big-fs),"		\
+						"8m(misc)"
+
+/*
+ * Environment settings
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE		0x10000
+#define CFG_ENV_SECT_SIZE	0x20000
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#define	CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+
+/*
+ * Memory map
+ */
+#define CFG_MBAR		0xF0000000
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_DEFAULT_MBAR	0x80000000
+
+/* Use ON-Chip SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
+#ifdef CONFIG_POST
+/* preserve space for the post_word at end of on-chip SRAM */
+#define CFG_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
+#else
+#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE
+#endif
+
+
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE	TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#   define CFG_RAMBOOT		1
+#endif
+
+#define CFG_MONITOR_LEN		(384 << 10)	/* Reserve 384 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc()	*/
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+/*
+ * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
+ */
+/* #define CONFIG_FEC_10MBIT 1 */
+#define CONFIG_PHY_ADDR		0x00
+
+/*
+ * GPIO configuration
+ *
+ * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
+ *	Bit 0 (mask: 0x80000000): 1
+ * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
+ *	00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
+ *	01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
+ *	      Use for REV200 STK52XX boards. Do not use with REV100 modules
+ *	      (because, there I2C1 is used as I2C bus)
+ * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
+ * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
+ *	000 -> All PSC2 pins are GIOPs
+ *	001 -> CAN1/2 on PSC2 pins
+ *	       Use for REV100 STK52xx boards
+ * use PSC3: Bits 20:23 (mask: 0x00000300):
+ *      0001 -> USB2
+ *      0000 -> GPIO
+ * use PSC6:
+ *   on STK52xx:
+ *	use as UART. Pins PSC6_0 to PSC6_3 are used.
+ *	Bits 9:11 (mask: 0x00700000):
+ *	   101 -> PSC6 : Extended POST test is not available
+ *   on MINI-FAP and TQM5200_IB:
+ *	use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
+ *	   000 -> PSC6 could not be used as UART, CODEC or IrDA
+ *   GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
+ *   tests.
+ */
+#define CFG_GPS_PORT_CONFIG	0x81500114
+
+/*
+ * RTC configuration
+ */
+#define CONFIG_RTC_M41T11	1
+#define CFG_I2C_RTC_ADDR	0x68
+#define CFG_M41T11_BASE_YEAR	1900    /* because Linux uses the same base
+					   year */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory	    */
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS		16	/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+/* Enable an alternate, more extensive memory test */
+#define CFG_ALT_MEMTEST
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
+#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+/*
+ * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
+ * which is normally part of the default commands (CFV_CMD_DFL)
+ */
+#define CONFIG_LOOPW
+
+/*
+ * Various low-level settings
+ */
+#if defined(CONFIG_MPC5200)
+#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL		HID0_ICE
+#else
+#define CFG_HID0_INIT		0
+#define CFG_HID0_FINAL		0
+#endif
+
+#define CFG_BOOTCS_START	CFG_FLASH_BASE
+#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
+#ifdef CFG_PCISPEED_66
+#define CFG_BOOTCS_CFG		0x0008DF30 /* for pci_clk  = 66 MHz */
+#else
+#define CFG_BOOTCS_CFG		0x0004DF30 /* for pci_clk = 33 MHz */
+#endif
+#define CFG_CS0_START		CFG_FLASH_BASE
+#define CFG_CS0_SIZE		CFG_FLASH_SIZE
+
+/* automatic configuration of chip selects */
+#ifdef CONFIG_CS_AUTOCONF
+#define CONFIG_LAST_STAGE_INIT
+#endif
+
+/*
+ * SRAM - Do not map below 2 GB in address space, because this area is used
+ * for SDRAM autosizing.
+ */
+#if defined (CONFIG_CS_AUTOCONF)
+#define CFG_CS2_START		0xE5000000
+#define CFG_CS2_SIZE		0x100000	/* 1 MByte */
+#define CFG_CS2_CFG		0x0004D930
+#endif
+
+/*
+ * Grafic controller - Do not map below 2 GB in address space, because this
+ * area is used for SDRAM autosizing.
+ */
+#if defined (CONFIG_CS_AUTOCONF)
+#define SM501_FB_BASE		0xE0000000
+#define CFG_CS1_START		(SM501_FB_BASE)
+#define CFG_CS1_SIZE		0x4000000	/* 64 MByte */
+#define CFG_CS1_CFG		0x8F48FF70
+#define SM501_MMIO_BASE		CFG_CS1_START + 0x03E00000
+#endif
+
+#define CFG_CS_BURST		0x00000000
+#define CFG_CS_DEADCYCLE	0x33333311	/* 1 dead cycle for flash and SM501 */
+
+#define CFG_RESET_ADDRESS	0xff000000
+
+/*-----------------------------------------------------------------------
+ * USB stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_USB_CLOCK	0x0001BBBB
+#define CONFIG_USB_CONFIG	0x00001000
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+#undef	CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card Adapter */
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
+#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
+
+#define CONFIG_IDE_RESET		/* reset for ide supported	*/
+#define CONFIG_IDE_PREINIT
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	2	/* max. 2 drives per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(0x0060)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	(0x005C)
+
+/* Interval between registers						     */
+#define CFG_ATA_STRIDE		4
+
+#endif /* __CONFIG_H */

include/configs/gth2.h

@@ -12,7 +12,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -34,7 +34,7 @@
 
 #define CONFIG_AU1000		1
 
-#define CONFIG_MISC_INIT_R      1
+#define CONFIG_MISC_INIT_R	1
 
 #define CONFIG_ETHADDR		DE:AD:BE:EF:01:02    /* Ethernet address */
 
@@ -59,21 +59,21 @@
 #define CONFIG_AUTOBOOT_DELAY_STR "d"
 #define CONFIG_AUTOBOOT_STOP_STR " "
 
-#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
-#define	CONFIG_BOOTARGS "panic=1"
+#define CONFIG_TIMESTAMP		/* Print image info with timestamp */
+#define CONFIG_BOOTARGS "panic=1"
 
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
+#define CONFIG_EXTRA_ENV_SETTINGS					\
 	"addmisc=setenv bootargs $(bootargs) "				\
-	        "ethaddr=$(ethaddr) \0"					\
-        "netboot=bootp;run addmisc;bootm\0"                             \
-                ""
+		"ethaddr=$(ethaddr) \0"					\
+	"netboot=bootp;run addmisc;bootm\0"				\
+		""
 
 /* Boot from Compact flash partition 2 as default */
 #define CONFIG_BOOTCOMMAND	"ide reset;disk 0x81000000 0:2;run addmisc;bootm"
 
-#define CONFIG_COMMANDS	((CONFIG_CMD_DFL | CFG_CMD_IDE | CFG_CMD_DHCP ) & \
+#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_IDE | CFG_CMD_DHCP ) & \
  ~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FLASH | CFG_CMD_FPGA | \
-   CFG_CMD_MII | CFG_CMD_LOADS  | CFG_CMD_LOADB | CFG_CMD_ELF | \
+   CFG_CMD_MII | CFG_CMD_LOADS	| CFG_CMD_LOADB | CFG_CMD_ELF | \
    CFG_CMD_BDI | CFG_CMD_BEDBUG | CFG_CMD_NFS | CFG_CMD_AUTOSCRIPT ))
 
 #include <cmd_confdefs.h>
@@ -81,11 +81,11 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP				/* undef to save memory      */
-#define	CFG_PROMPT		"GTH2 # "	/* Monitor Command Prompt    */
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size   */
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)  /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args*/
+#define CFG_LONGHELP				/* undef to save memory	     */
+#define CFG_PROMPT		"GTH2 # "	/* Monitor Command Prompt    */
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size   */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)  /* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args*/
 
 #define CFG_MALLOC_LEN		128*1024
 
@@ -93,16 +93,16 @@
 
 #define CFG_MHZ			500
 
-#define CFG_HZ                  (CFG_MHZ * 1000000) /* FIXME causes overflow in net.c */
+#define CFG_HZ			(CFG_MHZ * 1000000) /* FIXME causes overflow in net.c */
 
 #define CFG_SDRAM_BASE		0x80000000     /* Cached addr */
 
-#define	CFG_LOAD_ADDR		0x81000000     /* default load address	*/
+#define CFG_LOAD_ADDR		0x81000000     /* default load address	*/
 
 #define CFG_MEMTEST_START	0x80100000
 #define CFG_MEMTEST_END		0x83000000
 
-#define CONFIG_HW_WATCHDOG      1
+#define CONFIG_HW_WATCHDOG	1
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
@@ -113,8 +113,8 @@
 #define PHYS_FLASH		0xbfc00000 /* Flash Bank #1 */
 
 /* The following #defines are needed to get flash environment right */
-#define	CFG_MONITOR_BASE	TEXT_BASE
-#define	CFG_MONITOR_LEN		(192 << 10)
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MONITOR_LEN		(192 << 10)
 
 #define CFG_INIT_SP_OFFSET	0x400000
 
@@ -125,7 +125,7 @@
 #define CFG_FLASH_ERASE_TOUT	(2 * CFG_HZ) /* Timeout for Flash Erase */
 #define CFG_FLASH_WRITE_TOUT	(2 * CFG_HZ) /* Timeout for Flash Write */
 
-#define	CFG_ENV_IS_NOWHERE	1
+#define CFG_ENV_IS_NOWHERE	1
 
 /* Address and size of Primary Environment Sector	*/
 #define CFG_ENV_ADDR		0xB0030000
@@ -158,21 +158,21 @@
 #define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
 #define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
 
-#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
 #undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
 
 #define CFG_ATA_IDE0_OFFSET	0
 
-#define CFG_ATA_BASE_ADDR       CFG_PCMCIA_IO_BASE
+#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_IO_BASE
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET     0
+#define CFG_ATA_DATA_OFFSET	0
 
-/* Offset for normal register accesses  */
-#define CFG_ATA_REG_OFFSET      0
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	0
 
-/* Offset for alternate registers       */
-#define CFG_ATA_ALT_OFFSET      0x0200
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x0200
 
 /*-----------------------------------------------------------------------
  * Cache Configuration

include/configs/ppmc7xx.h

@@ -1,9 +1,9 @@
 /*
  * ppmc7xx.h
  * ---------
- * 
+ *
  * Wind River PPMC 7xx/74xx board configuration file.
- * 
+ *
  * By Richard Danter (richard.danter@windriver.com)
  * Copyright (C) 2005 Wind River Systems
  */
@@ -16,15 +16,15 @@
 
 
 /*===================================================================
- * 
+ *
  * User configurable settings - Modify to your preference
- * 
+ *
  *===================================================================
  */
 
 /*
  * Debug
- * 
+ *
  * DEBUG			- Define this is you want extra debug info
  * GTREGREAD			- Required to build with debug
  * do_bdinfo			- Required to build with debug
@@ -37,7 +37,7 @@
 
 /*
  * CPU type
- * 
+ *
  * CONFIG_7xx			- We have a 750 or 755 CPU
  * CONFIG_74xx			- We have a 7400 CPU
  * CONFIG_ALTIVEC		- We have altivec enabled CPU (only 7400)
@@ -52,11 +52,11 @@
 
 /*
  * Monitor configuration
- * 
+ *
  * CONFIG_COMMANDS		- List of command sets to include in shell
- * 
+ *
  * The following command sets have been tested and known to work:
- * 
+ *
  * CFG_CMD_CACHE		- Cache control commands
  * CFG_CMD_MEMORY		- Memory display, change and test commands
  * CFG_CMD_FLASH		- Erase and program flash
@@ -91,7 +91,7 @@
 
 /*
  * PCI config
- * 
+ *
  * CONFIG_PCI				- Enable PCI bus
  * CONFIG_PCI_PNP			- Enable Plug & Play support
  * CONFIG_PCI_SCAN_SHOW		- Enable display of devices at startup
@@ -104,7 +104,7 @@
 
 /*
  * Network config
- * 
+ *
  * CONFIG_NET_MULTI			- Support for multiple network interfaces
  * CONFIG_EEPRO100			- Intel 8255x Ethernet Controller
  * CONFIG_EEPRO100_SROM_WRITE - Enable writing to network card ROM
@@ -117,18 +117,18 @@
 
 /*
  * Enable extra init functions
- * 
+ *
  * CONFIG_MISC_INIT_F		- Call pre-relocation init functions
  * CONFIG_MISC_INIT_R		- Call post relocation init functions
  */
 
 #undef	CONFIG_MISC_INIT_F
-#define CONFIG_MISC_INIT_R 
+#define CONFIG_MISC_INIT_R
 
 
 /*
  * Boot config
- * 
+ *
  * CONFIG_BOOTCOMMAND		- Command(s) to execute to auto-boot
  * CONFIG_BOOTDELAY			- How long to wait before auto-boot (in sec)
  */
@@ -142,9 +142,9 @@
 
 
 /*===================================================================
- * 
+ *
  * Board configuration settings - You should not need to modify these
- * 
+ *
  *===================================================================
  */
 
@@ -154,9 +154,9 @@
 
 /*
  * Memory map
- * 
+ *
  * This board runs in a standard CHRP (Map-B) configuration.
- * 
+ *
  *	Type		Start		End			Size	Width	Chip Sel
  *	----------- ----------- ----------- ------- ------- --------
  *	SDRAM		0x00000000	0x04000000	64MB	64b		SDRAMCS0
@@ -164,9 +164,9 @@
  *	UART		0x7C000000						RCS2
  *	Mailbox		0xFF000000						RCS1
  *	Flash		0xFFC00000	0xFFFFFFFF	4MB	64b		RCS0
- * 
+ *
  * Flash sectors are laid out as follows.
- * 
+ *
  *	Sector	Start		End			Size	Comments
  *	------- ----------- ----------- ------- -----------
  *	 0		0xFFC00000	0xFFC3FFFF	256KB
@@ -193,7 +193,7 @@
 
 /*
  * SDRAM config - see memory map details above.
- * 
+ *
  * CFG_SDRAM_BASE			- Start address of SDRAM, this _must_ be zero!
  * CFG_SDRAM_SIZE			- Total size of contiguous SDRAM bank(s)
  */
@@ -202,9 +202,9 @@
 #define CFG_SDRAM_SIZE			0x04000000
 
 
-/* 
+/*
  * Flash config - see memory map details above.
- * 
+ *
  * CFG_FLASH_BASE			- Start address of flash memory
  * CFG_FLASH_SIZE			- Total size of contiguous flash mem
  * CFG_FLASH_ERASE_TOUT		- Erase timeout in ms
@@ -223,7 +223,7 @@
 
 /*
  * Monitor config - see memory map details above
- * 
+ *
  * CFG_MONITOR_BASE			- Base address of monitor code
  * CFG_MALLOC_LEN			- Size of malloc pool (128KB)
  */
@@ -234,7 +234,7 @@
 
 /*
  * Command shell settings
- * 
+ *
  * CFG_BARGSIZE			- Boot Argument buffer size
  * CFG_BOOTMAPSZ		- Size of app's mapped RAM at boot (Linux=8MB)
  * CFG_CBSIZE			- Console Buffer (input) size
@@ -261,10 +261,10 @@
 
 /*
  * Environment config - see memory map details above
- * 
+ *
  * CFG_ENV_IS_IN_FLASH		- The env variables are stored in flash
  * CFG_ENV_ADDR			- Address of the sector containing env vars
- * CFG_ENV_SIZE			- Ammount of RAM for env vars (used to save RAM, 4KB) 
+ * CFG_ENV_SIZE			- Ammount of RAM for env vars (used to save RAM, 4KB)
  * CFG_ENV_SECT_SIZE		- Size of sector containing env vars (32KB)
  */
 
@@ -282,7 +282,7 @@
  * Since the main system RAM is initialised very early, we place the INIT_RAM
  * in the main system RAM just above the exception vectors. The contents are
  * copied to top of RAM by the init code.
- * 
+ *
  * CFG_INIT_RAM_ADDR		- Address of Init RAM, above exception vect
  * CFG_INIT_RAM_END			- Size of Init RAM
  * CFG_GBL_DATA_SIZE		- Ammount of RAM to reserve for global data
@@ -297,7 +297,7 @@
 
 /*
  * Initial BAT config
- * 
+ *
  * BAT0	- System SDRAM
  * BAT1 - LED's and Serial Port
  * BAT2 - PCI Memory
@@ -327,7 +327,7 @@
 
 /*
  * Cache config
- * 
+ *
  * CFG_CACHELINE_SIZE		- Size of a cache line (CPU specific)
  * CFG_L2					- L2 cache enabled if defined
  * L2_INIT					- L2 cache init flags
@@ -342,7 +342,7 @@
 
 /*
  * Clocks config
- * 
+ *
  * CFG_BUS_HZ				- Bus clock frequency in Hz
  * CFG_BUS_CLK				- As above (?)
  * CFG_HZ					- Decrementer freq in Hz
@@ -355,7 +355,7 @@
 
 /*
  * Serial port config
- * 
+ *
  * CFG_BAUDRATE_TABLE		- List of valid baud rates
  * CFG_NS16550				- Include the NS16550 driver
  * CFG_NS16550_SERIAL		- Include the serial (wrapper) driver
@@ -398,7 +398,7 @@
 
 /*
  * Extra init functions
- * 
+ *
  * CFG_BOARD_ASM_INIT		- Call assembly init code
  */
 
@@ -407,11 +407,11 @@
 
 /*
  * Boot flags
- * 
+ *
  * BOOTFLAG_COLD			- Indicates a power-on boot
  * BOOTFLAG_WARM			- Indicates a software reset
  */
- 
+
 #define BOOTFLAG_COLD			0x01
 #define BOOTFLAG_WARM			0x02
 

include/ns16550.h

@@ -7,7 +7,7 @@
  * added prototypes for ns16550.c
  * reduced no of com ports to 2
  * modifications (c) Rob Taylor, Flying Pig Systems. 2000.
- * 
+ *
  * added support for port on 64-bit bus
  * by Richard Danter (richard.danter@windriver.com), (C) 2005 Wind River Systems
  */