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@@ -100,6 +100,10 @@ _TEXT_BASE:
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_bss_start_ofs:
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.word __bss_start - _start
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+.global _image_copy_end_ofs
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+_image_copy_end_ofs:
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+ .word __image_copy_end - _start
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+
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.globl _bss_end_ofs
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_bss_end_ofs:
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.word __bss_end__ - _start
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@@ -193,7 +197,7 @@ stack_setup:
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moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
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beq clear_bss /* skip relocation */
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mov r1, r6 /* r1 <- scratch for copy_loop */
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- ldr r3, _bss_start_ofs
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+ ldr r3, _image_copy_end_ofs
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add r2, r0, r3 /* r2 <- source end address */
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copy_loop:
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@@ -241,15 +245,28 @@ fixnext:
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add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
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cmp r2, r3
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blo fixloop
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+ b clear_bss
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+
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+_rel_dyn_start_ofs:
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+ .word __rel_dyn_start - _start
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+_rel_dyn_end_ofs:
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+ .word __rel_dyn_end - _start
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+_dynsym_start_ofs:
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+ .word __dynsym_start - _start
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#endif
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clear_bss:
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-#ifndef CONFIG_SPL_BUILD
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+#ifdef CONFIG_SPL_BUILD
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+ /* No relocation for SPL */
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+ ldr r0, =__bss_start
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+ ldr r1, =__bss_end__
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+#else
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ldr r0, _bss_start_ofs
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ldr r1, _bss_end_ofs
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mov r4, r6 /* reloc addr */
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add r0, r0, r4
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add r1, r1, r4
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+#endif
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mov r2, #0x00000000 /* clear */
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clbss_l:cmp r0, r1 /* clear loop... */
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@@ -258,7 +275,6 @@ clbss_l:cmp r0, r1 /* clear loop... */
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add r0, r0, #4
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b clbss_l
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clbss_e:
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-#endif /* #ifndef CONFIG_SPL_BUILD */
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/*
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* We are done. Do not return, instead branch to second part of board
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@@ -273,7 +289,7 @@ _nand_boot_ofs:
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#else
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jump_2_ram:
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ldr r0, _board_init_r_ofs
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- ldr r1, _TEXT_BASE
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+ adr r1, _start
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add lr, r0, r1
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add lr, lr, r9
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/* setup parameters for board_init_r */
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@@ -286,13 +302,6 @@ _board_init_r_ofs:
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.word board_init_r - _start
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#endif
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-_rel_dyn_start_ofs:
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- .word __rel_dyn_start - _start
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-_rel_dyn_end_ofs:
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- .word __rel_dyn_end - _start
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-_dynsym_start_ofs:
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- .word __dynsym_start - _start
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-
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/*
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*************************************************************************
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*
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