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@@ -1,352 +0,0 @@
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-/*
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- * (C) Copyright 2007-2008
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- * Stelian Pop <stelian.pop@leadtechdesign.com>
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- * Lead Tech Design <www.leadtechdesign.com>
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- *
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- * See file CREDITS for list of people who contributed to this
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- * project.
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- *
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- * This program is free software; you can redistribute it and/or
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- * modify it under the terms of the GNU General Public License as
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- * published by the Free Software Foundation; either version 2 of
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- * the License, or (at your option) any later version.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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- * GNU General Public License for more details.
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- *
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- * You should have received a copy of the GNU General Public License
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- * along with this program; if not, write to the Free Software
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- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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- * MA 02111-1307 USA
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- */
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-
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-#include <common.h>
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-#include <asm/arch/at91cap9.h>
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-#include <asm/arch/at91cap9_matrix.h>
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-#include <asm/arch/at91sam9_smc.h>
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-#include <asm/arch/at91_common.h>
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-#include <asm/arch/at91_pmc.h>
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-#include <asm/arch/at91_rstc.h>
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-#include <asm/arch/clk.h>
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-#include <asm/arch/gpio.h>
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-#include <asm/arch/io.h>
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-#include <asm/arch/hardware.h>
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-#include <lcd.h>
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-#include <atmel_lcdc.h>
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-#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
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-#include <net.h>
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-#endif
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-#include <netdev.h>
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-
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-#define MP_BLOCK_3_BASE 0xFDF00000
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-
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-DECLARE_GLOBAL_DATA_PTR;
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-
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-/* ------------------------------------------------------------------------- */
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-/*
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- * Miscelaneous platform dependent initialisations
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- */
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-
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-static void at91cap9_slowclock_hw_init(void)
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-{
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- /*
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- * On AT91CAP9 revC CPUs, the slow clock can be based on an
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- * internal impreciseRC oscillator or an external 32kHz oscillator.
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- * Switch to the latter.
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- */
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-#define ARCH_ID_AT91CAP9_REVB 0x399
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-#define ARCH_ID_AT91CAP9_REVC 0x601
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- if (at91_sys_read(AT91_PMC_VER) == ARCH_ID_AT91CAP9_REVC) {
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- unsigned i, tmp = at91_sys_read(AT91_SCKCR);
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- if ((tmp & AT91CAP9_SCKCR_OSCSEL) == AT91CAP9_SCKCR_OSCSEL_RC) {
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- timer_init();
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- tmp |= AT91CAP9_SCKCR_OSC32EN;
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- at91_sys_write(AT91_SCKCR, tmp);
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- for (i = 0; i < 1200; i++)
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- udelay(1000);
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- tmp |= AT91CAP9_SCKCR_OSCSEL_32;
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- at91_sys_write(AT91_SCKCR, tmp);
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- udelay(200);
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- tmp &= ~AT91CAP9_SCKCR_RCEN;
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- at91_sys_write(AT91_SCKCR, tmp);
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- }
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- }
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-}
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-
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-static void at91cap9_nor_hw_init(void)
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-{
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- unsigned long csa;
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-
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- /* Ensure EBI supply is 3.3V */
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- csa = at91_sys_read(AT91_MATRIX_EBICSA);
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- at91_sys_write(AT91_MATRIX_EBICSA,
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- csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
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- /* Configure SMC CS0 for parallel flash */
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- at91_sys_write(AT91_SMC_SETUP(0),
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- AT91_SMC_NWESETUP_(4) | AT91_SMC_NCS_WRSETUP_(2) |
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- AT91_SMC_NRDSETUP_(4) | AT91_SMC_NCS_RDSETUP_(2));
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- at91_sys_write(AT91_SMC_PULSE(0),
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- AT91_SMC_NWEPULSE_(8) | AT91_SMC_NCS_WRPULSE_(10) |
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- AT91_SMC_NRDPULSE_(8) | AT91_SMC_NCS_RDPULSE_(10));
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- at91_sys_write(AT91_SMC_CYCLE(0),
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- AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
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- at91_sys_write(AT91_SMC_MODE(0),
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- AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
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- AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE |
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- AT91_SMC_DBW_16 | AT91_SMC_TDF_(1));
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-}
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-
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-#ifdef CONFIG_CMD_NAND
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-static void at91cap9_nand_hw_init(void)
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-{
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- unsigned long csa;
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-
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- /* Enable CS3 */
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- csa = at91_sys_read(AT91_MATRIX_EBICSA);
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- at91_sys_write(AT91_MATRIX_EBICSA,
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- csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA |
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- AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
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-
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- /* Configure SMC CS3 for NAND/SmartMedia */
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- at91_sys_write(AT91_SMC_SETUP(3),
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- AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(1) |
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- AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(1));
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- at91_sys_write(AT91_SMC_PULSE(3),
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- AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(6) |
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- AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(6));
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- at91_sys_write(AT91_SMC_CYCLE(3),
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- AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(8));
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- at91_sys_write(AT91_SMC_MODE(3),
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- AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
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- AT91_SMC_EXNWMODE_DISABLE |
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-#ifdef CONFIG_SYS_NAND_DBW_16
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- AT91_SMC_DBW_16 |
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-#else /* CONFIG_SYS_NAND_DBW_8 */
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- AT91_SMC_DBW_8 |
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-#endif
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- AT91_SMC_TDF_(1));
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-
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- at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_PIOABCD);
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-
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- /* RDY/BSY is not connected */
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-
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- /* Enable NandFlash */
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- at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
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-}
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-#endif
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-
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-#ifdef CONFIG_MACB
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-static void at91cap9_macb_hw_init(void)
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-{
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- /* Enable clock */
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- at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_EMAC);
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-
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- /*
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- * Disable pull-up on:
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- * RXDV (PB22) => PHY normal mode (not Test mode)
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- * ERX0 (PB25) => PHY ADDR0
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- * ERX1 (PB26) => PHY ADDR1 => PHYADDR = 0x0
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- *
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- * PHY has internal pull-down
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- */
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- writel(pin_to_mask(AT91_PIN_PB22) |
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- pin_to_mask(AT91_PIN_PB25) |
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- pin_to_mask(AT91_PIN_PB26),
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- pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
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-
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- /* Need to reset PHY -> 500ms reset */
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- at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
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- (AT91_RSTC_ERSTL & (0x0D << 8)) |
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- AT91_RSTC_URSTEN);
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-
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- at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
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-
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- /* Wait for end hardware reset */
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- while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
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-
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- /* Restore NRST value */
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- at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
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- (AT91_RSTC_ERSTL & (0x0 << 8)) |
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- AT91_RSTC_URSTEN);
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-
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- /* Re-enable pull-up */
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- writel(pin_to_mask(AT91_PIN_PB22) |
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- pin_to_mask(AT91_PIN_PB25) |
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- pin_to_mask(AT91_PIN_PB26),
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- pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
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-
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- at91_macb_hw_init();
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-
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- /* Unlock EMAC, 3 0 2 1 sequence */
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-#define MP_MAC_KEY0 0x5969cb2a
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-#define MP_MAC_KEY1 0xb4a1872e
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-#define MP_MAC_KEY2 0x05683fbc
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-#define MP_MAC_KEY3 0x3634fba4
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-#define UNLOCK_MAC 0x00000008
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- writel(MP_MAC_KEY3, MP_BLOCK_3_BASE + 0x3c);
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- writel(MP_MAC_KEY0, MP_BLOCK_3_BASE + 0x30);
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- writel(MP_MAC_KEY2, MP_BLOCK_3_BASE + 0x38);
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- writel(MP_MAC_KEY1, MP_BLOCK_3_BASE + 0x34);
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- writel(UNLOCK_MAC, MP_BLOCK_3_BASE + 0x40);
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-}
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-#endif
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-
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-#ifdef CONFIG_USB_OHCI_NEW
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-static void at91cap9_uhp_hw_init(void)
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-{
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- /* Unlock USB OHCI, 3 2 0 1 sequence */
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-#define MP_OHCI_KEY0 0x896c11ca
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-#define MP_OHCI_KEY1 0x68ebca21
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-#define MP_OHCI_KEY2 0x4823efbc
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-#define MP_OHCI_KEY3 0x8651aae4
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-#define UNLOCK_OHCI 0x00000010
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- writel(MP_OHCI_KEY3, MP_BLOCK_3_BASE + 0x3c);
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- writel(MP_OHCI_KEY2, MP_BLOCK_3_BASE + 0x38);
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- writel(MP_OHCI_KEY0, MP_BLOCK_3_BASE + 0x30);
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- writel(MP_OHCI_KEY1, MP_BLOCK_3_BASE + 0x34);
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- writel(UNLOCK_OHCI, MP_BLOCK_3_BASE + 0x40);
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-}
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-#endif
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-
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-#ifdef CONFIG_LCD
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-vidinfo_t panel_info = {
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- vl_col: 240,
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- vl_row: 320,
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- vl_clk: 4965000,
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- vl_sync: ATMEL_LCDC_INVLINE_INVERTED |
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- ATMEL_LCDC_INVFRAME_INVERTED,
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- vl_bpix: 3,
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- vl_tft: 1,
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- vl_hsync_len: 5,
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- vl_left_margin: 1,
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- vl_right_margin:33,
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- vl_vsync_len: 1,
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- vl_upper_margin:1,
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- vl_lower_margin:0,
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- mmio: AT91CAP9_LCDC_BASE,
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-};
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-
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-void lcd_enable(void)
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-{
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- at91_set_gpio_value(AT91_PIN_PC0, 0); /* power up */
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-}
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-
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-void lcd_disable(void)
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-{
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- at91_set_gpio_value(AT91_PIN_PC0, 1); /* power down */
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-}
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-
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-static void at91cap9_lcd_hw_init(void)
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-{
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- at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
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- at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
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- at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */
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- at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */
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- at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */
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- at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */
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- at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */
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- at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */
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- at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */
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- at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */
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- at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */
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- at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */
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- at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */
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- at91_set_A_periph(AT91_PIN_PC17, 0); /* LCDD13 */
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- at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */
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- at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */
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- at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */
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- at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */
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- at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */
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- at91_set_A_periph(AT91_PIN_PC25, 0); /* LCDD21 */
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- at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */
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- at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */
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-
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- at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_LCDC);
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-
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- gd->fb_base = 0;
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-}
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-
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-#ifdef CONFIG_LCD_INFO
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-#include <nand.h>
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-#include <version.h>
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-
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-void lcd_show_board_info(void)
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-{
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- ulong dram_size, nand_size;
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- int i;
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- char temp[32];
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-
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- lcd_printf ("%s\n", U_BOOT_VERSION);
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- lcd_printf ("(C) 2008 ATMEL Corp\n");
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- lcd_printf ("at91support@atmel.com\n");
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- lcd_printf ("%s CPU at %s MHz\n",
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- CONFIG_SYS_AT91_CPU_NAME,
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- strmhz(temp, get_cpu_clk_rate()));
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-
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- dram_size = 0;
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- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
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- dram_size += gd->bd->bi_dram[i].size;
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- nand_size = 0;
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- for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
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- nand_size += nand_info[i].size;
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- lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
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- dram_size >> 20,
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- nand_size >> 20 );
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-}
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-#endif /* CONFIG_LCD_INFO */
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-#endif
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-
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-int board_init(void)
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-{
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- /* Enable Ctrlc */
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- console_init_f();
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-
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- /* arch number of AT91CAP9ADK-Board */
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- gd->bd->bi_arch_number = MACH_TYPE_AT91CAP9ADK;
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- /* adress of boot parameters */
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- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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-
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- at91_serial_hw_init();
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- at91cap9_slowclock_hw_init();
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- at91cap9_nor_hw_init();
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-#ifdef CONFIG_CMD_NAND
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- at91cap9_nand_hw_init();
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-#endif
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-#ifdef CONFIG_HAS_DATAFLASH
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- at91_spi0_hw_init(1 << 0);
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-#endif
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-#ifdef CONFIG_MACB
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- at91cap9_macb_hw_init();
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-#endif
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-#ifdef CONFIG_USB_OHCI_NEW
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- at91cap9_uhp_hw_init();
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-#endif
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-#ifdef CONFIG_LCD
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- at91cap9_lcd_hw_init();
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-#endif
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- return 0;
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-}
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-
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-int dram_init(void)
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-{
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- gd->bd->bi_dram[0].start = PHYS_SDRAM;
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- gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
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- return 0;
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-}
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-
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-#ifdef CONFIG_RESET_PHY_R
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-void reset_phy(void)
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-{
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-}
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-#endif
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-
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-int board_eth_init(bd_t *bis)
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-{
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- int rc = 0;
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-#ifdef CONFIG_MACB
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- rc = macb_eth_initialize(0, (void *)AT91CAP9_BASE_EMAC, 0x00);
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-#endif
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- return rc;
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-}
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Wolfgang Denk