Fix bug in [id]cache_status commands for MPC85xx processors;

should look at LSB of L1CSRn registers to determine if L1 cache is
enabled, not the MSB.
Patch by Murray Jensen, 19 Jul 2005

CHANGELOG

@@ -2,6 +2,11 @@
 Changes since U-Boot 1.1.4:
 ======================================================================
 
+* Fix bug in [id]cache_status commands for MPC85xx processors;
+  should look at LSB of L1CSRn registers to determine if L1 cache is
+  enabled, not the MSB.
+  Patch by Murray Jensen, 19 Jul 2005
+
 * Fix array overflow with fw_setenv on uninitialised environment
   Patch by Murray Jensen, 15 Jul 2005
 

cpu/mpc85xx/start.S

@@ -715,7 +715,7 @@ icache_disable:
 	.globl	icache_status
 icache_status:
 	mfspr	r3,L1CSR1
-	srwi	r3, r3, 31	/* >>31 => select bit 0 */
+	andi.	r3,r3,1
 	blr
 
 	.globl	dcache_enable
@@ -748,7 +748,7 @@ dcache_disable:
 	.globl	dcache_status
 dcache_status:
 	mfspr	r3,L1CSR0
-	srwi	r3, r3, 31	/* >>31 => select bit 0 */
+	andi.	r3,r3,1
 	blr
 
 	.globl get_pir