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@@ -653,6 +653,9 @@ The following options need to be configured:
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CONFIG_RTC_DS1338 - use Maxim, Inc. DS1338 RTC
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CONFIG_RTC_DS164x - use Dallas DS164x RTC
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+ Note that if the RTC uses I2C, then the I2C interface
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+ must also be configured. See I2C Support, below.
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+
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- Timestamp Support:
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When CONFIG_TIMESTAMP is selected, the timestamp
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@@ -904,29 +907,48 @@ The following options need to be configured:
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- I2C Support: CONFIG_HARD_I2C | CONFIG_SOFT_I2C
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- Enables I2C serial bus commands. If this is selected,
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- either CONFIG_HARD_I2C or CONFIG_SOFT_I2C must be defined
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- to include the appropriate I2C driver.
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+ These enable I2C serial bus commands. Defining either of
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+ (but not both of) CONFIG_HARD_I2C or CONFIG_SOFT_I2C will
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+ include the appropriate I2C driver for the selected cpu.
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- See also: common/cmd_i2c.c for a description of the
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+ This will allow you to use i2c commands at the u-boot
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+ command line (as long as you set CFG_CMD_I2C in
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+ CONFIG_COMMANDS) and communicate with i2c based realtime
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+ clock chips. See common/cmd_i2c.c for a description of the
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command line interface.
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+ CONFIG_HARD_I2C selects the CPM hardware driver for I2C.
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+
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+ CONFIG_SOFT_I2C configures u-boot to use a software (aka
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+ bit-banging) driver instead of CPM or similar hardware
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+ support for I2C.
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- CONFIG_HARD_I2C
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+ There are several other quantities that must also be
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+ defined when you define CONFIG_HARD_I2C or CONFIG_SOFT_I2C.
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- Selects the CPM hardware driver for I2C.
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+ In both cases you will need to define CFG_I2C_SPEED
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+ to be the frequency (in Hz) at which you wish your i2c bus
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+ to run and CFG_I2C_SLAVE to be the address of this node (ie
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+ the cpu's i2c node address).
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+
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+ Now, the u-boot i2c code for the mpc8xx (cpu/mpc8xx/i2c.c)
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+ sets the cpu up as a master node and so its address should
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+ therefore be cleared to 0 (See, eg, MPC823e User's Manual
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+ p.16-473). So, set CFG_I2C_SLAVE to 0.
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- CONFIG_SOFT_I2C
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+ That's all that's required for CONFIG_HARD_I2C.
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- Use software (aka bit-banging) driver instead of CPM
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- or similar hardware support for I2C. This is configured
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- via the following defines.
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+ If you use the software i2c interface (CONFIG_SOFT_I2C)
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+ then the following macros need to be defined (examples are
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+ from include/configs/lwmon.h):
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I2C_INIT
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- (Optional). Any commands necessary to enable I2C
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+ (Optional). Any commands necessary to enable the I2C
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controller or configure ports.
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+ eg: #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
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+
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I2C_PORT
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(Only for MPC8260 CPU). The I/O port to use (the code
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@@ -939,32 +961,49 @@ The following options need to be configured:
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(driven). If the data line is open collector, this
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define can be null.
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+ eg: #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
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+
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I2C_TRISTATE
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The code necessary to make the I2C data line tri-stated
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(inactive). If the data line is open collector, this
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define can be null.
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+ eg: #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
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+
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I2C_READ
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Code that returns TRUE if the I2C data line is high,
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FALSE if it is low.
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+ eg: #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
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+
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I2C_SDA(bit)
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If <bit> is TRUE, sets the I2C data line high. If it
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is FALSE, it clears it (low).
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+ eg: #define I2C_SDA(bit) \
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+ if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
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+ else immr->im_cpm.cp_pbdat &= ~PB_SDA
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+
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I2C_SCL(bit)
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If <bit> is TRUE, sets the I2C clock line high. If it
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is FALSE, it clears it (low).
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+ eg: #define I2C_SCL(bit) \
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+ if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
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+ else immr->im_cpm.cp_pbdat &= ~PB_SCL
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+
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I2C_DELAY
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This delay is invoked four times per clock cycle so this
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controls the rate of data transfer. The data rate thus
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- is 1 / (I2C_DELAY * 4).
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+ is 1 / (I2C_DELAY * 4). Often defined to be something
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+ like:
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+
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+ #define I2C_DELAY udelay(2)
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CFG_I2C_INIT_BOARD
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