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@@ -298,4 +298,13 @@
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#define LCRR_CLKDIV_4 0x00000004
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#define LCRR_CLKDIV_8 0x00000008
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+/* LTEDR - Transfer Error Check Disable Register
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+ */
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+#define LTEDR_BMD 0x80000000 /* Bus monitor disable */
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+#define LTEDR_PARD 0x20000000 /* Parity error checking disabled */
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+#define LTEDR_WPD 0x04000000 /* Write protect error checking diable */
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+#define LTEDR_WARA 0x00800000 /* Write-after-read-atomic error checking diable */
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+#define LTEDR_RAWA 0x00400000 /* Read-after-write-atomic error checking disable */
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+#define LTEDR_CSD 0x00080000 /* Chip select error checking disable */
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+
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#endif /* __ASM_PPC_FSL_LBC_H */
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