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@@ -68,6 +68,24 @@ static void sdram_start (int hi_addr)
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{
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long hi_addr_bit = hi_addr ? 0x01000000 : 0;
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+#ifdef CONFIG_MPC5200_DDR
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+ /* unlock mode register */
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+ *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xf05f0f00 | hi_addr_bit;
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+ /* precharge all banks */
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+ *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xf05f0f02 | hi_addr_bit;
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+ /* set mode register: extended mode */
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+ *(vu_long *)MPC5XXX_SDRAM_MODE = 0x40090000;
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+ /* set mode register: reset DLL */
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+ *(vu_long *)MPC5XXX_SDRAM_MODE = 0x058d0000;
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+ /* precharge all banks */
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+ *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xf05f0f02 | hi_addr_bit;
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+ /* auto refresh */
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+ *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xf05f0f04 | hi_addr_bit;
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+ /* set mode register */
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+ *(vu_long *)MPC5XXX_SDRAM_MODE = 0x018d0000;
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+ /* normal operation */
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+ *(vu_long *)MPC5XXX_SDRAM_CTRL = 0x705f0f00 | hi_addr_bit;
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+#else
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/* unlock mode register */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0000 | hi_addr_bit;
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/* precharge all banks */
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@@ -86,12 +104,16 @@ static void sdram_start (int hi_addr)
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*(vu_long *)MPC5XXX_SDRAM_MODE = 0x008d0000;
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/* normal operation */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = 0x504f0000 | hi_addr_bit;
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+#endif
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}
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#endif
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long int initdram (int board_type)
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{
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ulong dramsize = 0;
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+#ifdef CONFIG_MPC5200_DDR
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+ ulong dramsize2 = 0;
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+#endif
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#ifndef CFG_RAMBOOT
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ulong test1, test2;
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@@ -100,9 +122,18 @@ long int initdram (int board_type)
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*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
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*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
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+#ifdef CONFIG_MPC5200_DDR
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+ /* setup config registers */
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+ *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0x73722930;
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+ *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x47770000;
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+
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+ /* set tap delay to 0x10 */
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+ *(vu_long *)MPC5XXX_CDM_PORCFG = 0x10000000;
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+#else
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/* setup config registers */
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*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0xc2233a00;
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*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x88b70004;
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+#endif
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#elif defined(CONFIG_MGT5100)
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*(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
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@@ -129,7 +160,23 @@ long int initdram (int board_type)
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#if defined(CONFIG_MPC5200)
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*(vu_long *)MPC5XXX_SDRAM_CS0CFG =
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(0x13 + __builtin_ffs(dramsize >> 20) - 1);
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+#ifdef CONFIG_MPC5200_DDR
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+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
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+ sdram_start(0);
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+ test1 = dram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
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+ sdram_start(1);
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+ test2 = dram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
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+ if (test1 > test2) {
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+ sdram_start(0);
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+ dramsize2 = test1;
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+ } else {
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+ dramsize2 = test2;
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+ }
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+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG =
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+ dramsize + (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
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+#else
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*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
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+#endif
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#elif defined(CONFIG_MGT5100)
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*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
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#endif
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@@ -140,8 +187,15 @@ long int initdram (int board_type)
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dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
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#else
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dramsize = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS0CFG - 0x13)) << 20);
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+#ifdef CONFIG_MPC5200_DDR
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+ dramsize2 = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS1CFG - 0x13)) << 20);
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+#endif
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#endif
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#endif /* CFG_RAMBOOT */
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+
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+#ifdef CONFIG_MPC5200_DDR
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+ dramsize += dramsize2;
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+#endif
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/* return total ram size */
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return dramsize;
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}
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