nand_spl: change out_be32 to raw_writel and depend on subsequent sync

This change reduces the SPL size by removing the redundant syncs produced
by out_be32 and just replies on one final sync

Done with:

sed -r '/in_be32/b; s/(out_be32)\(([^,]*),\s+(.*)\)/__raw_writel(\3, \2)/g' -i `git grep --name-only sdram_init nand_spl/`

Signed-off-by: Matthew McClintock <msm@freescale.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

nand_spl/board/freescale/p1010rdb/nand_boot.c

@@ -39,39 +39,37 @@ void sdram_init(void)
 	/* mask off E bit */
 	u32 svr = SVR_SOC_VER(mfspr(SPRN_SVR));
 
-	out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE);
-	out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
-	out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
-	out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL_2);
-	out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
+	__raw_writel(CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE, &ddr->sdram_cfg);
+	__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
+	__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
+	__raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
+	__raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
 
 	if (ddr_freq_mhz < 700) {
-		out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3_667);
-		out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0_667);
-		out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_667);
-		out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_667);
-		out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_667);
-		out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_667);
-		out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_667);
-		out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL_667);
-		out_be32(&ddr->ddr_wrlvl_cntl,
-				CONFIG_SYS_DDR_WRLVL_CONTROL_667);
+		__raw_writel(CONFIG_SYS_DDR_TIMING_3_667, &ddr->timing_cfg_3);
+		__raw_writel(CONFIG_SYS_DDR_TIMING_0_667, &ddr->timing_cfg_0);
+		__raw_writel(CONFIG_SYS_DDR_TIMING_1_667, &ddr->timing_cfg_1);
+		__raw_writel(CONFIG_SYS_DDR_TIMING_2_667, &ddr->timing_cfg_2);
+		__raw_writel(CONFIG_SYS_DDR_MODE_1_667, &ddr->sdram_mode);
+		__raw_writel(CONFIG_SYS_DDR_MODE_2_667, &ddr->sdram_mode_2);
+		__raw_writel(CONFIG_SYS_DDR_INTERVAL_667, &ddr->sdram_interval);
+		__raw_writel(CONFIG_SYS_DDR_CLK_CTRL_667, &ddr->sdram_clk_cntl);
+		__raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_667, &ddr->ddr_wrlvl_cntl);
 	} else {
-		out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3_800);
-		out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0_800);
-		out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_800);
-		out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_800);
-		out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_800);
-		out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_800);
-		out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_800);
-		out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL_800);
-		out_be32(&ddr->ddr_wrlvl_cntl,
-				CONFIG_SYS_DDR_WRLVL_CONTROL_800);
+		__raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3);
+		__raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0);
+		__raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1);
+		__raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2);
+		__raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode);
+		__raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2);
+		__raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval);
+		__raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl);
+		__raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl);
 	}
 
-	out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
-	out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
-	out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CONTROL);
+	__raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
+	__raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
+	__raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
 
 	/* P1014 and it's derivatives support max 16bit DDR width */
 	if (svr == SVR_P1014) {

nand_spl/board/freescale/p1023rds/nand_boot.c

@@ -37,28 +37,28 @@ void sdram_init(void)
 
 	set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1);
 
-	out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
-	out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
-	out_be32(&ddr->cs1_bnds, CONFIG_SYS_DDR_CS1_BNDS);
-	out_be32(&ddr->cs1_config, CONFIG_SYS_DDR_CS1_CONFIG);
-	out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
-	out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
-	out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
-	out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
-	out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL2);
-	out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1);
-	out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2);
-	out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL);
-	out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
-	out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL);
-	out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
-	out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
-	out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL);
-	out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL);
-	out_be32(&ddr->ddr_cdr1, CONFIG_SYS_DDR_CDR_1);
-	out_be32(&ddr->ddr_cdr2, CONFIG_SYS_DDR_CDR_2);
+	__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
+	__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
+	__raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
+	__raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
+	__raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3);
+	__raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0);
+	__raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1);
+	__raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2);
+	__raw_writel(CONFIG_SYS_DDR_CONTROL2, &ddr->sdram_cfg_2);
+	__raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode);
+	__raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2);
+	__raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval);
+	__raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
+	__raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl);
+	__raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
+	__raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
+	__raw_writel(CONFIG_SYS_DDR_ZQ_CNTL, &ddr->ddr_zq_cntl);
+	__raw_writel(CONFIG_SYS_DDR_WRLVL_CNTL, &ddr->ddr_wrlvl_cntl);
+	__raw_writel(CONFIG_SYS_DDR_CDR_1, &ddr->ddr_cdr1);
+	__raw_writel(CONFIG_SYS_DDR_CDR_2, &ddr->ddr_cdr2);
 	/* Set, but do not enable the memory */
-	out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN);
+	__raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg);
 
 	asm volatile("sync;isync");
 	udelay(500);

nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c

@@ -36,32 +36,32 @@ void sdram_init(void)
 {
 	ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
 
-	out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
-	out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
+	__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
+	__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
 #if CONFIG_CHIP_SELECTS_PER_CTRL > 1
-	out_be32(&ddr->cs1_bnds, CONFIG_SYS_DDR_CS1_BNDS);
-	out_be32(&ddr->cs1_config, CONFIG_SYS_DDR_CS1_CONFIG);
+	__raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
+	__raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
 #endif
-	out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
-	out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
-	out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
-	out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+	__raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3);
+	__raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0);
+	__raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1);
+	__raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2);
 
-	out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL_2);
-	out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1);
-	out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2);
+	__raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
+	__raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode);
+	__raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2);
 
-	out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL);
-	out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
-	out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL);
+	__raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval);
+	__raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
+	__raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl);
 
-	out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
-	out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
-	out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CONTROL);
-	out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CONTROL);
+	__raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
+	__raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
+	__raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
+	__raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL, &ddr->ddr_wrlvl_cntl);
 
 	/* Set, but do not enable the memory */
-	out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN);
+	__raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg);
 
 	asm volatile("sync;isync");
 	udelay(500);
@@ -92,13 +92,13 @@ void board_init_f(ulong bootflag)
 
 #ifndef CONFIG_QE
 	/* init DDR3 reset signal */
-	out_be32(&pgpio->gpdir, 0x02000000);
-	out_be32(&pgpio->gpodr, 0x00200000);
-	out_be32(&pgpio->gpdat, 0x00000000);
+	__raw_writel(0x02000000, &pgpio->gpdir);
+	__raw_writel(0x00200000, &pgpio->gpodr);
+	__raw_writel(0x00000000, &pgpio->gpdat);
 	udelay(1000);
-	out_be32(&pgpio->gpdat, 0x00200000);
+	__raw_writel(0x00200000, &pgpio->gpdat);
 	udelay(1000);
-	out_be32(&pgpio->gpdir, 0x00000000);
+	__raw_writel(0x00000000, &pgpio->gpdir);
 #endif
 
 	/* Initialize the DDR3 */