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@@ -404,6 +404,47 @@
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#define CONTROL_PADCONF_SDRC_CKE0 0x0262
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#define CONTROL_PADCONF_SDRC_CKE0 0x0262
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#define CONTROL_PADCONF_SDRC_CKE1 0x0264
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#define CONTROL_PADCONF_SDRC_CKE1 0x0264
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+/* AM3517 specific mux configuration */
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+#define CONTROL_PADCONF_SYS_NRESWARM 0x0A08
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+/* CCDC */
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+#define CONTROL_PADCONF_CCDC_PCLK 0x01E4
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+#define CONTROL_PADCONF_CCDC_FIELD 0x01E6
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+#define CONTROL_PADCONF_CCDC_HD 0x01E8
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+#define CONTROL_PADCONF_CCDC_VD 0x01EA
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+#define CONTROL_PADCONF_CCDC_WEN 0x01EC
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+#define CONTROL_PADCONF_CCDC_DATA0 0x01EE
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+#define CONTROL_PADCONF_CCDC_DATA1 0x01F0
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+#define CONTROL_PADCONF_CCDC_DATA2 0x01F2
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+#define CONTROL_PADCONF_CCDC_DATA3 0x01F4
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+#define CONTROL_PADCONF_CCDC_DATA4 0x01F6
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+#define CONTROL_PADCONF_CCDC_DATA5 0x01F8
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+#define CONTROL_PADCONF_CCDC_DATA6 0x01FA
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+#define CONTROL_PADCONF_CCDC_DATA7 0x01FC
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+/* RMII */
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+#define CONTROL_PADCONF_RMII_MDIO_DATA 0x01FE
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+#define CONTROL_PADCONF_RMII_MDIO_CLK 0x0200
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+#define CONTROL_PADCONF_RMII_RXD0 0x0202
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+#define CONTROL_PADCONF_RMII_RXD1 0x0204
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+#define CONTROL_PADCONF_RMII_CRS_DV 0x0206
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+#define CONTROL_PADCONF_RMII_RXER 0x0208
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+#define CONTROL_PADCONF_RMII_TXD0 0x020A
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+#define CONTROL_PADCONF_RMII_TXD1 0x020C
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+#define CONTROL_PADCONF_RMII_TXEN 0x020E
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+#define CONTROL_PADCONF_RMII_50MHZ_CLK 0x0210
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+#define CONTROL_PADCONF_USB0_DRVBUS 0x0212
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+/* CAN */
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+#define CONTROL_PADCONF_HECC1_TXD 0x0214
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+#define CONTROL_PADCONF_HECC1_RXD 0x0216
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+
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+#define CONTROL_PADCONF_SYS_BOOT7 0x0218
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+#define CONTROL_PADCONF_SDRC_DQS0N 0x021A
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+#define CONTROL_PADCONF_SDRC_DQS1N 0x021C
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+#define CONTROL_PADCONF_SDRC_DQS2N 0x021E
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+#define CONTROL_PADCONF_SDRC_DQS3N 0x0220
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+#define CONTROL_PADCONF_STRBEN_DLY0 0x0222
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+#define CONTROL_PADCONF_STRBEN_DLY1 0x0224
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+#define CONTROL_PADCONF_SYS_BOOT8 0x0226
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+
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#define MUX_VAL(OFFSET,VALUE)\
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#define MUX_VAL(OFFSET,VALUE)\
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writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
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writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
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