Home Explore Help
Register Sign In
phyus
/
uboot-vybrid_public
8
0
Fork 0
Files Issues 0 Pull Requests 0 Wiki
Browse Source

board/T4240qds:Fix TLB and LAW size of NAND flash

The internal SRAM of Freescale's IFC NAND machine is of 64K and controller's
Address Mask Registers is initialised with the same.

So Update TLB and LAW size of NAND flash accordingly.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Prabhakar Kushwaha 12 years ago
parent
2d9f26b693
commit
ac13eb5de0
2 changed files with 2 additions and 2 deletions
Split View Show Diff Stats
  1. 1 1
      board/freescale/t4qds/law.c
  2. 1 1
      board/freescale/t4qds/tlb.c

+ 1 - 1
board/freescale/t4qds/law.c
View File 

@@ -40,7 +40,7 @@ struct law_entry law_table[] = {
 
 	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
 
 #endif
 
 #ifdef CONFIG_SYS_NAND_BASE_PHYS
 
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
 
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
 
 #endif
 
 };

+ 1 - 1
board/freescale/t4qds/tlb.c
View File 

@@ -125,7 +125,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
 	 */
 
 	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
 
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 
-			0, 16, BOOKE_PAGESZ_1M, 1),
 
+			0, 16, BOOKE_PAGESZ_64K, 1),
 
 #endif
 
 	SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
 
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,