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@@ -2,7 +2,7 @@
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* (C) Copyright 2001-2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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- * (C) Copyright 2003 Arabella Software Ltd.
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+ * (C) Copyright 2003-2005 Arabella Software Ltd.
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* Yuli Barcohen <yuli@arabellasw.com>
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*
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* See file CREDITS for list of people who contributed to this
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@@ -27,9 +27,6 @@
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#include <common.h>
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#include <ioports.h>
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#include <mpc8260.h>
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-#include <asm/m8260_pci.h>
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-#include <i2c.h>
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-#include <spd.h>
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#include <miiphy.h>
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/*
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@@ -167,8 +164,8 @@ const iop_conf_t iop_conf_tab[4][32] = {
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/* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
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/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
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/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
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- /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
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- /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
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+ /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
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+ /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */
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/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
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/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
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/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
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@@ -231,11 +228,10 @@ long int initdram(int board_type)
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vu_char *ramaddr;
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uchar c = 0xFF;
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long int msize = CFG_SDRAM_SIZE;
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- uint psdmr = CFG_PSDMR;
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int i;
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if (bcsr[4] & BCSR_PCI_MODE) { /* PCI mode selected by JP9 */
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- immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN;
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+ immap->im_clkrst.car_sccr |= SCCR_PCI_MODE;
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immap->im_siu_conf.sc_siumcr =
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(immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
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| SIUMCR_LBPC01;
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@@ -255,10 +251,10 @@ long int initdram(int board_type)
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*/
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if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) {
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memctl->memc_lsrt = CFG_LSRT;
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- memctl->memc_or4 = 0xFFC01480;
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- memctl->memc_br4 = CFG_LSDRAM_BASE | 0x00001861;
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- memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_PREA;
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+ memctl->memc_or4 = CFG_LSDRAM_OR;
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+ memctl->memc_br4 = CFG_LSDRAM_BR;
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ramaddr = (vu_char *)CFG_LSDRAM_BASE;
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+ memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_PREA;
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*ramaddr = c;
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memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_CBRR;
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for (i = 0; i < 8; i++)
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@@ -271,8 +267,8 @@ long int initdram(int board_type)
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/* Initialise 60x bus SDRAM */
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memctl->memc_psrt = CFG_PSRT;
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- memctl->memc_or2 = 0xFC0028C0;
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- memctl->memc_br2 = CFG_SDRAM_BASE | 0x00000041;
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+ memctl->memc_or2 = CFG_PSDRAM_OR;
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+ memctl->memc_br2 = CFG_PSDRAM_BR;
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/*
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* The mode data for Mode Register Write command must appear on
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* the address lines during a mode-set cycle. It is driven by
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@@ -283,15 +279,15 @@ long int initdram(int board_type)
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* length must be 4.
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*/
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ramaddr = (vu_char *)(CFG_SDRAM_BASE |
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- ((psdmr & PSDMR_CL_MSK) << 7) | 0x10);
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- memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */
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+ ((CFG_PSDMR & PSDMR_CL_MSK) << 7) | 0x10);
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+ memctl->memc_psdmr = CFG_PSDMR | PSDMR_OP_PREA; /* Precharge all banks */
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*ramaddr = c;
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- memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
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+ memctl->memc_psdmr = CFG_PSDMR | PSDMR_OP_CBRR; /* CBR refresh */
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for (i = 0; i < 8; i++)
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*ramaddr = c;
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- memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; /* Mode Register write */
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+ memctl->memc_psdmr = CFG_PSDMR | PSDMR_OP_MRW; /* Mode Register write */
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*ramaddr = c;
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- memctl->memc_psdmr = psdmr | PSDMR_RFEN; /* Refresh enable */
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+ memctl->memc_psdmr = CFG_PSDMR | PSDMR_RFEN; /* Refresh enable */
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*ramaddr = c;
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#endif /* CFG_RAMBOOT */
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Wolfgang Denk