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@@ -75,9 +75,11 @@ phys_size_t initdram(int board_type)
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sdram->dacr0 =
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SDRAMC_DARCn_BA(CFG_SDRAM_BASE) | SDRAMC_DARCn_CASL_C1 |
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SDRAMC_DARCn_CBM_CMD20 | SDRAMC_DARCn_PS_32;
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+ asm("nop");
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/* Initialize DMR0 */
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sdram->dmr0 = ((dramsize - 1) & 0xFFFC0000) | SDRAMC_DMRn_V;
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+ asm("nop");
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/* Set IP (bit 3) in DACR */
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sdram->dacr0 |= SDRAMC_DARCn_IP;
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@@ -100,6 +102,7 @@ phys_size_t initdram(int board_type)
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/* Finish the configuration by issuing the MRS. */
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sdram->dacr0 |= SDRAMC_DARCn_IMRS;
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+ asm("nop");
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/* Write to the SDRAM Mode Register */
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*(u32 *) (CFG_SDRAM_BASE + 0x400) = 0xA5A59696;
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