* Add dual ethernet support on PM826

* Add support for LXT971 PHY on PM826

* Patch by Tord Andersson, 16 Jan 2003:
  Fix flash sector count for TQM8xxL

* Fix I2C EEPROM problem on ICU862 board (would only write the first
  16 bytes out of each 32 byte block)

CHANGELOG

@@ -1,5 +1,19 @@
 ======================================================================
-Changes since U-Boot 0.2.0:
+Changes since U-Boot 0.2.1:
+======================================================================
+
+* Add dual ethernet support on PM826
+
+* Add support for LXT971 PHY on PM826
+
+* Patch by Tord Andersson, 16 Jan 2003:
+  Fix flash sector count for TQM8xxL
+
+* Fix I2C EEPROM problem on ICU862 board (would only write the first
+  16 bytes out of each 32 byte block)
+
+======================================================================
+Changes for U-Boot 0.2.1:
 ======================================================================
 
 * Add support for V37 board

board/pm826/pm826.c

@@ -72,20 +72,27 @@ const iop_conf_t iop_conf_tab[4][32] = {
 
     /* Port B configuration */
     {   /*	      conf ppar psor pdir podr pdat */
-	/* PB31 */ {   0,   1,   0,   1,   0,   0   }, /* PB31 */
-	/* PB30 */ {   0,   1,   0,   0,   0,   0   }, /* PB30 */
-	/* PB29 */ {   0,   1,   1,   1,   0,   0   }, /* PB29 */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 TX_ER */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RX_DV  */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 TX_EN  */
+#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
+#ifdef CONFIG_ETHER_ON_FCC2
+#error "SCC1 conflicts with FCC2"
+#endif
 	/* PB28 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 TXD */
-	/* PB27 */ {   0,   1,   0,   0,   0,   0   }, /* PB27 */
-	/* PB26 */ {   0,   1,   0,   0,   0,   0   }, /* PB26 */
-	/* PB25 */ {   0,   1,   0,   1,   0,   0   }, /* PB25 */
-	/* PB24 */ {   0,   1,   0,   1,   0,   0   }, /* PB24 */
-	/* PB23 */ {   0,   1,   0,   1,   0,   0   }, /* PB23 */
-	/* PB22 */ {   0,   1,   0,   1,   0,   0   }, /* PB22 */
-	/* PB21 */ {   0,   1,   0,   0,   0,   0   }, /* PB21 */
-	/* PB20 */ {   0,   1,   0,   0,   0,   0   }, /* PB20 */
-	/* PB19 */ {   0,   1,   0,   0,   0,   0   }, /* PB19 */
-	/* PB18 */ {   0,   1,   0,   0,   0,   0   }, /* PB18 */
+#else
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RX_ER */
+#endif
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 COL */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 CRS */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RxD[3] */
 	/* PB17 */ {   0,   0,   0,   0,   0,   0   }, /* PB17 */
 	/* PB16 */ {   0,   0,   0,   0,   0,   0   }, /* PB16 */
 	/* PB15 */ {   1,   1,   0,   0,   0,   0   }, /* SCC2 RXD */
@@ -119,9 +126,9 @@ const iop_conf_t iop_conf_tab[4][32] = {
 	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* PC23 */
 	/* PC22 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 TXCK */
 	/* PC21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 RXCK */
-	/* PC20 */ {   0,   1,   0,   0,   0,   0   }, /* PC20 */
-	/* PC19 */ {   0,   1,   0,   0,   0,   0   }, /* PC19 */
-	/* PC18 */ {   0,   1,   0,   0,   0,   0   }, /* PC18 */
+	/* PC20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 TXCK(2) */
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RXCK */
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 TXCK */
 	/* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
 	/* PC16 */ {   0,   0,   0,   1,   0,   0   }, /* PC16 */
 	/* PC15 */ {   1,   1,   0,   1,   0,   0   }, /* SMC2 TXD */

common/cmd_eeprom.c

@@ -288,7 +288,7 @@ int eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cn
 			 */
 			contr_reg[0] = 0;
 			for (i = 0; i < MAX_ACKNOWLEDGE_POLLS; i++) {
-				if (i2c_read (addr_void[0], addr_void[1], 1, contr_reg, 1) == 1)
+				if (i2c_read (addr_void[0], addr_void[1], 1, contr_reg, 1) == 0)
 					break;	/* got ack */
 #if defined(CFG_EEPROM_PAGE_WRITE_DELAY_MS)
 				udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);

cpu/mpc8260/ether_fcc.c

@@ -40,40 +40,61 @@
  */
 
 #include <common.h>
+#include <malloc.h>
 #include <asm/cpm_8260.h>
 #include <mpc8260.h>
-#include <net.h>
 #include <command.h>
 #include <config.h>
+#include <net.h>
 
-#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_COMMANDS & CFG_CMD_NET)
-
-/*---------------------------------------------------------------------*/
-#if (CONFIG_ETHER_INDEX == 1)
-
-#define PROFF_ENET		PROFF_FCC1
-#define CPM_CR_ENET_SBLOCK	CPM_CR_FCC1_SBLOCK
-#define CPM_CR_ENET_SBLOCK	CPM_CR_FCC1_SBLOCK
-#define CPM_CR_ENET_PAGE	CPM_CR_FCC1_PAGE
-
-/*---------------------------------------------------------------------*/
-#elif (CONFIG_ETHER_INDEX == 2)
-
-#define PROFF_ENET		PROFF_FCC2
-#define CPM_CR_ENET_SBLOCK	CPM_CR_FCC2_SBLOCK
-#define CPM_CR_ENET_PAGE	CPM_CR_FCC2_PAGE
+#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_COMMANDS & CFG_CMD_NET) && \
+	defined(CONFIG_NET_MULTI)
 
-/*---------------------------------------------------------------------*/
-#elif (CONFIG_ETHER_INDEX == 3)
+static struct ether_fcc_info_s
+{
+	int ether_index;
+	int proff_enet;
+	ulong cpm_cr_enet_sblock;
+	ulong cpm_cr_enet_page;
+	ulong cmxfcr_mask;
+	ulong cmxfcr_value;
+}
+	ether_fcc_info[] =
+{
+#ifdef CONFIG_ETHER_ON_FCC1
+{
+	0,
+	PROFF_FCC1,
+	CPM_CR_FCC1_SBLOCK,
+	CPM_CR_FCC1_PAGE,
+	CFG_CMXFCR_MASK1,
+	CFG_CMXFCR_VALUE1
+},
+#endif
 
-#define PROFF_ENET		PROFF_FCC3
-#define CPM_CR_ENET_SBLOCK	CPM_CR_FCC3_SBLOCK
-#define CPM_CR_ENET_PAGE	CPM_CR_FCC3_PAGE
+#ifdef CONFIG_ETHER_ON_FCC2
+{
+	1,
+	PROFF_FCC2,
+	CPM_CR_FCC2_SBLOCK,
+	CPM_CR_FCC2_PAGE,
+	CFG_CMXFCR_MASK2,
+	CFG_CMXFCR_VALUE2
+},
+#endif
 
-/*---------------------------------------------------------------------*/
-#else
-#error "FCC Ethernet not correctly defined"
+#ifdef CONFIG_ETHER_ON_FCC3
+{
+	2,
+	PROFF_FCC3,
+	CPM_CR_FCC3_SBLOCK,
+	CPM_CR_FCC3_PAGE,
+	CFG_CMXFCR_MASK3,
+	CFG_CMXFCR_VALUE3
+},
 #endif
+};
+
 /*---------------------------------------------------------------------*/
 
 /* Maximum input DMA size.  Must be a should(?) be a multiple of 4. */
@@ -116,7 +137,7 @@ static RTXBD rtx __attribute__ ((aligned(8)));
 #error "rtx must be 64-bit aligned"
 #endif
 
-int eth_send(volatile void *packet, int length)
+static int fec_send(struct eth_device* dev, volatile void *packet, int length)
 {
     int i;
     int result = 0;
@@ -156,7 +177,7 @@ out:
     return result;
 }
 
-int eth_rx(void)
+static int fec_recv(struct eth_device* dev)
 {
     int length;
 
@@ -194,8 +215,9 @@ int eth_rx(void)
 }
 
 
-int eth_init(bd_t *bis)
+static int fec_init(struct eth_device* dev, bd_t *bis)
 {
+    struct ether_fcc_info_s * info = dev->priv;
     int i;
     volatile immap_t *immr = (immap_t *)CFG_IMMR;
     volatile cpm8260_t *cp = &(immr->im_cpm);
@@ -210,18 +232,18 @@ int eth_init(bd_t *bis)
 
     /* 28.9 - (3): connect FCC's tx and rx clocks */
     immr->im_cpmux.cmx_uar = 0;
-    immr->im_cpmux.cmx_fcr = (immr->im_cpmux.cmx_fcr & ~CFG_CMXFCR_MASK) |
-    							CFG_CMXFCR_VALUE;
+    immr->im_cpmux.cmx_fcr = (immr->im_cpmux.cmx_fcr & ~info->cmxfcr_mask) |
+    							info->cmxfcr_value;
 
     /* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, Mode Ethernet */
-    immr->im_fcc[CONFIG_ETHER_INDEX-1].fcc_gfmr =
+    immr->im_fcc[info->ether_index].fcc_gfmr =
       FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
 
     /* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet */
-    immr->im_fcc[CONFIG_ETHER_INDEX-1].fcc_fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
+    immr->im_fcc[info->ether_index].fcc_fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
 
     /* 28.9 - (6): FDSR: Ethernet Syn */
-    immr->im_fcc[CONFIG_ETHER_INDEX-1].fcc_fdsr = 0xD555;
+    immr->im_fcc[info->ether_index].fcc_fdsr = 0xD555;
 
     /* reset indeces to current rx/tx bd (see eth_send()/eth_rx()) */
     rxIdx = 0;
@@ -246,7 +268,7 @@ int eth_init(bd_t *bis)
     rtx.txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
 
     /* 28.9 - (7): initialise parameter ram */
-    pram_ptr = (fcc_enet_t *)&(immr->im_dprambase[PROFF_ENET]);
+    pram_ptr = (fcc_enet_t *)&(immr->im_dprambase[info->proff_enet]);
 
     /* clear whole structure to make sure all reserved fields are zero */
     memset((void*)pram_ptr, 0, sizeof(fcc_enet_t));
@@ -259,7 +281,7 @@ int eth_init(bd_t *bis)
      * can do this.  Later, we will add resource management for
      * this area.
      */
-    mem_addr = CPM_FCC_SPECIAL_BASE + ((CONFIG_ETHER_INDEX-1) * 64);
+    mem_addr = CPM_FCC_SPECIAL_BASE + ((info->ether_index) * 64);
     pram_ptr->fen_genfcc.fcc_riptr = mem_addr;
     pram_ptr->fen_genfcc.fcc_tiptr = mem_addr+32;
     /*
@@ -288,7 +310,7 @@ int eth_init(bd_t *bis)
      * it unique by setting a few bits in the upper byte of the
      * non-static part of the address.
      */
-#define ea bis->bi_enetaddr
+#define ea eth_get_dev()->enetaddr
     pram_ptr->fen_paddrh = (ea[5] << 8) + ea[4];
     pram_ptr->fen_paddrm = (ea[3] << 8) + ea[2];
     pram_ptr->fen_paddrl = (ea[1] << 8) + ea[0];
@@ -308,10 +330,10 @@ int eth_init(bd_t *bis)
 #endif
 
     /* 28.9 - (8): clear out events in FCCE */
-    immr->im_fcc[CONFIG_ETHER_INDEX-1].fcc_fcce = ~0x0;
+    immr->im_fcc[info->ether_index].fcc_fcce = ~0x0;
 
     /* 28.9 - (9): FCCM: mask all events */
-    immr->im_fcc[CONFIG_ETHER_INDEX-1].fcc_fccm = 0;
+    immr->im_fcc[info->ether_index].fcc_fccm = 0;
 
     /* 28.9 - (10-12): we don't use ethernet interrupts */
 
@@ -321,8 +343,8 @@ int eth_init(bd_t *bis)
      * than the manual describes because we have just now finished
      * the BD initialization.
      */
-    cp->cp_cpcr = mk_cr_cmd(CPM_CR_ENET_PAGE,
-			    CPM_CR_ENET_SBLOCK,
+    cp->cp_cpcr = mk_cr_cmd(info->cpm_cr_enet_page,
+			    info->cpm_cr_enet_sblock,
 			    0x0c,
 			    CPM_CR_INIT_TRX) | CPM_CR_FLG;
     do {
@@ -330,18 +352,43 @@ int eth_init(bd_t *bis)
     } while (cp->cp_cpcr & CPM_CR_FLG);
 
     /* 28.9 - (14): enable tx/rx in gfmr */
-    immr->im_fcc[CONFIG_ETHER_INDEX-1].fcc_gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
+    immr->im_fcc[info->ether_index].fcc_gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
 
     return 1;
 }
 
-void eth_halt(void)
+static void fec_halt(struct eth_device* dev)
 {
+    struct ether_fcc_info_s * info = dev->priv;
     volatile immap_t *immr = (immap_t *)CFG_IMMR;
 
     /* write GFMR: disable tx/rx */
-    immr->im_fcc[CONFIG_ETHER_INDEX-1].fcc_gfmr &=
+    immr->im_fcc[info->ether_index].fcc_gfmr &=
 						~(FCC_GFMR_ENT | FCC_GFMR_ENR);
 }
 
-#endif	/* CONFIG_ETHER_ON_FCC && CFG_CMD_NET */
+int fec_initialize(bd_t *bis)
+{
+	struct eth_device* dev;
+	int i;
+
+	for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++)
+	{
+		dev = (struct eth_device*) malloc(sizeof *dev);
+		memset(dev, 0, sizeof *dev);
+
+		sprintf(dev->name, "FCC%d ETHERNET",
+		        ether_fcc_info[i].ether_index + 1);
+		dev->priv   = &ether_fcc_info[i];
+		dev->init   = fec_init;
+		dev->halt   = fec_halt;
+		dev->send   = fec_send;
+		dev->recv   = fec_recv;
+
+		eth_register(dev);
+	}
+
+	return 1;
+}
+
+#endif	/* CONFIG_ETHER_ON_FCC && CFG_CMD_NET && CONFIG_NET_MULTI */

include/configs/PM826.h

@@ -38,6 +38,8 @@
 #define CONFIG_MPC8260		1	/* This is a MPC8260 CPU	*/
 #define CONFIG_PM826		1	/* ...on a PM8260 module	*/
 
+#undef CONFIG_DB_CR826_J30x_ON		/* J30x jumpers on D.B. carrier	*/
+
 #define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
 
 #define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
@@ -93,33 +95,50 @@
 /*
  * select ethernet configuration
  *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
+ * if CONFIG_ETHER_ON_SCC is selected, then
+ *   - CONFIG_ETHER_INDEX must be set to the channel number (1-4)
+ *   - CONFIG_NET_MULTI must not be defined
+ *
+ * if CONFIG_ETHER_ON_FCC is selected, then
+ *   - one or more CONFIG_ETHER_ON_FCCx (x=1,2,3) must also be selected
+ *   - CONFIG_NET_MULTI must be defined
  *
  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
  * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
  * from CONFIG_COMMANDS to remove support for networking.
  */
-#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
-#define	CONFIG_ETHER_ON_FCC		/* define if ether on FCC       */
+#define	CONFIG_NET_MULTI
 #undef	CONFIG_ETHER_NONE		/* define if ether on something else */
-#define	CONFIG_ETHER_INDEX    1		/* which SCC/FCC channel for ethernet */
 
-#if (CONFIG_ETHER_INDEX == 1)
+#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
+#define	CONFIG_ETHER_INDEX    1		/* which SCC channel for ethernet */
+
+#define	CONFIG_ETHER_ON_FCC		/* define if ether on FCC       */
 /*
  * - Rx-CLK is CLK11
  * - Tx-CLK is CLK10
+ */
+#define	CONFIG_ETHER_ON_FCC1
+# define CFG_CMXFCR_MASK1	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
+#ifndef CONFIG_DB_CR826_J30x_ON
+# define CFG_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10)
+#else
+# define CFG_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
+#endif
+/*
+ * - Rx-CLK is CLK15
+ * - Tx-CLK is CLK14
+ */
+#define	CONFIG_ETHER_ON_FCC2
+# define CFG_CMXFCR_MASK2	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
+# define CFG_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+/*
  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  * - Enable Full Duplex in FSMR
  */
-# define CFG_CMXFCR_MASK	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10)
 # define CFG_CPMFCR_RAMTYPE	0
 # define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
 
-#endif /* CONFIG_ETHER_INDEX */
-
 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
 #define CONFIG_8260_CLKIN	64000000	/* in Hz */
 

include/configs/TQM823L.h

@@ -178,7 +178,7 @@
  * FLASH organization
  */
 #define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/
+#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip	*/
 
 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

include/configs/TQM850L.h

@@ -170,7 +170,7 @@
  * FLASH organization
  */
 #define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/
+#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip	*/
 
 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

include/configs/TQM855L.h

@@ -170,7 +170,7 @@
  * FLASH organization
  */
 #define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/
+#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip	*/
 
 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

include/configs/TQM860L.h

@@ -170,7 +170,7 @@
  * FLASH organization
  */
 #define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/
+#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip	*/
 
 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

include/net.h

@@ -18,6 +18,30 @@
 #define CONFIG_NET_MULTI
 #endif
 #endif
+
+#if !defined(CONFIG_NET_MULTI) && defined(CONFIG_8260)
+#include <config.h>
+#if defined(CONFIG_ETHER_ON_FCC)
+#if defined(CONFIG_ETHER_ON_SCC)
+#error "Ethernet not correctly defined"
+#endif /* CONFIG_ETHER_ON_SCC */
+#define CONFIG_NET_MULTI
+#if (CONFIG_ETHER_INDEX == 1)
+#define	CONFIG_ETHER_ON_FCC1
+# define CFG_CMXFCR_MASK1	CFG_CMXFCR_MASK
+# define CFG_CMXFCR_VALUE1	CFG_CMXFCR_VALUE
+#elif (CONFIG_ETHER_INDEX == 2)
+#define	CONFIG_ETHER_ON_FCC2
+# define CFG_CMXFCR_MASK2	CFG_CMXFCR_MASK
+# define CFG_CMXFCR_VALUE2	CFG_CMXFCR_VALUE
+#elif (CONFIG_ETHER_INDEX == 3)
+#define	CONFIG_ETHER_ON_FCC3
+# define CFG_CMXFCR_MASK3	CFG_CMXFCR_MASK
+# define CFG_CMXFCR_VALUE3	CFG_CMXFCR_VALUE
+#endif /* CONFIG_ETHER_INDEX */
+#endif /* CONFIG_ETHER_ON_FCC */
+#endif /* !CONFIG_NET_MULTI && CONFIG_8260 */
+
 #include <asm/byteorder.h>	/* for nton* / ntoh* stuff */
 
 

net/eth.c

@@ -119,7 +119,7 @@ int eth_initialize(bd_t *bis)
 #ifdef SCC_ENET
 	scc_initialize(bis);
 #endif
-#ifdef FEC_ENET
+#if defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
 	fec_initialize(bis);
 #endif