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/*
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/*
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- * (C) Copyright 2007-2008
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+ * (C) Copyright 2007-2009
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* Larry Johnson, lrj@acm.org
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* Larry Johnson, lrj@acm.org
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*
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*
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* (C) Copyright 2006-2007
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* (C) Copyright 2006-2007
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@@ -138,15 +138,14 @@
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/*
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/*
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* DDR SDRAM
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* DDR SDRAM
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*/
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*/
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-#define CONFIG_SYS_MBYTES_SDRAM (512) /* 512 MiB TODO: remove */
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#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
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#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
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#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
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#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
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#define CONFIG_ZERO_SDRAM /* Zero SDRAM after setup */
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#define CONFIG_ZERO_SDRAM /* Zero SDRAM after setup */
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#define CONFIG_DDR_ECC /* Use ECC when available */
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#define CONFIG_DDR_ECC /* Use ECC when available */
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#define SPD_EEPROM_ADDRESS {0x50}
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#define SPD_EEPROM_ADDRESS {0x50}
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#define CONFIG_PROG_SDRAM_TLB
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#define CONFIG_PROG_SDRAM_TLB
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-#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
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- /* 440EPx errata CHIP 11 */
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+#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4 KiB as */
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+ /* per 440EPx Errata CHIP_11 */
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/*
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/*
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* I2C
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* I2C
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@@ -173,42 +172,59 @@
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#define CONFIG_SYS_DTT_MIN_TEMP -30
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#define CONFIG_SYS_DTT_MIN_TEMP -30
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#define CONFIG_PREBOOT "echo;" \
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#define CONFIG_PREBOOT "echo;" \
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- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
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+ "echo Type \\\"run flash_cf\\\" to mount from CompactFlash(R);" \
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"echo"
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"echo"
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#undef CONFIG_BOOTARGS
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#undef CONFIG_BOOTARGS
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/* Setup some board specific values for the default environment variables */
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/* Setup some board specific values for the default environment variables */
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#define CONFIG_HOSTNAME korat
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#define CONFIG_HOSTNAME korat
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-#define CONFIG_SYS_BOOTFILE "bootfile=/tftpboot/korat/uImage\0"
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-#define CONFIG_SYS_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0"
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/* Note: kernel_addr and ramdisk_addr assume that FLASH1 is 64 MiB. */
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/* Note: kernel_addr and ramdisk_addr assume that FLASH1 is 64 MiB. */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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#define CONFIG_EXTRA_ENV_SETTINGS \
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- CONFIG_SYS_BOOTFILE \
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- CONFIG_SYS_ROOTPATH \
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+ "u_boot=korat/u-boot.bin\0" \
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+ "load=tftp 200000 ${u_boot}\0" \
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+ "update=protect off F7F60000 F7FBFFFF;erase F7F60000 F7FBFFFF;" \
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+ "cp.b ${fileaddr} F7F60000 ${filesize};protect on " \
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+ "F7F60000 F7FBFFFF\0" \
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+ "upd=run load update\0" \
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+ "bootfile=korat/uImage\0" \
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+ "dtb=korat/korat.dtb\0" \
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+ "kernel_addr=F4000000\0" \
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+ "ramdisk_addr=F4400000\0" \
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+ "dtb_addr=F41E0000\0" \
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+ "udl=tftp 200000 ${bootfile}; erase F4000000 F41DFFFF; " \
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+ "cp.b ${fileaddr} F4000000 ${filesize}\0" \
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+ "udd=tftp 200000 ${dtb}; erase F41E0000 F41FFFFF; " \
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+ "cp.b ${fileaddr} F41E0000 ${filesize}\0" \
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+ "ll=setenv kernel_addr 200000; setenv dtb_addr 1000000; " \
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+ "tftp ${kernel_addr} ${uImage}; tftp ${dtb_addr} " \
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+ "${dtb}\0" \
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+ "rd_size=73728\0" \
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+ "ramargs=setenv bootargs root=/dev/ram rw " \
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+ "ramdisk_size=${rd_size}\0" \
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+ "usbdev=sda1\0" \
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+ "usbargs=setenv bootargs root=/dev/${usbdev} ro rootdelay=10\0" \
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+ "rootpath=/opt/eldk/ppc_4xxFP\0" \
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"netdev=eth0\0" \
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"netdev=eth0\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"nfsroot=${serverip}:${rootpath}\0" \
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- "ramargs=setenv bootargs root=/dev/ram rw\0" \
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+ "pciclk=33\0" \
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+ "addide=setenv bootargs ${bootargs} ide=reverse " \
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+ "idebus=${pciclk}\0" \
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"addip=setenv bootargs ${bootargs} " \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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":${hostname}:${netdev}:off panic=1\0" \
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"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
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"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
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- "flash_nfs=run nfsargs addip addtty;" \
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- "bootm ${kernel_addr}\0" \
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- "flash_self=run ramargs addip addtty;" \
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- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
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- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
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- "bootm\0" \
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- "kernel_addr=F4000000\0" \
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- "ramdisk_addr=F4400000\0" \
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- "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \
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- "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
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- "cp.b 200000 FFFA0000 60000\0" \
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- "upd=run load update\0" \
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+ "flash_cf=run usbargs addide addip addtty; " \
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+ "bootm ${kernel_addr} - ${dtb_addr}\0" \
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+ "flash_nfs=run nfsargs addide addip addtty; " \
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+ "bootm ${kernel_addr} - ${dtb_addr}\0" \
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+ "flash_self=run ramargs addip addtty; " \
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+ "bootm ${kernel_addr} ${ramdisk_addr} ${dtb_addr}\0" \
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""
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""
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-#define CONFIG_BOOTCOMMAND "run flash_self"
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+
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+#define CONFIG_BOOTCOMMAND "run flash_cf"
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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@@ -278,15 +294,15 @@
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#define CONFIG_CMD_USB
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#define CONFIG_CMD_USB
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/* POST support */
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/* POST support */
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-#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
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- CONFIG_SYS_POST_CPU | \
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- CONFIG_SYS_POST_ECC | \
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- CONFIG_SYS_POST_ETHER | \
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- CONFIG_SYS_POST_FPU | \
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- CONFIG_SYS_POST_I2C | \
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- CONFIG_SYS_POST_MEMORY | \
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- CONFIG_SYS_POST_RTC | \
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- CONFIG_SYS_POST_SPR | \
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+#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
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+ CONFIG_SYS_POST_CPU | \
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+ CONFIG_SYS_POST_ECC | \
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+ CONFIG_SYS_POST_ETHER | \
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+ CONFIG_SYS_POST_FPU | \
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+ CONFIG_SYS_POST_I2C | \
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+ CONFIG_SYS_POST_MEMORY | \
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+ CONFIG_SYS_POST_RTC | \
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+ CONFIG_SYS_POST_SPR | \
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CONFIG_SYS_POST_UART)
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CONFIG_SYS_POST_UART)
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#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
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#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
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@@ -403,7 +419,7 @@
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* GPIO10 Alt1 O x PerCS5 to expansion bus connector
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* GPIO10 Alt1 O x PerCS5 to expansion bus connector
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* GPIO11 Alt1 I x PerErr
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* GPIO11 Alt1 I x PerErr
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* GPIO12 GPIO O 0 ATMega !Reset
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* GPIO12 GPIO O 0 ATMega !Reset
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- * GPIO13 GPIO O 1 SPI Atmega !SS
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+ * GPIO13 GPIO x x Test Point 2 (TP2)
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* GPIO14 GPIO O 1 Write protect EEPROM #1 (0xA8)
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* GPIO14 GPIO O 1 Write protect EEPROM #1 (0xA8)
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* GPIO15 GPIO O 0 CPU Run LED !On
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* GPIO15 GPIO O 0 CPU Run LED !On
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* GPIO16 Alt1 O x GMC1TxD0
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* GPIO16 Alt1 O x GMC1TxD0
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@@ -478,7 +494,7 @@
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \
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{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \
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{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
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-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO13 */ \
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+{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4) */ \
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