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@@ -321,17 +321,17 @@ unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
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unsigned effective_rate;
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int mux_bits, divider_bits, source;
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int divider;
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+ int xdiv = 0;
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/* work out the source clock and set it */
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source = get_periph_clock_source(periph_id, parent, &mux_bits,
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÷r_bits);
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+ divider = find_best_divider(divider_bits, pll_rate[parent],
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+ rate, &xdiv);
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if (extra_div)
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- divider = find_best_divider(divider_bits, pll_rate[parent],
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- rate, extra_div);
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- else
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- divider = clk_get_divider(divider_bits, pll_rate[parent],
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- rate);
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+ *extra_div = xdiv;
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+
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assert(divider >= 0);
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if (adjust_periph_pll(periph_id, source, mux_bits, divider))
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return -1U;
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