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@@ -39,8 +39,10 @@
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#define CFG_HZ 1000
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/*
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- * Set up the PLL to run at 199.5 MHz, the CPU to run at 1/2 the PLL
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- * frequency and the peripherals to run at 1/4 the PLL frequency.
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+ * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
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+ * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
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+ * PLL frequency.
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+ * (CFG_OSC0_HZ * CFG_PLL0_MUL) / CFG_PLL0_DIV = PLL MHz
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*/
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#define CONFIG_PLL 1
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#define CFG_POWER_MANAGER 1
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@@ -48,9 +50,25 @@
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#define CFG_PLL0_DIV 1
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#define CFG_PLL0_MUL 7
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#define CFG_PLL0_SUPPRESS_CYCLES 16
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+/*
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+ * Set the CPU running at:
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+ * PLL / (2^CFG_CLKDIV_CPU) = CPU MHz
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+ */
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#define CFG_CLKDIV_CPU 0
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+/*
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+ * Set the HSB running at:
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+ * PLL / (2^CFG_CLKDIV_HSB) = HSB MHz
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+ */
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#define CFG_CLKDIV_HSB 1
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+/*
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+ * Set the PBA running at:
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+ * PLL / (2^CFG_CLKDIV_PBA) = PBA MHz
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+ */
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#define CFG_CLKDIV_PBA 2
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+/*
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+ * Set the PBB running at:
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+ * PLL / (2^CFG_CLKDIV_PBB) = PBB MHz
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+ */
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#define CFG_CLKDIV_PBB 1
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/*
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