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@@ -23,29 +23,71 @@
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#include <common.h>
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#ifndef CONFIG_SYS_DCACHE_OFF
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-static inline void dcache_noop(void)
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+
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+#ifndef CONFIG_SYS_CACHELINE_SIZE
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+#define CONFIG_SYS_CACHELINE_SIZE 32
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+#endif
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+
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+void invalidate_dcache_all(void)
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{
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- if (dcache_status()) {
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- puts("WARNING: cache operations are not implemented!\n"
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- "WARNING: disabling D-Cache now, you can re-enable it"
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- "later with 'dcache on' command\n");
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- dcache_disable();
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- }
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+ asm volatile("mcr p15, 0, %0, c7, c6, 0\n"::"r"(0));
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}
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-void invalidate_dcache_all(void)
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+void flush_dcache_all(void)
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{
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- dcache_noop();
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+ asm volatile(
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+ "0:"
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+ "mrc p15, 0, r15, c7, c14, 3\n"
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+ "bne 0b\n"
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+ "mcr p15, 0, %0, c7, c10, 4\n"
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+ ::"r"(0):"memory"
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+ );
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+}
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+
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+static int check_cache_range(unsigned long start, unsigned long stop)
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+{
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+ int ok = 1;
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+
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+ if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
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+ ok = 0;
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+
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+ if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
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+ ok = 0;
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+
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+ if (!ok)
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+ printf("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
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+ start, stop);
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+
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+ return ok;
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}
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void invalidate_dcache_range(unsigned long start, unsigned long stop)
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{
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- dcache_noop();
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+ if (!check_cache_range(start, stop))
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+ return;
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+
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+ while (start < stop) {
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+ asm volatile("mcr p15, 0, %0, c7, c6, 1\n"::"r"(start));
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+ start += CONFIG_SYS_CACHELINE_SIZE;
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+ }
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}
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void flush_dcache_range(unsigned long start, unsigned long stop)
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{
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- dcache_noop();
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+ if (!check_cache_range(start, stop))
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+ return;
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+
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+ while (start < stop) {
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+ asm volatile("mcr p15, 0, %0, c7, c14, 1\n"::"r"(start));
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+ start += CONFIG_SYS_CACHELINE_SIZE;
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+ }
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+
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+ asm("mcr p15, 0, %0, c7, c10, 4\n"::"r"(0));
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+}
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+
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+void flush_cache(unsigned long start, unsigned long size)
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+{
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+ flush_dcache_range(start, start + size);
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}
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#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
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void invalidate_dcache_all(void)
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@@ -64,7 +106,7 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
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{
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}
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-void flush_cache(unsigned long start, unsigned long size)
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+void flush_cache(unsigned long start, unsigned long size)
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{
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}
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#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
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