|
@@ -30,7 +30,7 @@
|
|
#define CONFIG_PLL_BYPASS 0
|
|
#define CONFIG_PLL_BYPASS 0
|
|
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
|
|
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
|
|
/* Values can range from 0-63 (where 0 means 64) */
|
|
/* Values can range from 0-63 (where 0 means 64) */
|
|
-#define CONFIG_VCO_MULT 36
|
|
|
|
|
|
+#define CONFIG_VCO_MULT 45
|
|
/* CCLK_DIV controls the core clock divider */
|
|
/* CCLK_DIV controls the core clock divider */
|
|
/* Values can be 1, 2, 4, or 8 ONLY */
|
|
/* Values can be 1, 2, 4, or 8 ONLY */
|
|
#define CONFIG_CCLK_DIV 1
|
|
#define CONFIG_CCLK_DIV 1
|