|
@@ -45,70 +45,51 @@
|
|
|
|
|
|
void at91_serial0_hw_init(void)
|
|
void at91_serial0_hw_init(void)
|
|
{
|
|
{
|
|
- at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
|
|
|
|
|
|
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
|
|
|
|
|
|
at91_set_a_periph(AT91_PIO_PORTB, 4, 1); /* TXD0 */
|
|
at91_set_a_periph(AT91_PIO_PORTB, 4, 1); /* TXD0 */
|
|
at91_set_a_periph(AT91_PIO_PORTB, 5, PUP); /* RXD0 */
|
|
at91_set_a_periph(AT91_PIO_PORTB, 5, PUP); /* RXD0 */
|
|
- writel(1 << AT91SAM9260_ID_US0, &pmc->pcer);
|
|
|
|
|
|
+ writel(1 << ATMEL_ID_USART0, &pmc->pcer);
|
|
}
|
|
}
|
|
|
|
|
|
void at91_serial1_hw_init(void)
|
|
void at91_serial1_hw_init(void)
|
|
{
|
|
{
|
|
- at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
|
|
|
|
|
|
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
|
|
|
|
|
|
at91_set_a_periph(AT91_PIO_PORTB, 6, 1); /* TXD1 */
|
|
at91_set_a_periph(AT91_PIO_PORTB, 6, 1); /* TXD1 */
|
|
at91_set_a_periph(AT91_PIO_PORTB, 7, PUP); /* RXD1 */
|
|
at91_set_a_periph(AT91_PIO_PORTB, 7, PUP); /* RXD1 */
|
|
- writel(1 << AT91SAM9260_ID_US1, &pmc->pcer);
|
|
|
|
|
|
+ writel(1 << ATMEL_ID_USART1, &pmc->pcer);
|
|
}
|
|
}
|
|
|
|
|
|
void at91_serial2_hw_init(void)
|
|
void at91_serial2_hw_init(void)
|
|
{
|
|
{
|
|
- at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
|
|
|
|
|
|
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
|
|
|
|
|
|
at91_set_a_periph(AT91_PIO_PORTB, 8, 1); /* TXD2 */
|
|
at91_set_a_periph(AT91_PIO_PORTB, 8, 1); /* TXD2 */
|
|
at91_set_a_periph(AT91_PIO_PORTB, 9, PUP); /* RXD2 */
|
|
at91_set_a_periph(AT91_PIO_PORTB, 9, PUP); /* RXD2 */
|
|
- writel(1 << AT91SAM9260_ID_US2, &pmc->pcer);
|
|
|
|
|
|
+ writel(1 << ATMEL_ID_USART2, &pmc->pcer);
|
|
}
|
|
}
|
|
|
|
|
|
-void at91_serial3_hw_init(void)
|
|
|
|
|
|
+void at91_seriald_hw_init(void)
|
|
{
|
|
{
|
|
- at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
|
|
|
|
|
|
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
|
|
|
|
|
|
at91_set_a_periph(AT91_PIO_PORTB, 14, PUP); /* DRXD */
|
|
at91_set_a_periph(AT91_PIO_PORTB, 14, PUP); /* DRXD */
|
|
at91_set_a_periph(AT91_PIO_PORTB, 15, 1); /* DTXD */
|
|
at91_set_a_periph(AT91_PIO_PORTB, 15, 1); /* DTXD */
|
|
- writel(1 << AT91_ID_SYS, &pmc->pcer);
|
|
|
|
-}
|
|
|
|
-
|
|
|
|
-void at91_serial_hw_init(void)
|
|
|
|
-{
|
|
|
|
-#ifdef CONFIG_USART0
|
|
|
|
- at91_serial0_hw_init();
|
|
|
|
-#endif
|
|
|
|
-
|
|
|
|
-#ifdef CONFIG_USART1
|
|
|
|
- at91_serial1_hw_init();
|
|
|
|
-#endif
|
|
|
|
-
|
|
|
|
-#ifdef CONFIG_USART2
|
|
|
|
- at91_serial2_hw_init();
|
|
|
|
-#endif
|
|
|
|
-
|
|
|
|
-#ifdef CONFIG_USART3 /* DBGU */
|
|
|
|
- at91_serial3_hw_init();
|
|
|
|
-#endif
|
|
|
|
|
|
+ writel(1 << ATMEL_ID_SYS, &pmc->pcer);
|
|
}
|
|
}
|
|
|
|
|
|
#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
|
|
#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
|
|
void at91_spi0_hw_init(unsigned long cs_mask)
|
|
void at91_spi0_hw_init(unsigned long cs_mask)
|
|
{
|
|
{
|
|
- at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
|
|
|
|
|
|
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
|
|
|
|
|
|
at91_set_a_periph(AT91_PIO_PORTA, 0, PUP); /* SPI0_MISO */
|
|
at91_set_a_periph(AT91_PIO_PORTA, 0, PUP); /* SPI0_MISO */
|
|
at91_set_a_periph(AT91_PIO_PORTA, 1, PUP); /* SPI0_MOSI */
|
|
at91_set_a_periph(AT91_PIO_PORTA, 1, PUP); /* SPI0_MOSI */
|
|
at91_set_a_periph(AT91_PIO_PORTA, 2, PUP); /* SPI0_SPCK */
|
|
at91_set_a_periph(AT91_PIO_PORTA, 2, PUP); /* SPI0_SPCK */
|
|
|
|
|
|
/* Enable clock */
|
|
/* Enable clock */
|
|
- writel(1 << AT91SAM9260_ID_SPI0, &pmc->pcer);
|
|
|
|
|
|
+ writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
|
|
|
|
|
|
if (cs_mask & (1 << 0)) {
|
|
if (cs_mask & (1 << 0)) {
|
|
at91_set_a_periph(AT91_PIO_PORTA, 3, 1);
|
|
at91_set_a_periph(AT91_PIO_PORTA, 3, 1);
|
|
@@ -138,14 +119,14 @@ void at91_spi0_hw_init(unsigned long cs_mask)
|
|
|
|
|
|
void at91_spi1_hw_init(unsigned long cs_mask)
|
|
void at91_spi1_hw_init(unsigned long cs_mask)
|
|
{
|
|
{
|
|
- at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
|
|
|
|
|
|
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
|
|
|
|
|
|
at91_set_a_periph(AT91_PIO_PORTB, 0, PUP); /* SPI1_MISO */
|
|
at91_set_a_periph(AT91_PIO_PORTB, 0, PUP); /* SPI1_MISO */
|
|
at91_set_a_periph(AT91_PIO_PORTB, 1, PUP); /* SPI1_MOSI */
|
|
at91_set_a_periph(AT91_PIO_PORTB, 1, PUP); /* SPI1_MOSI */
|
|
at91_set_a_periph(AT91_PIO_PORTB, 2, PUP); /* SPI1_SPCK */
|
|
at91_set_a_periph(AT91_PIO_PORTB, 2, PUP); /* SPI1_SPCK */
|
|
|
|
|
|
/* Enable clock */
|
|
/* Enable clock */
|
|
- writel(1 << AT91SAM9260_ID_SPI1, &pmc->pcer);
|
|
|
|
|
|
+ writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
|
|
|
|
|
|
if (cs_mask & (1 << 0)) {
|
|
if (cs_mask & (1 << 0)) {
|
|
at91_set_a_periph(AT91_PIO_PORTB, 3, 1);
|
|
at91_set_a_periph(AT91_PIO_PORTB, 3, 1);
|