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@@ -49,7 +49,7 @@
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# define SCFRDR (vu_char *)(SCIF_BASE + 0x24)
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#else
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# define SCFTDR (vu_char *)(SCIF_BASE + 0xC)
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-# define SCFSR (vu_short *)(SCIF_BASE + 0x10)
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+# define SCFSR (vu_short *)(SCIF_BASE + 0x10)
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# define SCFRDR (vu_char *)(SCIF_BASE + 0x14)
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#endif
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@@ -64,7 +64,7 @@
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#elif defined(CONFIG_CPU_SH7763)
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# if defined(CONFIG_CONS_SCIF2)
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# define SCSPTR (vu_short *)(SCIF_BASE + 0x20)
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-# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
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+# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
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# define LSR_ORER 1
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# define FIFOLEVEL_MASK 0x1F
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# else
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@@ -90,7 +90,7 @@
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defined(CONFIG_CPU_SH7722) || \
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defined(CONFIG_CPU_SH7203)
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# define SCSPTR (vu_short *)(SCIF_BASE + 0x20)
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-# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
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+# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
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# define LSR_ORER 1
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# define FIFOLEVEL_MASK 0x1F
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#elif defined(CONFIG_CPU_SH7720)
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@@ -106,31 +106,32 @@
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/* SCBRR register value setting */
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#if defined(CONFIG_CPU_SH7720)
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-# define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
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+# define SCBRR_VALUE(bps, clk) (((clk * 2) + 16 * bps) / (32 * bps) - 1)
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#elif defined(CONFIG_CPU_SH7723) && defined(CONFIG_SCIF_A)
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/* SH7723 SCIFA use bus clock. So clock *2 */
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-# define SCBRR_VALUE(bps, clk) (((clk*2*2)+16*bps)/(32*bps)-1)
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+# define SCBRR_VALUE(bps, clk) (((clk * 2 * 2) + 16 * bps) / (32 * bps) - 1)
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#else /* Generic SuperH */
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-# define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
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+# define SCBRR_VALUE(bps, clk) ((clk + 16 * bps) / (32 * bps) - 1)
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#endif
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-#define SCR_RE (1 << 4)
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-#define SCR_TE (1 << 5)
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+#define SCR_RE (1 << 4)
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+#define SCR_TE (1 << 5)
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#define FCR_RFRST (1 << 1) /* RFCL */
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#define FCR_TFRST (1 << 2) /* TFCL */
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-#define FSR_DR (1 << 0)
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-#define FSR_RDF (1 << 1)
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-#define FSR_FER (1 << 3)
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-#define FSR_BRK (1 << 4)
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-#define FSR_FER (1 << 3)
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-#define FSR_TEND (1 << 6)
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-#define FSR_ER (1 << 7)
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+#define FSR_DR (1 << 0)
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+#define FSR_RDF (1 << 1)
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+#define FSR_FER (1 << 3)
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+#define FSR_BRK (1 << 4)
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+#define FSR_FER (1 << 3)
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+#define FSR_TEND (1 << 6)
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+#define FSR_ER (1 << 7)
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/*----------------------------------------------------------------------*/
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void serial_setbrg(void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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+
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*SCBRR = SCBRR_VALUE(gd->baudrate, CONFIG_SYS_CLK_FREQ);
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}
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@@ -191,8 +192,8 @@ int serial_tstc(void)
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return serial_rx_fifo_level() ? 1 : 0;
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}
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-#define FSR_ERR_CLEAR 0x0063
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-#define RDRF_CLEAR 0x00fc
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+#define FSR_ERR_CLEAR 0x0063
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+#define RDRF_CLEAR 0x00fc
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void handle_error(void)
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{
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Jean-Christophe PLAGNIOL-VILLARD