|
@@ -321,35 +321,9 @@ cpu_init_f (void)
|
|
*/
|
|
*/
|
|
int cpu_init_r (void)
|
|
int cpu_init_r (void)
|
|
{
|
|
{
|
|
-#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
|
|
|
|
- bd_t *bd = gd->bd;
|
|
|
|
- unsigned long reg;
|
|
|
|
- uchar enetaddr[6];
|
|
|
|
#if defined(CONFIG_405GP)
|
|
#if defined(CONFIG_405GP)
|
|
uint pvr = get_pvr();
|
|
uint pvr = get_pvr();
|
|
-#endif
|
|
|
|
-
|
|
|
|
- /*
|
|
|
|
- * Write Ethernetaddress into on-chip register
|
|
|
|
- */
|
|
|
|
- reg = 0x00000000;
|
|
|
|
- eth_getenv_enetaddr("ethaddr", enetaddr);
|
|
|
|
- reg |= enetaddr[0]; /* set high address */
|
|
|
|
- reg = reg << 8;
|
|
|
|
- reg |= enetaddr[1];
|
|
|
|
- out32 (EMAC_IAH, reg);
|
|
|
|
-
|
|
|
|
- reg = 0x00000000;
|
|
|
|
- reg |= enetaddr[2]; /* set low address */
|
|
|
|
- reg = reg << 8;
|
|
|
|
- reg |= enetaddr[3];
|
|
|
|
- reg = reg << 8;
|
|
|
|
- reg |= enetaddr[4];
|
|
|
|
- reg = reg << 8;
|
|
|
|
- reg |= enetaddr[5];
|
|
|
|
- out32 (EMAC_IAL, reg);
|
|
|
|
|
|
|
|
-#if defined(CONFIG_405GP)
|
|
|
|
/*
|
|
/*
|
|
* Set edge conditioning circuitry on PPC405GPr
|
|
* Set edge conditioning circuitry on PPC405GPr
|
|
* for compatibility to existing PPC405GP designs.
|
|
* for compatibility to existing PPC405GP designs.
|
|
@@ -358,7 +332,6 @@ int cpu_init_r (void)
|
|
mtdcr(ecr, 0x60606000);
|
|
mtdcr(ecr, 0x60606000);
|
|
}
|
|
}
|
|
#endif /* defined(CONFIG_405GP) */
|
|
#endif /* defined(CONFIG_405GP) */
|
|
-#endif /* defined(CONFIG_405GP) || defined(CONFIG_405EP) */
|
|
|
|
|
|
|
|
- return (0);
|
|
|
|
|
|
+ return 0;
|
|
}
|
|
}
|