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@@ -290,7 +290,7 @@
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#define CFG_UEC1_TX_CLK QE_CLK9
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#define CFG_UEC1_ETH_TYPE GIGA_ETH
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#define CFG_UEC1_PHY_ADDR 2
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-#define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII
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+#define CFG_UEC1_INTERFACE_MODE ENET_1000_RGMII_RXID
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#endif
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#define CONFIG_UEC_ETH2 /* GETH2 */
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@@ -301,7 +301,7 @@
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#define CFG_UEC2_TX_CLK QE_CLK4
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#define CFG_UEC2_ETH_TYPE GIGA_ETH
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#define CFG_UEC2_PHY_ADDR 4
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-#define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII
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+#define CFG_UEC2_INTERFACE_MODE ENET_1000_RGMII_RXID
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#endif
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/*
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