Merge branch 'master' of git://git.denx.de/u-boot

MAINTAINERS

@@ -27,6 +27,10 @@ Poonam Aggrwal <poonam.aggrwal@freescale.com>
 
 	BSC9131RDB	BSC9131
 
+Naveen Burmi <NaveenBurmi@freescale.com>
+
+	BSC9132QDS	BSC9132
+
 Greg Allen <gallen@arlut.utexas.edu>
 
 	UTX8245		MPC8245

arch/arm/cpu/arm1136/mx31/timer.c

@@ -115,13 +115,13 @@ unsigned long long get_ticks(void)
 {
 	ulong now = GPTCNT; /* current tick value */
 
-	if (now >= gd->lastinc)	/* normal mode (non roll) */
+	if (now >= gd->arch.lastinc)	/* normal mode (non roll) */
 		/* move stamp forward with absolut diff ticks */
-		gd->tbl += (now - gd->lastinc);
+		gd->arch.tbl += (now - gd->arch.lastinc);
 	else			/* we have rollover of incrementer */
-		gd->tbl += (0xFFFFFFFF - gd->lastinc) + now;
-	gd->lastinc = now;
-	return gd->tbl;
+		gd->arch.tbl += (0xFFFFFFFF - gd->arch.lastinc) + now;
+	gd->arch.lastinc = now;
+	return gd->arch.tbl;
 }
 
 ulong get_timer_masked(void)

arch/arm/cpu/arm1136/mx35/generic.c

@@ -478,11 +478,11 @@ int get_clocks(void)
 {
 #ifdef CONFIG_FSL_ESDHC
 #if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
-	gd->sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 #elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
-	gd->sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 #else
-	gd->sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
+	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
 #endif
 #endif
 	return 0;

arch/arm/cpu/arm1136/mx35/timer.c

@@ -32,8 +32,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define timestamp	(gd->tbl)
-#define lastinc		(gd->lastinc)
+#define timestamp	(gd->arch.tbl)
+#define lastinc		(gd->arch.lastinc)
 
 /* General purpose timers bitfields */
 #define GPTCR_SWR       (1<<15)	/* Software reset */

arch/arm/cpu/arm1136/omap24xx/timer.c

@@ -51,8 +51,8 @@ int timer_init (void)
 	*((int32_t *) (CONFIG_SYS_TIMERBASE + TCLR)) = val;	/* start timer */
 
 	/* reset time */
-	gd->lastinc = READ_TIMER;	/* capture current incrementer value */
-	gd->tbl = 0;			/* start "advancing" time stamp */
+	gd->arch.lastinc = READ_TIMER;	/* capture current incrementer value */
+	gd->arch.tbl = 0;		/* start "advancing" time stamp */
 
 	return(0);
 }
@@ -81,8 +81,8 @@ void __udelay (unsigned long usec)
 	tmp = get_timer (0);		/* get current timestamp */
 	if ((tmo + tmp + 1) < tmp) {	/* if setting this forward will roll */
 					/* time stamp, then reset time */
-		gd->lastinc = READ_TIMER;	/* capture incrementer value */
-		gd->tbl = 0;			/* start time stamp */
+		gd->arch.lastinc = READ_TIMER;	/* capture incrementer value */
+		gd->arch.tbl = 0;			/* start time stamp */
 	} else {
 		tmo	+= tmp;		/* else, set advancing stamp wake up time */
 	}
@@ -94,12 +94,15 @@ ulong get_timer_masked (void)
 {
 	ulong now = READ_TIMER;		/* current tick value */
 
-	if (now >= gd->lastinc)		/* normal mode (non roll) */
-		gd->tbl += (now - gd->lastinc); /* move stamp fordward with absoulte diff ticks */
-	else				/* we have rollover of incrementer */
-		gd->tbl += (0xFFFFFFFF - gd->lastinc) + now;
-	gd->lastinc = now;
-	return gd->tbl;
+	if (now >= gd->arch.lastinc) {		/* normal mode (non roll) */
+		/* move stamp fordward with absoulte diff ticks */
+		gd->arch.tbl += (now - gd->arch.lastinc);
+	} else {
+		/* we have rollover of incrementer */
+		gd->arch.tbl += (0xFFFFFFFF - gd->arch.lastinc) + now;
+	}
+	gd->arch.lastinc = now;
+	return gd->arch.tbl;
 }
 
 /* waits specified delay value and resets timestamp */

arch/arm/cpu/arm920t/a320/timer.c

@@ -31,14 +31,14 @@ DECLARE_GLOBAL_DATA_PTR;
 static inline unsigned long long tick_to_time(unsigned long long tick)
 {
 	tick *= CONFIG_SYS_HZ;
-	do_div(tick, gd->timer_rate_hz);
+	do_div(tick, gd->arch.timer_rate_hz);
 
 	return tick;
 }
 
 static inline unsigned long long usec_to_tick(unsigned long long usec)
 {
-	usec *= gd->timer_rate_hz;
+	usec *= gd->arch.timer_rate_hz;
 	do_div(usec, 1000000);
 
 	return usec;
@@ -74,8 +74,8 @@ int timer_init(void)
 	cr |= FTTMR010_TM3_ENABLE;
 	writel(cr, &tmr->cr);
 
-	gd->timer_rate_hz = TIMER_CLOCK;
-	gd->tbu = gd->tbl = 0;
+	gd->arch.timer_rate_hz = TIMER_CLOCK;
+	gd->arch.tbu = gd->arch.tbl = 0;
 
 	return 0;
 }
@@ -89,10 +89,10 @@ unsigned long long get_ticks(void)
 	ulong now = TIMER_LOAD_VAL - readl(&tmr->timer3_counter);
 
 	/* increment tbu if tbl has rolled over */
-	if (now < gd->tbl)
-		gd->tbu++;
-	gd->tbl = now;
-	return (((unsigned long long)gd->tbu) << 32) | gd->tbl;
+	if (now < gd->arch.tbl)
+		gd->arch.tbu++;
+	gd->arch.tbl = now;
+	return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
 }
 
 void __udelay(unsigned long usec)
@@ -126,5 +126,5 @@ ulong get_timer(ulong base)
  */
 ulong get_tbclk(void)
 {
-	return gd->timer_rate_hz;
+	return gd->arch.timer_rate_hz;
 }

arch/arm/cpu/arm920t/at91/clock.c

@@ -29,11 +29,11 @@ static unsigned long at91_css_to_rate(unsigned long css)
 	case AT91_PMC_MCKR_CSS_SLOW:
 		return CONFIG_SYS_AT91_SLOW_CLOCK;
 	case AT91_PMC_MCKR_CSS_MAIN:
-		return gd->main_clk_rate_hz;
+		return gd->arch.main_clk_rate_hz;
 	case AT91_PMC_MCKR_CSS_PLLA:
-		return gd->plla_rate_hz;
+		return gd->arch.plla_rate_hz;
 	case AT91_PMC_MCKR_CSS_PLLB:
-		return gd->pllb_rate_hz;
+		return gd->arch.pllb_rate_hz;
 	}
 
 	return 0;
@@ -124,10 +124,10 @@ int at91_clock_init(unsigned long main_clock)
 		main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
 	}
 #endif
-	gd->main_clk_rate_hz = main_clock;
+	gd->arch.main_clk_rate_hz = main_clock;
 
 	/* report if PLLA is more than mildly overclocked */
-	gd->plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
+	gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
 
 #ifdef CONFIG_USB_ATMEL
 	/*
@@ -136,9 +136,10 @@ int at91_clock_init(unsigned long main_clock)
 	 *
 	 * REVISIT:  assumes MCK doesn't derive from PLLB!
 	 */
-	gd->at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
+	gd->arch.at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
 			     AT91_PMC_PLLBR_USBDIV_2;
-	gd->pllb_rate_hz = at91_pll_rate(main_clock, gd->at91_pllb_usb_init);
+	gd->arch.pllb_rate_hz = at91_pll_rate(main_clock,
+					      gd->arch.at91_pllb_usb_init);
 #endif
 
 	/*
@@ -146,13 +147,14 @@ int at91_clock_init(unsigned long main_clock)
 	 * For now, assume this parentage won't change.
 	 */
 	mckr = readl(&pmc->mckr);
-	gd->mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
-	freq = gd->mck_rate_hz;
+	gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
+	freq = gd->arch.mck_rate_hz;
 
 	freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2));	/* prescale */
 	/* mdiv */
-	gd->mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
-	gd->cpu_clk_rate_hz = freq;
+	gd->arch.mck_rate_hz = freq /
+			(1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
+	gd->arch.cpu_clk_rate_hz = freq;
 
 	return 0;
 }

arch/arm/cpu/arm920t/at91/timer.c

@@ -63,8 +63,8 @@ int timer_init(void)
 	writel(TIMER_LOAD_VAL, &tc->tc[0].rc);
 
 	writel(AT91_TC_CCR_SWTRG | AT91_TC_CCR_CLKEN, &tc->tc[0].ccr);
-	gd->lastinc = 0;
-	gd->tbl = 0;
+	gd->arch.lastinc = 0;
+	gd->arch.tbl = 0;
 
 	return 0;
 }
@@ -89,16 +89,16 @@ ulong get_timer_raw(void)
 
 	now = readl(&tc->tc[0].cv) & 0x0000ffff;
 
-	if (now >= gd->lastinc) {
+	if (now >= gd->arch.lastinc) {
 		/* normal mode */
-		gd->tbl += now - gd->lastinc;
+		gd->arch.tbl += now - gd->arch.lastinc;
 	} else {
 		/* we have an overflow ... */
-		gd->tbl += now + TIMER_LOAD_VAL - gd->lastinc;
+		gd->arch.tbl += now + TIMER_LOAD_VAL - gd->arch.lastinc;
 	}
-	gd->lastinc = now;
+	gd->arch.lastinc = now;
 
-	return gd->tbl;
+	return gd->arch.tbl;
 }
 
 ulong get_timer_masked(void)

arch/arm/cpu/arm920t/s3c24x0/timer.c

@@ -45,25 +45,25 @@ int timer_init(void)
 	/* use PWM Timer 4 because it has no output */
 	/* prescaler for Timer 4 is 16 */
 	writel(0x0f00, &timers->tcfg0);
-	if (gd->tbu == 0) {
+	if (gd->arch.tbu == 0) {
 		/*
 		 * for 10 ms clock period @ PCLK with 4 bit divider = 1/2
 		 * (default) and prescaler = 16. Should be 10390
 		 * @33.25MHz and 15625 @ 50 MHz
 		 */
-		gd->tbu = get_PCLK() / (2 * 16 * 100);
-		gd->timer_rate_hz = get_PCLK() / (2 * 16);
+		gd->arch.tbu = get_PCLK() / (2 * 16 * 100);
+		gd->arch.timer_rate_hz = get_PCLK() / (2 * 16);
 	}
 	/* load value for 10 ms timeout */
-	writel(gd->tbu, &timers->tcntb4);
+	writel(gd->arch.tbu, &timers->tcntb4);
 	/* auto load, manual update of timer 4 */
 	tmr = (readl(&timers->tcon) & ~0x0700000) | 0x0600000;
 	writel(tmr, &timers->tcon);
 	/* auto load, start timer 4 */
 	tmr = (tmr & ~0x0700000) | 0x0500000;
 	writel(tmr, &timers->tcon);
-	gd->lastinc = 0;
-	gd->tbl = 0;
+	gd->arch.lastinc = 0;
+	gd->arch.tbl = 0;
 
 	return 0;
 }
@@ -82,7 +82,7 @@ void __udelay (unsigned long usec)
 	ulong start = get_ticks();
 
 	tmo = usec / 1000;
-	tmo *= (gd->tbu * 100);
+	tmo *= (gd->arch.tbu * 100);
 	tmo /= 1000;
 
 	while ((ulong) (get_ticks() - start) < tmo)
@@ -93,7 +93,7 @@ ulong get_timer_masked(void)
 {
 	ulong tmr = get_ticks();
 
-	return tmr / (gd->timer_rate_hz / CONFIG_SYS_HZ);
+	return tmr / (gd->arch.timer_rate_hz / CONFIG_SYS_HZ);
 }
 
 void udelay_masked(unsigned long usec)
@@ -104,10 +104,10 @@ void udelay_masked(unsigned long usec)
 
 	if (usec >= 1000) {
 		tmo = usec / 1000;
-		tmo *= (gd->tbu * 100);
+		tmo *= (gd->arch.tbu * 100);
 		tmo /= 1000;
 	} else {
-		tmo = usec * (gd->tbu * 100);
+		tmo = usec * (gd->arch.tbu * 100);
 		tmo /= (1000 * 1000);
 	}
 
@@ -128,16 +128,16 @@ unsigned long long get_ticks(void)
 	struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
 	ulong now = readl(&timers->tcnto4) & 0xffff;
 
-	if (gd->lastinc >= now) {
+	if (gd->arch.lastinc >= now) {
 		/* normal mode */
-		gd->tbl += gd->lastinc - now;
+		gd->arch.tbl += gd->arch.lastinc - now;
 	} else {
 		/* we have an overflow ... */
-		gd->tbl += gd->lastinc + gd->tbu - now;
+		gd->arch.tbl += gd->arch.lastinc + gd->arch.tbu - now;
 	}
-	gd->lastinc = now;
+	gd->arch.lastinc = now;
 
-	return gd->tbl;
+	return gd->arch.tbl;
 }
 
 /*

arch/arm/cpu/arm926ejs/armada100/timer.c

@@ -61,7 +61,7 @@ struct armd1tmr_registers {
 #define	COUNT_RD_REQ		0x1
 
 DECLARE_GLOBAL_DATA_PTR;
-/* Using gd->tbu from timestamp and gd->tbl for lastdec */
+/* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */
 
 /* For preventing risk of instability in reading counter value,
  * first set read request to register cvwr and then read same
@@ -82,16 +82,16 @@ ulong get_timer_masked(void)
 {
 	ulong now = read_timer();
 
-	if (now >= gd->tbl) {
+	if (now >= gd->arch.tbl) {
 		/* normal mode */
-		gd->tbu += now - gd->tbl;
+		gd->arch.tbu += now - gd->arch.tbl;
 	} else {
 		/* we have an overflow ... */
-		gd->tbu += now + TIMER_LOAD_VAL - gd->tbl;
+		gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl;
 	}
-	gd->tbl = now;
+	gd->arch.tbl = now;
 
-	return gd->tbu;
+	return gd->arch.tbu;
 }
 
 ulong get_timer(ulong base)
@@ -135,9 +135,9 @@ int timer_init(void)
 
 	/* Enable timer 0 */
 	writel(0x1, &armd1timers->cer);
-	/* init the gd->tbu and gd->tbl value */
-	gd->tbl = read_timer();
-	gd->tbu = 0;
+	/* init the gd->arch.tbu and gd->arch.tbl value */
+	gd->arch.tbl = read_timer();
+	gd->arch.tbu = 0;
 
 	return 0;
 }

arch/arm/cpu/arm926ejs/at91/clock.c

@@ -29,11 +29,11 @@ static unsigned long at91_css_to_rate(unsigned long css)
 	case AT91_PMC_MCKR_CSS_SLOW:
 		return CONFIG_SYS_AT91_SLOW_CLOCK;
 	case AT91_PMC_MCKR_CSS_MAIN:
-		return gd->main_clk_rate_hz;
+		return gd->arch.main_clk_rate_hz;
 	case AT91_PMC_MCKR_CSS_PLLA:
-		return gd->plla_rate_hz;
+		return gd->arch.plla_rate_hz;
 	case AT91_PMC_MCKR_CSS_PLLB:
-		return gd->pllb_rate_hz;
+		return gd->arch.pllb_rate_hz;
 	}
 
 	return 0;
@@ -132,10 +132,10 @@ int at91_clock_init(unsigned long main_clock)
 		main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
 	}
 #endif
-	gd->main_clk_rate_hz = main_clock;
+	gd->arch.main_clk_rate_hz = main_clock;
 
 	/* report if PLLA is more than mildly overclocked */
-	gd->plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
+	gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
 
 #ifdef CONFIG_USB_ATMEL
 	/*
@@ -144,9 +144,10 @@ int at91_clock_init(unsigned long main_clock)
 	 *
 	 * REVISIT:  assumes MCK doesn't derive from PLLB!
 	 */
-	gd->at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
+	gd->arch.at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
 			     AT91_PMC_PLLBR_USBDIV_2;
-	gd->pllb_rate_hz = at91_pll_rate(main_clock, gd->at91_pllb_usb_init);
+	gd->arch.pllb_rate_hz = at91_pll_rate(main_clock,
+					      gd->arch.at91_pllb_usb_init);
 #endif
 
 	/*
@@ -157,15 +158,15 @@ int at91_clock_init(unsigned long main_clock)
 #if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \
 		|| defined(CONFIG_AT91SAM9X5)
 	/* plla divisor by 2 */
-	gd->plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
+	gd->arch.plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
 #endif
-	gd->mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
-	freq = gd->mck_rate_hz;
+	gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
+	freq = gd->arch.mck_rate_hz;
 
 	freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2));	/* prescale */
 #if defined(CONFIG_AT91SAM9G20)
 	/* mdiv ; (x >> 7) = ((x >> 8) * 2) */
-	gd->mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?
+	gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?
 		freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq;
 	if (mckr & AT91_PMC_MCKR_MDIV_MASK)
 		freq /= 2;			/* processor clock division */
@@ -177,14 +178,15 @@ int at91_clock_init(unsigned long main_clock)
 	 *  2   <==>   4
 	 *  3   <==>   3
 	 */
-	gd->mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ==
+	gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ==
 		(AT91_PMC_MCKR_MDIV_2 | AT91_PMC_MCKR_MDIV_4)
 		? freq / 3
 		: freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
 #else
-	gd->mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
+	gd->arch.mck_rate_hz = freq /
+			(1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
 #endif
-	gd->cpu_clk_rate_hz = freq;
+	gd->arch.cpu_clk_rate_hz = freq;
 
 	return 0;
 }

arch/arm/cpu/arm926ejs/at91/timer.c

@@ -52,14 +52,14 @@ DECLARE_GLOBAL_DATA_PTR;
 static inline unsigned long long tick_to_time(unsigned long long tick)
 {
 	tick *= CONFIG_SYS_HZ;
-	do_div(tick, gd->timer_rate_hz);
+	do_div(tick, gd->arch.timer_rate_hz);
 
 	return tick;
 }
 
 static inline unsigned long long usec_to_tick(unsigned long long usec)
 {
-	usec *= gd->timer_rate_hz;
+	usec *= gd->arch.timer_rate_hz;
 	do_div(usec, 1000000);
 
 	return usec;
@@ -79,8 +79,8 @@ int timer_init(void)
 	/* Enable PITC */
 	writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
 
-	gd->timer_rate_hz = gd->mck_rate_hz / 16;
-	gd->tbu = gd->tbl = 0;
+	gd->arch.timer_rate_hz = gd->arch.mck_rate_hz / 16;
+	gd->arch.tbu = gd->arch.tbl = 0;
 
 	return 0;
 }
@@ -95,10 +95,10 @@ unsigned long long get_ticks(void)
 	ulong now = readl(&pit->piir);
 
 	/* increment tbu if tbl has rolled over */
-	if (now < gd->tbl)
-		gd->tbu++;
-	gd->tbl = now;
-	return (((unsigned long long)gd->tbu) << 32) | gd->tbl;
+	if (now < gd->arch.tbl)
+		gd->arch.tbu++;
+	gd->arch.tbl = now;
+	return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
 }
 
 void __udelay(unsigned long usec)
@@ -132,5 +132,5 @@ ulong get_timer(ulong base)
  */
 ulong get_tbclk(void)
 {
-	return gd->timer_rate_hz;
+	return gd->arch.timer_rate_hz;
 }

arch/arm/cpu/arm926ejs/davinci/timer.c

@@ -60,8 +60,8 @@ int timer_init(void)
 	writel(0x0, &timer->tim34);
 	writel(TIMER_LOAD_VAL, &timer->prd34);
 	writel(2 << 22, &timer->tcr);
-	gd->timer_rate_hz = CONFIG_SYS_HZ_CLOCK / TIM_CLK_DIV;
-	gd->timer_reset_value = 0;
+	gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK / TIM_CLK_DIV;
+	gd->arch.timer_reset_value = 0;
 
 	return(0);
 }
@@ -74,27 +74,28 @@ unsigned long long get_ticks(void)
 	unsigned long now = readl(&timer->tim34);
 
 	/* increment tbu if tbl has rolled over */
-	if (now < gd->tbl)
-		gd->tbu++;
-	gd->tbl = now;
+	if (now < gd->arch.tbl)
+		gd->arch.tbu++;
+	gd->arch.tbl = now;
 
-	return (((unsigned long long)gd->tbu) << 32) | gd->tbl;
+	return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
 }
 
 ulong get_timer(ulong base)
 {
 	unsigned long long timer_diff;
 
-	timer_diff = get_ticks() - gd->timer_reset_value;
+	timer_diff = get_ticks() - gd->arch.timer_reset_value;
 
-	return lldiv(timer_diff, (gd->timer_rate_hz / CONFIG_SYS_HZ)) - base;
+	return lldiv(timer_diff,
+		     (gd->arch.timer_rate_hz / CONFIG_SYS_HZ)) - base;
 }
 
 void __udelay(unsigned long usec)
 {
 	unsigned long long endtime;
 
-	endtime = lldiv((unsigned long long)usec * gd->timer_rate_hz,
+	endtime = lldiv((unsigned long long)usec * gd->arch.timer_rate_hz,
 			1000000UL);
 	endtime += get_ticks();
 
@@ -108,7 +109,7 @@ void __udelay(unsigned long usec)
  */
 ulong get_tbclk(void)
 {
-	return gd->timer_rate_hz;
+	return gd->arch.timer_rate_hz;
 }
 
 #ifdef CONFIG_HW_WATCHDOG

arch/arm/cpu/arm926ejs/kirkwood/timer.c

@@ -86,8 +86,8 @@ struct kwtmr_registers *kwtmr_regs = (struct kwtmr_registers *)KW_TIMER_BASE;
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define timestamp gd->tbl
-#define lastdec gd->lastinc
+#define timestamp gd->arch.tbl
+#define lastdec gd->arch.lastinc
 
 ulong get_timer_masked(void)
 {

arch/arm/cpu/arm926ejs/mb86r0x/timer.c

@@ -35,8 +35,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define timestamp gd->tbl
-#define lastdec gd->lastinc
+#define timestamp gd->arch.tbl
+#define lastdec gd->arch.lastinc
 
 static inline unsigned long long tick_to_time(unsigned long long tick)
 {

arch/arm/cpu/arm926ejs/mx25/generic.c

@@ -229,9 +229,9 @@ int get_clocks(void)
 {
 #ifdef CONFIG_FSL_ESDHC
 #if CONFIG_SYS_FSL_ESDHC_ADDR == IMX_MMC_SDHC2_BASE
-	gd->sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 #else
-	gd->sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
+	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
 #endif
 #endif
 	return 0;

arch/arm/cpu/arm926ejs/mx25/timer.c

@@ -44,8 +44,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define timestamp	(gd->tbl)
-#define lastinc		(gd->lastinc)
+#define timestamp	(gd->arch.tbl)
+#define lastinc		(gd->arch.lastinc)
 
 /*
  * "time" is measured in 1 / CONFIG_SYS_HZ seconds,

arch/arm/cpu/arm926ejs/mx27/timer.c

@@ -45,8 +45,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define timestamp	(gd->tbl)
-#define lastinc		(gd->lastinc)
+#define timestamp	(gd->arch.tbl)
+#define lastinc		(gd->arch.lastinc)
 
 /*
  * "time" is measured in 1 / CONFIG_SYS_HZ seconds,

arch/arm/cpu/arm926ejs/mxs/timer.c

@@ -36,8 +36,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define timestamp (gd->tbl)
-#define lastdec (gd->lastinc)
+#define timestamp (gd->arch.tbl)
+#define lastdec (gd->arch.lastinc)
 
 /*
  * This driver uses 1kHz clock source.

arch/arm/cpu/arm926ejs/omap/timer.c

@@ -44,8 +44,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define timestamp gd->tbl
-#define lastdec gd->lastinc
+#define timestamp gd->arch.tbl
+#define lastdec gd->arch.lastinc
 
 int timer_init (void)
 {

arch/arm/cpu/arm926ejs/orion5x/timer.c

@@ -92,8 +92,8 @@ static inline ulong read_timer(void)
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define timestamp gd->tbl
-#define lastdec gd->lastinc
+#define timestamp gd->arch.tbl
+#define lastdec gd->arch.lastinc
 
 ulong get_timer_masked(void)
 {

arch/arm/cpu/arm926ejs/pantheon/timer.c

@@ -60,7 +60,7 @@ struct panthtmr_registers {
 #define	COUNT_RD_REQ		0x1
 
 DECLARE_GLOBAL_DATA_PTR;
-/* Using gd->tbu from timestamp and gd->tbl for lastdec */
+/* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */
 
 /*
  * For preventing risk of instability in reading counter value,
@@ -90,16 +90,16 @@ ulong get_timer_masked(void)
 {
 	ulong now = read_timer();
 
-	if (now >= gd->tbl) {
+	if (now >= gd->arch.tbl) {
 		/* normal mode */
-		gd->tbu += now - gd->tbl;
+		gd->arch.tbu += now - gd->arch.tbl;
 	} else {
 		/* we have an overflow ... */
-		gd->tbu += now + TIMER_LOAD_VAL - gd->tbl;
+		gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl;
 	}
-	gd->tbl = now;
+	gd->arch.tbl = now;
 
-	return gd->tbu;
+	return gd->arch.tbu;
 }
 
 ulong get_timer(ulong base)
@@ -144,9 +144,9 @@ int timer_init(void)
 
 	/* Enable timer 0 */
 	writel(0x1, &panthtimers->cer);
-	/* init the gd->tbu and gd->tbl value */
-	gd->tbl = read_timer();
-	gd->tbu = 0;
+	/* init the gd->arch.tbu and gd->arch.tbl value */
+	gd->arch.tbl = read_timer();
+	gd->arch.tbu = 0;
 
 	return 0;
 }

arch/arm/cpu/arm926ejs/spear/timer.c

@@ -38,8 +38,8 @@ static struct misc_regs *const misc_regs_p =
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define timestamp gd->tbl
-#define lastdec gd->lastinc
+#define timestamp gd->arch.tbl
+#define lastdec gd->arch.lastinc
 
 int timer_init(void)
 {

arch/arm/cpu/arm926ejs/versatile/timer.c

@@ -44,8 +44,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define timestamp gd->tbl
-#define lastdec gd->lastinc
+#define timestamp gd->arch.tbl
+#define lastdec gd->arch.lastinc
 
 #define TIMER_ENABLE	(1 << 7)
 #define TIMER_MODE_MSK	(1 << 6)

arch/arm/cpu/armv7/omap-common/timer.c

@@ -56,8 +56,9 @@ int timer_init(void)
 		&timer_base->tclr);
 
 	/* reset time, capture current incrementer value time */
-	gd->lastinc = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ);
-	gd->tbl = 0;		/* start "advancing" time stamp from 0 */
+	gd->arch.lastinc = readl(&timer_base->tcrr) /
+					(TIMER_CLOCK / CONFIG_SYS_HZ);
+	gd->arch.tbl = 0;	/* start "advancing" time stamp from 0 */
 
 	return 0;
 }
@@ -91,14 +92,15 @@ ulong get_timer_masked(void)
 	/* current tick value */
 	ulong now = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ);
 
-	if (now >= gd->lastinc)	/* normal mode (non roll) */
+	if (now >= gd->arch.lastinc) {	/* normal mode (non roll) */
 		/* move stamp fordward with absoulte diff ticks */
-		gd->tbl += (now - gd->lastinc);
-	else	/* we have rollover of incrementer */
-		gd->tbl += ((TIMER_LOAD_VAL / (TIMER_CLOCK / CONFIG_SYS_HZ))
-			     - gd->lastinc) + now;
-	gd->lastinc = now;
-	return gd->tbl;
+		gd->arch.tbl += (now - gd->arch.lastinc);
+	} else {	/* we have rollover of incrementer */
+		gd->arch.tbl += ((TIMER_LOAD_VAL / (TIMER_CLOCK /
+				CONFIG_SYS_HZ)) - gd->arch.lastinc) + now;
+	}
+	gd->arch.lastinc = now;
+	return gd->arch.tbl;
 }
 
 /*

arch/arm/cpu/armv7/s5p-common/timer.c

@@ -105,8 +105,8 @@ void reset_timer_masked(void)
 	struct s5p_timer *const timer = s5p_get_base_timer();
 
 	/* reset time */
-	gd->lastinc = readl(&timer->tcnto4);
-	gd->tbl = 0;
+	gd->arch.lastinc = readl(&timer->tcnto4);
+	gd->arch.tbl = 0;
 }
 
 unsigned long get_timer_masked(void)
@@ -123,14 +123,14 @@ unsigned long get_current_tick(void)
 	unsigned long now = readl(&timer->tcnto4);
 	unsigned long count_value = readl(&timer->tcntb4);
 
-	if (gd->lastinc >= now)
-		gd->tbl += gd->lastinc - now;
+	if (gd->arch.lastinc >= now)
+		gd->arch.tbl += gd->arch.lastinc - now;
 	else
-		gd->tbl += gd->lastinc + count_value - now;
+		gd->arch.tbl += gd->arch.lastinc + count_value - now;
 
-	gd->lastinc = now;
+	gd->arch.lastinc = now;
 
-	return gd->tbl;
+	return gd->arch.tbl;
 }
 
 /*

arch/arm/cpu/armv7/socfpga/timer.c

@@ -80,16 +80,16 @@ ulong get_timer_masked(void)
 {
 	/* current tick value */
 	ulong now = read_timer() / (CONFIG_TIMER_CLOCK_KHZ/CONFIG_SYS_HZ);
-	if (gd->lastinc >= now) {
+	if (gd->arch.lastinc >= now) {
 		/* normal mode (non roll) */
 		/* move stamp forward with absolute diff ticks */
-		gd->tbl += gd->lastinc - now;
+		gd->arch.tbl += gd->arch.lastinc - now;
 	} else {
 		/* we have overflow of the count down timer */
-		gd->tbl += TIMER_LOAD_VAL - gd->lastinc + now;
+		gd->arch.tbl += TIMER_LOAD_VAL - gd->arch.lastinc + now;
 	}
-	gd->lastinc = now;
-	return gd->tbl;
+	gd->arch.lastinc = now;
+	return gd->arch.tbl;
 }
 
 /*
@@ -98,7 +98,8 @@ ulong get_timer_masked(void)
 void reset_timer(void)
 {
 	/* capture current decrementer value time */
-	gd->lastinc = read_timer() / (CONFIG_TIMER_CLOCK_KHZ/CONFIG_SYS_HZ);
+	gd->arch.lastinc = read_timer() /
+				(CONFIG_TIMER_CLOCK_KHZ / CONFIG_SYS_HZ);
 	/* start "advancing" time stamp from 0 */
-	gd->tbl = 0;
+	gd->arch.tbl = 0;
 }

arch/arm/cpu/armv7/u8500/timer.c

@@ -100,12 +100,14 @@ ulong get_timer_masked(void)
 	/* current tick value */
 	ulong now = TICKS_TO_HZ(READ_TIMER());
 
-	if (now >= gd->lastinc)	/* normal (non rollover) */
-		gd->tbl += (now - gd->lastinc);
-	else			/* rollover */
-		gd->tbl += (TICKS_TO_HZ(TIMER_LOAD_VAL) - gd->lastinc) + now;
-	gd->lastinc = now;
-	return gd->tbl;
+	if (now >= gd->arch.lastinc) {	/* normal (non rollover) */
+		gd->arch.tbl += (now - gd->arch.lastinc);
+	} else {			/* rollover */
+		gd->arch.tbl += (TICKS_TO_HZ(TIMER_LOAD_VAL) -
+					gd->arch.lastinc) + now;
+	}
+	gd->arch.lastinc = now;
+	return gd->arch.tbl;
 }
 
 /* Delay x useconds */
@@ -132,7 +134,7 @@ ulong get_timer(ulong base)
 /*
  * Emulation of Power architecture long long timebase.
  *
- * TODO: Support gd->tbu for real long long timebase.
+ * TODO: Support gd->arch.tbu for real long long timebase.
  */
 unsigned long long get_ticks(void)
 {

arch/arm/cpu/armv7/zynq/timer.c

@@ -83,9 +83,9 @@ int timer_init(void)
 								emask);
 
 	/* Reset time */
-	gd->lastinc = readl(&timer_base->counter) /
+	gd->arch.lastinc = readl(&timer_base->counter) /
 					(TIMER_TICK_HZ / CONFIG_SYS_HZ);
-	gd->tbl = 0;
+	gd->arch.tbl = 0;
 
 	return 0;
 }
@@ -100,16 +100,16 @@ ulong get_timer_masked(void)
 
 	now = readl(&timer_base->counter) / (TIMER_TICK_HZ / CONFIG_SYS_HZ);
 
-	if (gd->lastinc >= now) {
+	if (gd->arch.lastinc >= now) {
 		/* Normal mode */
-		gd->tbl += gd->lastinc - now;
+		gd->arch.tbl += gd->arch.lastinc - now;
 	} else {
 		/* We have an overflow ... */
-		gd->tbl += gd->lastinc + TIMER_LOAD_VAL - now;
+		gd->arch.tbl += gd->arch.lastinc + TIMER_LOAD_VAL - now;
 	}
-	gd->lastinc = now;
+	gd->arch.lastinc = now;
 
-	return gd->tbl;
+	return gd->arch.tbl;
 }
 
 void __udelay(unsigned long usec)

arch/arm/cpu/ixp/timer.c

@@ -70,23 +70,23 @@ unsigned long long get_ticks(void)
 
 	if (readl(IXP425_OSST) & IXP425_OSST_TIMER_TS_PEND) {
 		/* rollover of timestamp timer register */
-		gd->timestamp += (0xFFFFFFFF - gd->lastinc) + now + 1;
+		gd->arch.timestamp += (0xFFFFFFFF - gd->arch.lastinc) + now + 1;
 		writel(IXP425_OSST_TIMER_TS_PEND, IXP425_OSST);
 	} else {
 		/* move stamp forward with absolut diff ticks */
-		gd->timestamp += (now - gd->lastinc);
+		gd->arch.timestamp += (now - gd->arch.lastinc);
 	}
-	gd->lastinc = now;
-	return gd->timestamp;
+	gd->arch.lastinc = now;
+	return gd->arch.timestamp;
 }
 
 
 void reset_timer_masked(void)
 {
 	/* capture current timestamp counter */
-	gd->lastinc = readl(IXP425_OSTS_B);
+	gd->arch.lastinc = readl(IXP425_OSTS_B);
 	/* start "advancing" time stamp from 0 */
-	gd->timestamp = 0;
+	gd->arch.timestamp = 0;
 }
 
 ulong get_timer_masked(void)

arch/arm/cpu/pxa/timer.c

@@ -31,8 +31,8 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define	TIMER_LOAD_VAL	0xffffffff
 
-#define	timestamp	(gd->tbl)
-#define	lastinc		(gd->lastinc)
+#define	timestamp	(gd->arch.tbl)
+#define	lastinc		(gd->arch.lastinc)
 
 #if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
 #define	TIMER_FREQ_HZ	3250000

arch/arm/cpu/tegra-common/timer.c

@@ -75,14 +75,14 @@ ulong get_timer_masked(void)
 	/* current tick value */
 	now = timer_get_us() / (TIMER_CLK / CONFIG_SYS_HZ);
 
-	if (now >= gd->lastinc)	/* normal mode (non roll) */
+	if (now >= gd->arch.lastinc)	/* normal mode (non roll) */
 		/* move stamp forward with absolute diff ticks */
-		gd->tbl += (now - gd->lastinc);
+		gd->arch.tbl += (now - gd->arch.lastinc);
 	else	/* we have rollover of incrementer */
-		gd->tbl += ((TIMER_LOAD_VAL / (TIMER_CLK / CONFIG_SYS_HZ))
-				- gd->lastinc) + now;
-	gd->lastinc = now;
-	return gd->tbl;
+		gd->arch.tbl += ((TIMER_LOAD_VAL / (TIMER_CLK / CONFIG_SYS_HZ))
+				- gd->arch.lastinc) + now;
+	gd->arch.lastinc = now;
+	return gd->arch.tbl;
 }
 
 /*

arch/arm/imx-common/speed.c

@@ -37,23 +37,23 @@ int get_clocks(void)
 #ifdef CONFIG_FSL_ESDHC
 #ifdef CONFIG_FSL_USDHC
 #if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
-	gd->sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 #elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
-	gd->sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 #elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC4_BASE_ADDR
-	gd->sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 #else
-	gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 #endif
 #else
 #if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
-	gd->sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 #elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
-	gd->sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 #elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC4_BASE_ADDR
-	gd->sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 #else
-	gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 #endif
 #endif
 #endif

arch/arm/imx-common/timer.c

@@ -48,8 +48,8 @@ static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR;
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define timestamp (gd->tbl)
-#define lastinc (gd->lastinc)
+#define timestamp (gd->arch.tbl)
+#define lastinc (gd->arch.lastinc)
 
 static inline unsigned long long tick_to_time(unsigned long long tick)
 {

arch/arm/include/asm/arch-at91/clk.h

@@ -31,37 +31,37 @@
 static inline unsigned long get_cpu_clk_rate(void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
-	return gd->cpu_clk_rate_hz;
+	return gd->arch.cpu_clk_rate_hz;
 }
 
 static inline unsigned long get_main_clk_rate(void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
-	return gd->main_clk_rate_hz;
+	return gd->arch.main_clk_rate_hz;
 }
 
 static inline unsigned long get_mck_clk_rate(void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
-	return gd->mck_rate_hz;
+	return gd->arch.mck_rate_hz;
 }
 
 static inline unsigned long get_plla_clk_rate(void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
-	return gd->plla_rate_hz;
+	return gd->arch.plla_rate_hz;
 }
 
 static inline unsigned long get_pllb_clk_rate(void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
-	return gd->pllb_rate_hz;
+	return gd->arch.pllb_rate_hz;
 }
 
 static inline u32 get_pllb_init(void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
-	return gd->at91_pllb_usb_init;
+	return gd->arch.at91_pllb_usb_init;
 }
 
 static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)

arch/arm/include/asm/global_data.h

@@ -23,27 +23,11 @@
 
 #ifndef	__ASM_GBL_DATA_H
 #define __ASM_GBL_DATA_H
-/*
- * The following data structure is placed in some memory which is
- * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
- * some locked parts of the data cache) to allow for a minimum set of
- * global variables during system initialization (until we have set
- * up the memory controller so that we can use RAM).
- */
 
-typedef	struct	global_data {
-	bd_t		*bd;
-	unsigned long	flags;
-	unsigned int	baudrate;
-	unsigned long	have_console;	/* serial_init() was called */
-#ifdef CONFIG_PRE_CONSOLE_BUFFER
-	unsigned long	precon_buf_idx;	/* Pre-Console buffer index */
-#endif
-	unsigned long	env_addr;	/* Address  of Environment struct */
-	unsigned long	env_valid;	/* Checksum of Environment valid? */
-	unsigned long	fb_base;	/* base address of frame buffer */
-#ifdef CONFIG_FSL_ESDHC
-	unsigned long	sdhc_clk;
+/* Architecture-specific global data */
+struct arch_global_data {
+#if defined(CONFIG_FSL_ESDHC)
+	u32 sdhc_clk;
 #endif
 #ifdef CONFIG_AT91FAMILY
 	/* "static data" needed by at91's clock.c */
@@ -54,38 +38,22 @@ typedef	struct	global_data {
 	unsigned long	pllb_rate_hz;
 	unsigned long	at91_pllb_usb_init;
 #endif
-#ifdef CONFIG_ARM
 	/* "static data" needed by most of timer.c on ARM platforms */
-	unsigned long	timer_rate_hz;
-	unsigned long	tbl;
-	unsigned long	tbu;
-	unsigned long long	timer_reset_value;
-	unsigned long	lastinc;
-#endif
+	unsigned long timer_rate_hz;
+	unsigned long tbu;
+	unsigned long tbl;
+	unsigned long lastinc;
+	unsigned long long timer_reset_value;
 #ifdef CONFIG_IXP425
-	unsigned long	timestamp;
+	unsigned long timestamp;
 #endif
-	unsigned long	relocaddr;	/* Start address of U-Boot in RAM */
-	phys_size_t	ram_size;	/* RAM size */
-	unsigned long	mon_len;	/* monitor len */
-	unsigned long	irq_sp;		/* irq stack pointer */
-	unsigned long	start_addr_sp;	/* start_addr_stackpointer */
-	unsigned long	reloc_off;
 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
-	unsigned long	tlb_addr;
-	unsigned long	tlb_size;
-#endif
-	const void	*fdt_blob;	/* Our device tree, NULL if none */
-	void		**jt;		/* jump table */
-	char		env_buf[32];	/* buffer for getenv() before reloc. */
-#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
-	unsigned long	post_log_word; /* Record POST activities */
-	unsigned long	post_log_res; /* success of POST test */
-	unsigned long	post_init_f_time; /* When post_init_f started */
+	unsigned long tlb_addr;
+	unsigned long tlb_size;
 #endif
-} gd_t;
+};
 
-#include <asm-generic/global_data_flags.h>
+#include <asm-generic/global_data.h>
 
 #define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("r8")
 

arch/arm/lib/board.c

@@ -355,14 +355,14 @@ void board_init_f(ulong bootflag)
 
 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
 	/* reserve TLB table */
-	gd->tlb_size = 4096 * 4;
-	addr -= gd->tlb_size;
+	gd->arch.tlb_size = 4096 * 4;
+	addr -= gd->arch.tlb_size;
 
 	/* round down to next 64 kB limit */
 	addr &= ~(0x10000 - 1);
 
-	gd->tlb_addr = addr;
-	debug("TLB table from %08lx to %08lx\n", addr, addr + gd->tlb_size);
+	gd->arch.tlb_addr = addr;
+	debug("TLB table from %08lx to %08lx\n", addr, addr + gd->arch.tlb_size);
 #endif
 
 	/* round down to next 4 kB limit */
@@ -488,7 +488,7 @@ static char *failed = "*** failed ***\n";
 static int should_load_env(void)
 {
 #ifdef CONFIG_OF_CONTROL
-	return fdtdec_get_config_int(gd->fdt_blob, "load-environment", 0);
+	return fdtdec_get_config_int(gd->fdt_blob, "load-environment", 1);
 #elif defined CONFIG_DELAY_ENVIRONMENT
 	return 0;
 #else

arch/arm/lib/cache-cp15.c

@@ -46,7 +46,7 @@ static void cp_delay (void)
 
 void set_section_dcache(int section, enum dcache_option option)
 {
-	u32 *page_table = (u32 *)gd->tlb_addr;
+	u32 *page_table = (u32 *)gd->arch.tlb_addr;
 	u32 value;
 
 	value = (section << MMU_SECTION_SHIFT) | (3 << 10);
@@ -65,7 +65,7 @@ void mmu_page_table_flush(unsigned long start, unsigned long stop)
 void mmu_set_region_dcache_behaviour(u32 start, int size,
 				     enum dcache_option option)
 {
-	u32 *page_table = (u32 *)gd->tlb_addr;
+	u32 *page_table = (u32 *)gd->arch.tlb_addr;
 	u32 upto, end;
 
 	end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
@@ -111,7 +111,7 @@ static inline void mmu_setup(void)
 
 	/* Copy the page table address to cp15 */
 	asm volatile("mcr p15, 0, %0, c2, c0, 0"
-		     : : "r" (gd->tlb_addr) : "memory");
+		     : : "r" (gd->arch.tlb_addr) : "memory");
 	/* Set the access control to all-supervisor */
 	asm volatile("mcr p15, 0, %0, c3, c0, 0"
 		     : : "r" (~0));

arch/avr32/cpu/cpu.c

@@ -47,7 +47,7 @@ int cpu_init(void)
 {
 	extern void _evba(void);
 
-	gd->cpu_hz = CONFIG_SYS_OSC0_HZ;
+	gd->arch.cpu_hz = CONFIG_SYS_OSC0_HZ;
 
 	/* TODO: Move somewhere else, but needs to be run before we
 	 * increase the clock frequency. */
@@ -59,7 +59,7 @@ int cpu_init(void)
 	clk_init();
 
 	/* Update the CPU speed according to the PLL configuration */
-	gd->cpu_hz = get_cpu_clk_rate();
+	gd->arch.cpu_hz = get_cpu_clk_rate();
 
 	/* Set up the exception handler table and enable exceptions */
 	sysreg_write(EVBA, (unsigned long)&_evba);

arch/avr32/cpu/exception.c

@@ -112,11 +112,11 @@ void do_unknown_exception(unsigned int ecr, struct pt_regs *regs)
 	printf("CPU Mode: %s\n", cpu_modes[mode]);
 
 	/* Avoid exception loops */
-	if (regs->sp < (gd->stack_end - CONFIG_STACKSIZE)
-			|| regs->sp >= gd->stack_end)
+	if (regs->sp < (gd->arch.stack_end - CONFIG_STACKSIZE)
+			|| regs->sp >= gd->arch.stack_end)
 		printf("\nStack pointer seems bogus, won't do stack dump\n");
 	else
-		dump_mem("\nStack: ", regs->sp, gd->stack_end);
+		dump_mem("\nStack: ", regs->sp, gd->arch.stack_end);
 
 	panic("Unhandled exception\n");
 }

arch/avr32/cpu/interrupts.c

@@ -46,7 +46,7 @@ static unsigned long tb_factor;
 
 unsigned long get_tbclk(void)
 {
-	return gd->cpu_hz;
+	return gd->arch.cpu_hz;
 }
 
 unsigned long long get_ticks(void)
@@ -115,8 +115,8 @@ int timer_init(void)
 	sysreg_write(COUNT, 0);
 
 	tmp = (u64)CONFIG_SYS_HZ << 32;
-	tmp += gd->cpu_hz / 2;
-	do_div(tmp, gd->cpu_hz);
+	tmp += gd->arch.cpu_hz / 2;
+	do_div(tmp, gd->arch.cpu_hz);
 	tb_factor = (u32)tmp;
 
 	if (set_interrupt_handler(0, &timer_interrupt_handler, 3))

arch/avr32/include/asm/global_data.h

@@ -22,35 +22,13 @@
 #ifndef __ASM_GLOBAL_DATA_H__
 #define __ASM_GLOBAL_DATA_H__
 
-/*
- * The following data structure is placed in some memory wich is
- * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
- * some locked parts of the data cache) to allow for a minimum set of
- * global variables during system initialization (until we have set
- * up the memory controller so that we can use RAM).
- */
-
-typedef	struct	global_data {
-	bd_t		*bd;
-	unsigned long	flags;
-	unsigned int	baudrate;
-	unsigned long	stack_end;	/* highest stack address */
-	unsigned long	have_console;	/* serial_init() was called */
-#ifdef CONFIG_PRE_CONSOLE_BUFFER
-	unsigned long	precon_buf_idx;	/* Pre-Console buffer index */
-#endif
-	unsigned long	reloc_off;	/* Relocation Offset */
-	unsigned long	env_addr;	/* Address of env struct */
-	unsigned long	env_valid;	/* Checksum of env valid? */
-	unsigned long	cpu_hz;		/* cpu core clock frequency */
-#if defined(CONFIG_LCD)
-	void		*fb_base;	/* framebuffer address */
-#endif
-	void		**jt;		/* jump table */
-	char		env_buf[32];	/* buffer for getenv() before reloc. */
-} gd_t;
+/* Architecture-specific global data */
+struct arch_global_data {
+	unsigned long stack_end;	/* highest stack address */
+	unsigned long cpu_hz;		/* cpu core clock frequency */
+};
 
-#include <asm-generic/global_data_flags.h>
+#include <asm-generic/global_data.h>
 
 #define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm("r5")
 

arch/avr32/lib/board.c

@@ -231,7 +231,7 @@ void board_init_f(ulong board_type)
 
 	/* And finally, a new, bigger stack. */
 	new_sp = (unsigned long *)addr;
-	gd->stack_end = addr;
+	gd->arch.stack_end = addr;
 	*(--new_sp) = 0;
 	*(--new_sp) = 0;
 

arch/avr32/lib/bootm.c

@@ -109,7 +109,7 @@ static struct tag *setup_clock_tags(struct tag *params)
 	params->hdr.size = tag_size(tag_clock);
 	params->u.clock.clock_id = ACLOCK_BOOTCPU;
 	params->u.clock.clock_flags = 0;
-	params->u.clock.clock_hz = gd->cpu_hz;
+	params->u.clock.clock_hz = gd->arch.cpu_hz;
 
 #ifdef CONFIG_AT32AP7000
 	/*

arch/blackfin/include/asm/global_data.h

@@ -30,36 +30,11 @@
 
 #include <asm/u-boot.h>
 
-/*
- * The following data structure is placed in some memory wich is
- * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
- * some locked parts of the data cache) to allow for a minimum set of
- * global variables during system initialization (until we have set
- * up the memory controller so that we can use RAM).
- */
-typedef struct global_data {
-	bd_t *bd;
-	unsigned long flags;
-	unsigned long board_type;
-	unsigned int baudrate;
-	unsigned long have_console;	/* serial_init() was called */
-#ifdef CONFIG_PRE_CONSOLE_BUFFER
-	unsigned long	precon_buf_idx;	/* Pre-Console buffer index */
-#endif
-	phys_size_t ram_size;		/* RAM size */
-	unsigned long env_addr;	/* Address  of Environment struct */
-	unsigned long env_valid;	/* Checksum of Environment valid? */
-#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
-	unsigned long post_log_word;	/* Record POST activities */
-	unsigned long post_log_res; 	/* success of POST test */
-	unsigned long post_init_f_time;	/* When post_init_f started */
-#endif
-
-	void	**jt;			/* jump table */
-	char	env_buf[32];		/* buffer for getenv() before reloc. */
-} gd_t;
+/* Architecture-specific global data */
+struct arch_global_data {
+};
 
-#include <asm-generic/global_data_flags.h>
+#include <asm-generic/global_data.h>
 
 #define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("P3")
 

arch/m68k/cpu/mcf5227x/cpu.c

@@ -68,10 +68,10 @@ int checkcpu(void)
 		printf("       CPU CLK %s MHz BUS CLK %s MHz FLB CLK %s MHz\n",
 		       strmhz(buf1, gd->cpu_clk),
 		       strmhz(buf2, gd->bus_clk),
-		       strmhz(buf3, gd->flb_clk));
+		       strmhz(buf3, gd->arch.flb_clk));
 		printf("       INP CLK %s MHz VCO CLK %s MHz\n",
-		       strmhz(buf1, gd->inp_clk),
-		       strmhz(buf2, gd->vco_clk));
+		       strmhz(buf1, gd->arch.inp_clk),
+		       strmhz(buf2, gd->arch.vco_clk));
 	}
 
 	return 0;

arch/m68k/cpu/mcf5227x/speed.c

@@ -114,28 +114,28 @@ int get_clocks(void)
 			    ((in_be32(&pll->pcr) & 0xFF000000) >> 24) *
 			    CONFIG_SYS_INPUT_CLKSRC;
 		}
-		gd->vco_clk = vco;	/* Vco clock */
+		gd->arch.vco_clk = vco;	/* Vco clock */
 	} else if (bootmode == 3) {
 		/* serial mode */
 		vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
-		gd->vco_clk = vco;	/* Vco clock */
+		gd->arch.vco_clk = vco;	/* Vco clock */
 	}
 
 	if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
 		/* Limp mode */
 	} else {
-		gd->inp_clk = CONFIG_SYS_INPUT_CLKSRC;	/* Input clock */
+		gd->arch.inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
 
 		temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1;
 		gd->cpu_clk = vco / temp;	/* cpu clock */
 
 		temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
-		gd->flb_clk = vco / temp;	/* flexbus clock */
-		gd->bus_clk = gd->flb_clk;
+		gd->arch.flb_clk = vco / temp;	/* flexbus clock */
+		gd->bus_clk = gd->arch.flb_clk;
 	}
 
 #ifdef CONFIG_FSL_I2C
-	gd->i2c1_clk = gd->bus_clk;
+	gd->arch.i2c1_clk = gd->bus_clk;
 #endif
 
 	return (0);

arch/m68k/cpu/mcf523x/speed.c

@@ -48,7 +48,7 @@ int get_clocks(void)
 	gd->cpu_clk = (gd->bus_clk * 2);
 
 #ifdef CONFIG_FSL_I2C
-	gd->i2c1_clk = gd->bus_clk;
+	gd->arch.i2c1_clk = gd->bus_clk;
 #endif
 
 	return (0);

arch/m68k/cpu/mcf52x2/speed.c

@@ -91,9 +91,9 @@ int get_clocks (void)
 #endif
 
 #ifdef CONFIG_FSL_I2C
-	gd->i2c1_clk = gd->bus_clk;
+	gd->arch.i2c1_clk = gd->bus_clk;
 #ifdef CONFIG_SYS_I2C2_OFFSET
-	gd->i2c2_clk = gd->bus_clk;
+	gd->arch.i2c2_clk = gd->bus_clk;
 #endif
 #endif
 

arch/m68k/cpu/mcf532x/speed.c

@@ -271,7 +271,7 @@ int get_clocks(void)
 	gd->cpu_clk = (gd->bus_clk * 3);
 
 #ifdef CONFIG_FSL_I2C
-	gd->i2c1_clk = gd->bus_clk;
+	gd->arch.i2c1_clk = gd->bus_clk;
 #endif
 
 	return (0);

arch/m68k/cpu/mcf5445x/cpu.c

@@ -101,16 +101,16 @@ int checkcpu(void)
 		printf("       CPU CLK %s MHz BUS CLK %s MHz FLB CLK %s MHz\n",
 		       strmhz(buf1, gd->cpu_clk),
 		       strmhz(buf2, gd->bus_clk),
-		       strmhz(buf3, gd->flb_clk));
+		       strmhz(buf3, gd->arch.flb_clk));
 #ifdef CONFIG_PCI
 		printf("       PCI CLK %s MHz INP CLK %s MHz VCO CLK %s MHz\n",
 		       strmhz(buf1, gd->pci_clk),
-		       strmhz(buf2, gd->inp_clk),
-		       strmhz(buf3, gd->vco_clk));
+		       strmhz(buf2, gd->arch.inp_clk),
+		       strmhz(buf3, gd->arch.vco_clk));
 #else
 		printf("       INP CLK %s MHz VCO CLK %s MHz\n",
-		       strmhz(buf1, gd->inp_clk),
-		       strmhz(buf2, gd->vco_clk));
+		       strmhz(buf1, gd->arch.inp_clk),
+		       strmhz(buf2, gd->arch.vco_clk));
 #endif
 	}
 

arch/m68k/cpu/mcf5445x/speed.c

@@ -233,7 +233,7 @@ void setup_5445x_clocks(void)
 
 			out_be32(&pll->pcr, pcrvalue);
 		}
-		gd->vco_clk = vco;	/* Vco clock */
+		gd->arch.vco_clk = vco;	/* Vco clock */
 	} else if (bootmode == 2) {
 		/* Normal mode */
 		vco =  ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
@@ -244,17 +244,17 @@ void setup_5445x_clocks(void)
 			out_be32(&pll->pcr, pcrvalue);
 			vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
 		}
-		gd->vco_clk = vco;	/* Vco clock */
+		gd->arch.vco_clk = vco;	/* Vco clock */
 	} else if (bootmode == 3) {
 		/* serial mode */
 		vco =  ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
-		gd->vco_clk = vco;	/* Vco clock */
+		gd->arch.vco_clk = vco;	/* Vco clock */
 	}
 
 	if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
 		/* Limp mode */
 	} else {
-		gd->inp_clk = CONFIG_SYS_INPUT_CLKSRC;	/* Input clock */
+		gd->arch.inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
 
 		temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1;
 		gd->cpu_clk = vco / temp;	/* cpu clock */
@@ -263,7 +263,7 @@ void setup_5445x_clocks(void)
 		gd->bus_clk = vco / temp;	/* bus clock */
 
 		temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV3_MASK) >> 8) + 1;
-		gd->flb_clk = vco / temp;	/* FlexBus clock */
+		gd->arch.flb_clk = vco / temp;	/* FlexBus clock */
 
 #ifdef CONFIG_PCI
 		if (bPci) {
@@ -274,7 +274,7 @@ void setup_5445x_clocks(void)
 	}
 
 #ifdef CONFIG_FSL_I2C
-	gd->i2c1_clk = gd->bus_clk;
+	gd->arch.i2c1_clk = gd->bus_clk;
 #endif
 }
 #endif
@@ -290,7 +290,7 @@ int get_clocks(void)
 #endif
 
 #ifdef CONFIG_FSL_I2C
-	gd->i2c1_clk = gd->bus_clk;
+	gd->arch.i2c1_clk = gd->bus_clk;
 #endif
 
 	return (0);

arch/m68k/cpu/mcf547x_8x/speed.c

@@ -41,7 +41,7 @@ int get_clocks(void)
 	gd->cpu_clk = (gd->bus_clk * 2);
 
 #ifdef CONFIG_FSL_I2C
-	gd->i2c1_clk = gd->bus_clk;
+	gd->arch.i2c1_clk = gd->bus_clk;
 #endif
 
 	return (0);

arch/m68k/include/asm/global_data.h

@@ -23,52 +23,21 @@
 
 #ifndef	__ASM_GBL_DATA_H
 #define __ASM_GBL_DATA_H
-/*
- * The following data structure is placed in some memory wich is
- * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
- * some locked parts of the data cache) to allow for a minimum set of
- * global variables during system initialization (until we have set
- * up the memory controller so that we can use RAM).
- */
 
-typedef	struct	global_data {
-	bd_t		*bd;
-	unsigned long	flags;
-	unsigned int	baudrate;
-	unsigned long	cpu_clk;	/* CPU clock in Hz!		*/
-	unsigned long	bus_clk;
-#ifdef CONFIG_PCI
-	unsigned long	pci_clk;
-#endif
-#ifdef CONFIG_EXTRA_CLOCK
-	unsigned long	inp_clk;
-	unsigned long	vco_clk;
-	unsigned long	flb_clk;
-#endif
+/* Architecture-specific global data */
+struct arch_global_data {
 #ifdef CONFIG_FSL_I2C
 	unsigned long	i2c1_clk;
 	unsigned long	i2c2_clk;
 #endif
-	phys_size_t	ram_size;	/* RAM size */
-	unsigned long	reloc_off;	/* Relocation Offset */
-	unsigned long	reset_status;	/* reset status register at boot	*/
-	unsigned long	env_addr;	/* Address  of Environment struct	*/
-	unsigned long	env_valid;	/* Checksum of Environment valid?	*/
-	unsigned long	have_console;	/* serial_init() was called		*/
-#ifdef CONFIG_PRE_CONSOLE_BUFFER
-	unsigned long	precon_buf_idx;	/* Pre-Console buffer index */
-#endif
-#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO)
-	unsigned long	fb_base;	/* Base addr of framebuffer memory */
-#endif
-#ifdef CONFIG_BOARD_TYPES
-	unsigned long	board_type;
+#ifdef CONFIG_EXTRA_CLOCK
+	unsigned long inp_clk;
+	unsigned long vco_clk;
+	unsigned long flb_clk;
 #endif
-	void		**jt;		/* Standalone app jump table */
-	char		env_buf[32];	/* buffer for getenv() before reloc. */
-} gd_t;
+};
 
-#include <asm-generic/global_data_flags.h>
+#include <asm-generic/global_data.h>
 
 #if 0
 extern gd_t *global_data;

arch/m68k/lib/board.c

@@ -349,9 +349,9 @@ board_init_f (ulong bootflag)
 	bd->bi_pcifreq = gd->pci_clk;		/* PCI Freq in Hz */
 #endif
 #ifdef CONFIG_EXTRA_CLOCK
-	bd->bi_inpfreq = gd->inp_clk;		/* input Freq in Hz */
-	bd->bi_vcofreq = gd->vco_clk;		/* vco Freq in Hz */
-	bd->bi_flbfreq = gd->flb_clk;		/* flexbus Freq in Hz */
+	bd->bi_inpfreq = gd->arch.inp_clk;		/* input Freq in Hz */
+	bd->bi_vcofreq = gd->arch.vco_clk;		/* vco Freq in Hz */
+	bd->bi_flbfreq = gd->arch.flb_clk;		/* flexbus Freq in Hz */
 #endif
 	bd->bi_baudrate = gd->baudrate;	/* Console Baudrate     */
 

arch/microblaze/include/asm/global_data.h

@@ -24,31 +24,12 @@
 
 #ifndef	__ASM_GBL_DATA_H
 #define __ASM_GBL_DATA_H
-/*
- * The following data structure is placed in some memory wich is
- * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
- * some locked parts of the data cache) to allow for a minimum set of
- * global variables during system initialization (until we have set
- * up the memory controller so that we can use RAM).
- */
 
-typedef	struct	global_data {
-	bd_t		*bd;
-	unsigned long	flags;
-	unsigned int	baudrate;
-	unsigned long	have_console;	/* serial_init() was called */
-#ifdef CONFIG_PRE_CONSOLE_BUFFER
-	unsigned long	precon_buf_idx;	/* Pre-Console buffer index */
-#endif
-	unsigned long	env_addr;	/* Address  of Environment struct */
-	const void	*fdt_blob;	/* Our device tree, NULL if none */
-	unsigned long	env_valid;	/* Checksum of Environment valid? */
-	unsigned long	fb_base;	/* base address of frame buffer */
-	void		**jt;		/* jump table */
-	char		env_buf[32];	/* buffer for getenv() before reloc. */
-} gd_t;
+/* Architecture-specific global data */
+struct arch_global_data {
+};
 
-#include <asm-generic/global_data_flags.h>
+#include <asm-generic/global_data.h>
 
 #define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("r31")
 

arch/microblaze/lib/Makefile

@@ -29,6 +29,7 @@ SOBJS-y	+=
 
 COBJS-y	+= board.o
 COBJS-y	+= bootm.o
+COBJS-y	+= muldi3.o
 
 SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))

arch/microblaze/lib/muldi3.c

@@ -0,0 +1,91 @@
+/*
+ * U-boot - muldi3.c contains routines for mult and div
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* Generic function got from GNU gcc package, libgcc2.c */
+#ifndef SI_TYPE_SIZE
+#define SI_TYPE_SIZE 32
+#endif
+#define __ll_B (1L << (SI_TYPE_SIZE / 2))
+#define __ll_lowpart(t) ((USItype) (t) % __ll_B)
+#define __ll_highpart(t) ((USItype) (t) / __ll_B)
+#define BITS_PER_UNIT 8
+
+#if !defined(umul_ppmm)
+#define umul_ppmm(w1, w0, u, v)						\
+	do {								\
+	USItype __x0, __x1, __x2, __x3;					\
+	USItype __ul, __vl, __uh, __vh;					\
+									\
+		__ul = __ll_lowpart(u);					\
+		__uh = __ll_highpart(u);				\
+		__vl = __ll_lowpart(v);					\
+		__vh = __ll_highpart(v);				\
+									\
+	__x0 = (USItype) __ul * __vl;					\
+	__x1 = (USItype) __ul * __vh;					\
+	__x2 = (USItype) __uh * __vl;					\
+	__x3 = (USItype) __uh * __vh;					\
+									\
+		__x1 += __ll_highpart(__x0); /* this can't give carry */\
+		__x1 += __x2; /* but this indeed can */			\
+		if (__x1 < __x2) /* did we get it? */			\
+		__x3 += __ll_B;	/* yes, add it in the proper pos. */	\
+									\
+		(w1) = __x3 + __ll_highpart(__x1);			\
+		(w0) = __ll_lowpart(__x1) * __ll_B + __ll_lowpart(__x0);\
+	} while (0)
+#endif
+
+#if !defined(__umulsidi3)
+#define __umulsidi3(u, v)						\
+	({DIunion __w;							\
+	umul_ppmm(__w.s.high, __w.s.low, u, v);		\
+	__w.ll; })
+#endif
+
+typedef unsigned int USItype __attribute__ ((mode(SI)));
+typedef int SItype __attribute__ ((mode(SI)));
+typedef int DItype __attribute__ ((mode(DI)));
+typedef int word_type __attribute__ ((mode(__word__)));
+
+struct DIstruct {
+	SItype low, high;
+};
+typedef union {
+	struct DIstruct s;
+	DItype ll;
+} DIunion;
+
+DItype __muldi3(DItype u, DItype v)
+{
+	DIunion w;
+	DIunion uu, vv;
+
+	uu.ll = u, vv.ll = v;
+	/*  panic("kernel panic for __muldi3"); */
+	w.ll = __umulsidi3(uu.s.low, vv.s.low);
+	w.s.high += ((USItype) uu.s.low * (USItype) vv.s.high
+		     + (USItype) uu.s.high * (USItype) vv.s.low);
+
+	return w.ll;
+}

arch/mips/cpu/mips32/config.mk

@@ -30,5 +30,11 @@
 MIPSFLAGS := -march=mips32r2
 
 PLATFORM_CPPFLAGS += $(MIPSFLAGS)
+PLATFORM_CPPFLAGS += -mabi=32 -DCONFIG_32BIT
+ifdef CONFIG_SYS_BIG_ENDIAN
+PLATFORM_LDFLAGS  += -m elf32btsmip
+else
+PLATFORM_LDFLAGS  += -m elf32ltsmip
+endif
 
 CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T mips.lds

arch/mips/cpu/mips32/start.S

@@ -258,8 +258,7 @@ reset:
 #endif
 
 	/* Set up temporary stack */
-	li	t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
-	la	sp, 0(t0)
+	li	sp, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
 
 	la	t9, board_init_f
 	jr	t9
@@ -280,55 +279,41 @@ reset:
 relocate_code:
 	move	sp, a0			# set new stack pointer
 
+	move	s0, a1			# save gd in s0
+	move	s2, a2			# save destination address in s2
+
 	li	t0, CONFIG_SYS_MONITOR_BASE
+	sub	s1, s2, t0		# s1 <-- relocation offset
+
 	la	t3, in_ram
 	lw	t2, -12(t3)		# t2 <-- uboot_end_data
 	move	t1, a2
-	move	s2, a2			# s2 <-- destination address
 
-	/*
-	 * Fix $gp:
-	 *
-	 * New $gp = (Old $gp - CONFIG_SYS_MONITOR_BASE) + Destination Address
-	 */
-	move	t6, gp
-	sub	gp, CONFIG_SYS_MONITOR_BASE
-	add	gp, a2			# gp now adjusted
-	sub	s1, gp, t6		# s1 <-- relocation offset
+	add	gp, s1			# adjust gp
 
 	/*
 	 * t0 = source address
 	 * t1 = target address
 	 * t2 = source end address
 	 */
-
-	/*
-	 * Save destination address and size for later usage in flush_cache()
-	 */
-	move	s0, a1			# save gd in s0
-	move	a0, t1			# a0 <-- destination addr
-	sub	a1, t2, t0		# a1 <-- size
-
 1:
 	lw	t3, 0(t0)
 	sw	t3, 0(t1)
 	addu	t0, 4
-	ble	t0, t2, 1b
+	blt	t0, t2, 1b
 	 addu	t1, 4
 
 	/* If caches were enabled, we would have to flush them here. */
-
-	/* a0 & a1 are already set up for flush_cache(start, size) */
+	sub	a1, t1, s2		# a1 <-- size
 	la	t9, flush_cache
 	jalr	t9
-	 nop
+	 move	a0, s2			# a0 <-- destination address
 
 	/* Jump to where we've relocated ourselves */
 	addi	t0, s2, in_ram - _start
 	jr	t0
 	 nop
 
-	.word	_gp
 	.word	_GLOBAL_OFFSET_TABLE_
 	.word	uboot_end_data
 	.word	uboot_end
@@ -343,9 +328,7 @@ in_ram:
 	 */
 	lw	t3, -4(t0)		# t3 <-- num_got_entries
 	lw	t4, -16(t0)		# t4 <-- _GLOBAL_OFFSET_TABLE_
-	lw	t5, -20(t0)		# t5 <-- _gp
-	sub	t4, t5			# compute offset
-	add	t4, t4, gp		# t4 now holds relocated _G_O_T_
+	add	t4, s1			# t4 now holds relocated _G_O_T_
 	addi	t4, t4, 8		# skipping first two entries
 	li	t2, 2
 1:
@@ -380,6 +363,8 @@ in_ram:
 	/* Exception handlers */
 romReserved:
 	b	romReserved
+	 nop
 
 romExcHandle:
 	b	romExcHandle
+	 nop

arch/mips/cpu/mips64/start.S

@@ -137,8 +137,7 @@ reset:
 #endif
 
 	/* Set up temporary stack */
-	dli	t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
-	dla	sp, 0(t0)
+	dli	sp, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
 
 	dla	t9, board_init_f
 	jr	t9
@@ -159,55 +158,41 @@ reset:
 relocate_code:
 	move	sp, a0			# set new stack pointer
 
+	move	s0, a1			# save gd in s0
+	move	s2, a2			# save destination address in s2
+
 	dli	t0, CONFIG_SYS_MONITOR_BASE
+	dsub	s1, s2, t0		# s1 <-- relocation offset
+
 	dla	t3, in_ram
 	ld	t2, -24(t3)		# t2 <-- uboot_end_data
 	move	t1, a2
-	move	s2, a2			# s2 <-- destination address
 
-	/*
-	 * Fix $gp:
-	 *
-	 * New $gp = (Old $gp - CONFIG_SYS_MONITOR_BASE) + Destination Address
-	 */
-	move	t8, gp
-	dsub	gp, CONFIG_SYS_MONITOR_BASE
-	dadd	gp, a2			# gp now adjusted
-	dsub	s1, gp, t8		# s1 <-- relocation offset
+	dadd	gp, s1			# adjust gp
 
 	/*
 	 * t0 = source address
 	 * t1 = target address
 	 * t2 = source end address
 	 */
-
-	/*
-	 * Save destination address and size for dlater usage in flush_cache()
-	 */
-	move	s0, a1			# save gd in s0
-	move	a0, t1			# a0 <-- destination addr
-	dsub	a1, t2, t0		# a1 <-- size
-
 1:
 	lw	t3, 0(t0)
 	sw	t3, 0(t1)
 	daddu	t0, 4
-	ble	t0, t2, 1b
+	blt	t0, t2, 1b
 	 daddu	t1, 4
 
 	/* If caches were enabled, we would have to flush them here. */
-
-	/* a0 & a1 are already set up for flush_cache(start, size) */
+	dsub	a1, t1, s2		# a1 <-- size
 	dla	t9, flush_cache
 	jalr	t9
-	 nop
+	 move	a0, s2			# a0 <-- destination address
 
 	/* Jump to where we've relocated ourselves */
 	daddi	t0, s2, in_ram - _start
 	jr	t0
 	 nop
 
-	.dword	_gp
 	.dword	_GLOBAL_OFFSET_TABLE_
 	.dword	uboot_end_data
 	.dword	uboot_end
@@ -222,9 +207,7 @@ in_ram:
 	 */
 	ld	t3, -8(t0)		# t3 <-- num_got_entries
 	ld	t8, -32(t0)		# t8 <-- _GLOBAL_OFFSET_TABLE_
-	ld	t9, -40(t0)		# t9 <-- _gp
-	dsub	t8, t9			# compute offset
-	dadd	t8, t8, gp		# t8 now holds relocated _G_O_T_
+	dadd	t8, s1			# t8 now holds relocated _G_O_T_
 	daddi	t8, t8, 16		# skipping first two entries
 	dli	t2, 2
 1:
@@ -259,3 +242,4 @@ in_ram:
 	/* Exception handlers */
 romReserved:
 	b	romReserved
+	 nop

board/micronas/vct/u-boot.lds → arch/mips/cpu/u-boot.lds

@@ -21,7 +21,12 @@
  * MA 02111-1307 USA
  */
 
-OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
+#if defined(CONFIG_64BIT)
+#define PTR_COUNT_SHIFT	3
+#else
+#define PTR_COUNT_SHIFT	2
+#endif
+
 OUTPUT_ARCH(mips)
 ENTRY(_start)
 SECTIONS
@@ -29,41 +34,51 @@ SECTIONS
 	. = 0x00000000;
 
 	. = ALIGN(4);
-	.text       :
-	{
-	  *(.text*)
+	.text : {
+		*(.text*)
 	}
 
 	. = ALIGN(4);
-	.rodata  : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+	.rodata : {
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+	}
 
 	. = ALIGN(4);
-	.data  : { *(.data*) }
+	.data : {
+		*(.data*)
+	}
 
 	. = .;
 	_gp = ALIGN(16) + 0x7ff0;
 
 	.got : {
-	  __got_start = .;
-	  *(.got)
-	  __got_end = .;
+		__got_start = .;
+		*(.got)
+		__got_end = .;
 	}
 
 	. = ALIGN(4);
-	.sdata  : { *(.sdata*) }
+	.sdata : {
+		*(.sdata*)
+	}
 
 	. = ALIGN(4);
 	.u_boot_list : {
 		#include <u-boot.lst>
 	}
 
-	. = ALIGN(4);
 	uboot_end_data = .;
-	num_got_entries = (__got_end - __got_start) >> 2;
+
+	num_got_entries = (__got_end - __got_start) >> PTR_COUNT_SHIFT;
 
 	. = ALIGN(4);
-	.sbss (NOLOAD)  : { *(.sbss*) }
-	. = ALIGN(4);
-	.bss (NOLOAD)  : { *(.bss*) }
+	.sbss : {
+		*(.sbss*)
+	}
+
+	.bss : {
+		*(.bss*)
+		. = ALIGN(4);
+	}
 	uboot_end = .;
 }

arch/mips/cpu/xburst/config.mk

@@ -21,5 +21,11 @@
 #
 
 PLATFORM_CPPFLAGS += -march=mips32
+PLATFORM_CPPFLAGS += -mabi=32 -DCONFIG_32BIT
+ifdef CONFIG_SYS_BIG_ENDIAN
+PLATFORM_LDFLAGS  += -m elf32btsmip
+else
+PLATFORM_LDFLAGS  += -m elf32ltsmip
+endif
 
 CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T mips.lds

arch/mips/cpu/xburst/start.S

@@ -64,19 +64,13 @@ relocate_code:
 	move	sp, a0			# set new stack pointer
 
 	li	t0, CONFIG_SYS_MONITOR_BASE
+	sub	t6, a2, t0		# t6 <-- relocation offset
+
 	la	t3, in_ram
 	lw	t2, -12(t3)		# t2 <-- uboot_end_data
 	move	t1, a2
 
-	/*
-	 * Fix $gp:
-	 *
-	 * New $gp = (Old $gp - CONFIG_SYS_MONITOR_BASE) + Destination Address
-	 */
-	move	t6, gp
-	sub	gp, CONFIG_SYS_MONITOR_BASE
-	add	gp, a2			# gp now adjusted
-	sub	t6, gp, t6		# t6 <-- relocation offset
+	add	gp, t6			# adjust gp
 
 	/*
 	 * t0 = source address
@@ -87,7 +81,7 @@ relocate_code:
 	lw	t3, 0(t0)
 	sw	t3, 0(t1)
 	addu	t0, 4
-	ble	t0, t2, 1b
+	blt	t0, t2, 1b
 	 addu	t1, 4
 
 	/* If caches were enabled, we would have to flush them here. */
@@ -122,7 +116,6 @@ relocate_code:
 	jr	t0
 	 nop
 
-	.word	_gp
 	.word	_GLOBAL_OFFSET_TABLE_
 	.word	uboot_end_data
 	.word	uboot_end
@@ -137,9 +130,7 @@ in_ram:
 	 */
 	lw	t3, -4(t0)		# t3 <-- num_got_entries
 	lw	t4, -16(t0)		# t4 <-- _GLOBAL_OFFSET_TABLE_
-	lw	t5, -20(t0)		# t5 <-- _gp
-	sub	t4, t5			# compute offset
-	add	t4, t4, gp		# t4 now holds relocated _G_O_T_
+	add	t4, t6			# t4 now holds relocated _G_O_T_
 	addi	t4, t4, 8		# skipping first two entries
 	li	t2, 2
 1:

arch/mips/cpu/xburst/timer.c

@@ -34,24 +34,24 @@ static struct jz4740_tcu *tcu = (struct jz4740_tcu *)JZ4740_TCU_BASE;
 void reset_timer_masked(void)
 {
 	/* reset time */
-	gd->lastinc = readl(&tcu->tcnt0);
-	gd->tbl = 0;
+	gd->arch.lastinc = readl(&tcu->tcnt0);
+	gd->arch.tbl = 0;
 }
 
 ulong get_timer_masked(void)
 {
 	ulong now = readl(&tcu->tcnt0);
 
-	if (gd->lastinc <= now)
-		gd->tbl += now - gd->lastinc; /* normal mode */
+	if (gd->arch.lastinc <= now)
+		gd->arch.tbl += now - gd->arch.lastinc; /* normal mode */
 	else {
 		/* we have an overflow ... */
-		gd->tbl += TIMER_FDATA + now - gd->lastinc;
+		gd->arch.tbl += TIMER_FDATA + now - gd->arch.lastinc;
 	}
 
-	gd->lastinc = now;
+	gd->arch.lastinc = now;
 
-	return gd->tbl;
+	return gd->arch.tbl;
 }
 
 void udelay_masked(unsigned long usec)
@@ -94,8 +94,8 @@ int timer_init(void)
 	writel(1 << TIMER_CHAN, &tcu->tscr); /* enable timer clock */
 	writeb(1 << TIMER_CHAN, &tcu->tesr); /* start counting up */
 
-	gd->lastinc = 0;
-	gd->tbl = 0;
+	gd->arch.lastinc = 0;
+	gd->arch.tbl = 0;
 
 	return 0;
 }
@@ -112,7 +112,7 @@ ulong get_timer(ulong base)
 
 void set_timer(ulong t)
 {
-	gd->tbl = t;
+	gd->arch.tbl = t;
 }
 
 void __udelay(unsigned long usec)

arch/mips/include/asm/global_data.h

@@ -26,42 +26,16 @@
 
 #include <asm/regdef.h>
 
-/*
- * The following data structure is placed in some memory wich is
- * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
- * some locked parts of the data cache) to allow for a minimum set of
- * global variables during system initialization (until we have set
- * up the memory controller so that we can use RAM).
- */
-
-typedef	struct	global_data {
-	bd_t		*bd;
-	unsigned long	flags;
+/* Architecture-specific global data */
+struct arch_global_data {
 #ifdef CONFIG_JZSOC
 	/* There are other clocks in the jz4740 */
-	unsigned long	cpu_clk;	/* CPU core clock */
-	unsigned long	sys_clk;	/* System bus clock */
-	unsigned long	per_clk;	/* Peripheral bus clock */
-	unsigned long	mem_clk;	/* Memory bus clock */
-	unsigned long	dev_clk;	/* Device clock */
-	/* "static data" needed by most of timer.c */
-	unsigned long	tbl;
-	unsigned long	lastinc;
-#endif
-	unsigned int	baudrate;
-	unsigned long	have_console;	/* serial_init() was called */
-#ifdef CONFIG_PRE_CONSOLE_BUFFER
-	unsigned long	precon_buf_idx;	/* Pre-Console buffer index */
+	unsigned long per_clk;	/* Peripheral bus clock */
+	unsigned long dev_clk;	/* Device clock */
 #endif
-	phys_size_t	ram_size;	/* RAM size */
-	unsigned long	reloc_off;	/* Relocation Offset */
-	unsigned long	env_addr;	/* Address  of Environment struct */
-	unsigned long	env_valid;	/* Checksum of Environment valid? */
-	void		**jt;		/* jump table */
-	char		env_buf[32];	/* buffer for getenv() before reloc. */
-} gd_t;
+};
 
-#include <asm-generic/global_data_flags.h>
+#include <asm-generic/global_data.h>
 
 #define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("k0")
 

arch/mips/include/asm/io.h

@@ -254,7 +254,7 @@ out:
  */
 
 #define __OUT1(s) \
-extern inline void __out##s(unsigned int value, unsigned int port) {
+static inline void __out##s(unsigned int value, unsigned int port) {
 
 #define __OUT2(m) \
 __asm__ __volatile__ ("s" #m "\t%0,%1(%2)"
@@ -268,7 +268,7 @@ __OUT1(s##c_p) __OUT2(m) : : "r" (__ioswab##w(value)), "ir" (port), "r" (mips_io
 	SLOW_DOWN_IO; }
 
 #define __IN1(t,s) \
-extern __inline__ t __in##s(unsigned int port) { t _v;
+static inline t __in##s(unsigned int port) { t _v;
 
 /*
  * Required nops will be inserted by the assembler
@@ -283,7 +283,7 @@ __IN1(t,s##_p) __IN2(m) : "=r" (_v) : "i" (0), "r" (mips_io_port_base+port)); SL
 __IN1(t,s##c_p) __IN2(m) : "=r" (_v) : "ir" (port), "r" (mips_io_port_base)); SLOW_DOWN_IO; return __ioswab##w(_v); }
 
 #define __INS1(s) \
-extern inline void __ins##s(unsigned int port, void * addr, unsigned long count) {
+static inline void __ins##s(unsigned int port, void * addr, unsigned long count) {
 
 #define __INS2(m) \
 if (count) \
@@ -311,7 +311,7 @@ __INS1(s##c) __INS2(m) \
 	: "$1");}
 
 #define __OUTS1(s) \
-extern inline void __outs##s(unsigned int port, const void * addr, unsigned long count) {
+static inline void __outs##s(unsigned int port, const void * addr, unsigned long count) {
 
 #define __OUTS2(m) \
 if (count) \

arch/nds32/include/asm/global_data.h

@@ -33,39 +33,12 @@
 
 #ifndef	__ASM_GBL_DATA_H
 #define __ASM_GBL_DATA_H
-/*
- * The following data structure is placed in some memory wich is
- * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
- * some locked parts of the data cache) to allow for a minimum set of
- * global variables during system initialization (until we have set
- * up the memory controller so that we can use RAM).
- */
-
-typedef	struct global_data {
-	bd_t		*bd;
-	unsigned long	flags;
-	unsigned int	baudrate;
-	unsigned long	have_console;	/* serial_init() was called */
-
-	unsigned long	reloc_off;	/* Relocation Offset */
-	unsigned long	env_addr;	/* Address  of Environment struct */
-	unsigned long	env_valid;	/* Checksum of Environment valid? */
-	unsigned long	fb_base;	/* base address of frame buffer */
-
-	unsigned long	relocaddr;	/* Start address of U-Boot in RAM */
-	phys_size_t	ram_size;	/* RAM size */
-	unsigned long	mon_len;	/* monitor len */
-	unsigned long	irq_sp;		/* irq stack pointer */
-	unsigned long	start_addr_sp;	/* start_addr_stackpointer */
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
-	unsigned long	tlb_addr;
-#endif
 
-	void		**jt;		/* jump table */
-	char		env_buf[32];	/* buffer for getenv() before reloc. */
-} gd_t;
+/* Architecture-specific global data */
+struct arch_global_data {
+};
 
-#include <asm-generic/global_data_flags.h>
+#include <asm-generic/global_data.h>
 
 #ifdef CONFIG_GLOBAL_DATA_NOT_REG10
 extern volatile gd_t g_gd;

arch/nds32/lib/board.c

@@ -207,17 +207,6 @@ void board_init_f(ulong bootflag)
 
 	addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size;
 
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
-	/* reserve TLB table */
-	addr -= (4096 * 4);
-
-	/* round down to next 64 kB limit */
-	addr &= ~(0x10000 - 1);
-
-	gd->tlb_addr = addr;
-	debug("TLB table at: %08lx\n", addr);
-#endif
-
 	/* round down to next 4 kB limit */
 	addr &= ~(4096 - 1);
 	debug("Top of RAM usable for U-Boot at: %08lx\n", addr);

arch/nios2/include/asm/global_data.h

@@ -23,28 +23,11 @@
 #ifndef	__ASM_NIOS2_GLOBALDATA_H_
 #define __ASM_NIOS2_GLOBALDATA_H_
 
-typedef	struct	global_data {
-	bd_t		*bd;
-	unsigned long	flags;
-	unsigned int	baudrate;
-	unsigned long	cpu_clk;	/* CPU clock in Hz!		*/
-	unsigned long	have_console;	/* serial_init() was called */
-#ifdef CONFIG_PRE_CONSOLE_BUFFER
-	unsigned long	precon_buf_idx;	/* Pre-Console buffer index */
-#endif
-	phys_size_t	ram_size;	/* RAM size */
-	unsigned long	env_addr;	/* Address  of Environment struct */
-	unsigned long	env_valid;	/* Checksum of Environment valid */
-#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
-	unsigned long	post_log_word;	/* Record POST activities */
-	unsigned long	post_log_res; /* success of POST test */
-	unsigned long	post_init_f_time; /* When post_init_f started */
-#endif
-	void		**jt;		/* Standalone app jump table */
-	char		env_buf[32];	/* buffer for getenv() before reloc. */
-} gd_t;
+/* Architecture-specific global data */
+struct arch_global_data {
+};
 
-#include <asm-generic/global_data_flags.h>
+#include <asm-generic/global_data.h>
 
 #define DECLARE_GLOBAL_DATA_PTR     register gd_t *gd asm ("gp")
 

arch/openrisc/include/asm/global_data.h

@@ -24,29 +24,12 @@
 
 #ifndef __ASM_GBL_DATA_H
 #define __ASM_GBL_DATA_H
-/*
- * The following data structure is placed in some memory wich is
- * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
- * some locked parts of the data cache) to allow for a minimum set of
- * global variables during system initialization (until we have set
- * up the memory controller so that we can use RAM).
- */
 
-typedef struct global_data {
-	bd_t		*bd;
-	unsigned long	flags;
-	unsigned int	baudrate;
-	unsigned long	cpu_clk;	/* CPU clock in Hz! */
-	unsigned long	have_console;	/* serial_init() was called */
-	phys_size_t	ram_size;	/* RAM size */
-	unsigned long	env_addr;	/* Address  of Environment struct */
-	unsigned long	env_valid;	/* Checksum of Environment valid? */
-	unsigned long	fb_base;	/* base address of frame buffer */
-	void		**jt;		/* jump table */
-	char		env_buf[32];	/* buffer for getenv() before reloc. */
-} gd_t;
+/* Architecture-specific global data */
+struct arch_global_data {
+};
 
-#include <asm-generic/global_data_flags.h>
+#include <asm-generic/global_data.h>
 
 /* OR32 GCC already has r10 set as fixed-use */
 #define DECLARE_GLOBAL_DATA_PTR	register volatile gd_t *gd asm ("r10")

arch/powerpc/cpu/mpc512x/cpu.c

@@ -68,8 +68,8 @@ int checkcpu (void)
 	}
 	printf ("at %s MHz, CSB at %s MHz (RSR=0x%04lx)\n",
 		strmhz(buf1, clock),
-		strmhz(buf2, gd->csb_clk),
-		gd->reset_status & 0xffff);
+		strmhz(buf2, gd->arch.csb_clk),
+		gd->arch.reset_status & 0xffff);
 	return 0;
 }
 

arch/powerpc/cpu/mpc512x/cpu_init.c

@@ -62,7 +62,7 @@ void cpu_init_f (volatile immap_t * im)
 #endif
 
 	/* RSR - Reset Status Register - clear all status */
-	gd->reset_status = im->reset.rsr;
+	gd->arch.reset_status = im->reset.rsr;
 	out_be32(&im->reset.rsr, ~RSR_RES);
 
 	/*

arch/powerpc/cpu/mpc512x/i2c.c

@@ -250,7 +250,7 @@ static int mpc_get_fdr (int speed)
 			{126, 128}
 		};
 
-		ips = gd->ips_clk;
+		ips = gd->arch.ips_clk;
 		for (i = 7; i >= 0; i--) {
 			for (j = 7; j >= 0; j--) {
 				scl = 2 * (scltap[j].scl2tap +

arch/powerpc/cpu/mpc512x/ide.c

@@ -100,7 +100,7 @@ int ide_preinit (void)
 	ide_set_reset(0);
 
 	/* Init timings : we use PIO mode 0 timings */
-	t = 1000000000 / gd->ips_clk;	/* period in ns */
+	t = 1000000000 / gd->arch.ips_clk;	/* period in ns */
 	cfg.bytes.field1 = 3;
 	cfg.bytes.field2 = 3;
 	cfg.bytes.field3 = (pio_specs.t1 + t) / t;

arch/powerpc/cpu/mpc512x/serial.c

@@ -140,7 +140,7 @@ void serial_setbrg_dev(unsigned int idx)
 	}
 
 	/* calculate divisor for setting PSC CTUR and CTLR registers */
-	baseclk = (gd->ips_clk + 8) / 16;
+	baseclk = (gd->arch.ips_clk + 8) / 16;
 	div = (baseclk + (baudrate / 2)) / baudrate;
 
 	out_8(&psc->ctur, (div >> 8) & 0xff);

arch/powerpc/cpu/mpc512x/speed.c

@@ -113,9 +113,9 @@ int get_clocks (void)
 		pci_clk = 333333;
 	}
 
-	gd->ips_clk = ips_clk;
+	gd->arch.ips_clk = ips_clk;
 	gd->pci_clk = pci_clk;
-	gd->csb_clk = csb_clk;
+	gd->arch.csb_clk = csb_clk;
 	gd->cpu_clk = core_clk;
 	gd->bus_clk = csb_clk;
 	return 0;
@@ -128,7 +128,7 @@ int get_clocks (void)
  *********************************************/
 ulong get_bus_freq (ulong dummy)
 {
-	return gd->csb_clk;
+	return gd->arch.csb_clk;
 }
 
 int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
@@ -137,10 +137,13 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 
 	printf("Clock configuration:\n");
 	printf("  CPU:                 %-4s MHz\n", strmhz(buf, gd->cpu_clk));
-	printf("  Coherent System Bus: %-4s MHz\n", strmhz(buf, gd->csb_clk));
-	printf("  IPS Bus:             %-4s MHz\n", strmhz(buf, gd->ips_clk));
+	printf("  Coherent System Bus: %-4s MHz\n",
+	       strmhz(buf, gd->arch.csb_clk));
+	printf("  IPS Bus:             %-4s MHz\n",
+	       strmhz(buf, gd->arch.ips_clk));
 	printf("  PCI:                 %-4s MHz\n", strmhz(buf, gd->pci_clk));
-	printf("  DDR:                 %-4s MHz\n", strmhz(buf, 2*gd->csb_clk));
+	printf("  DDR:                 %-4s MHz\n",
+	       strmhz(buf, 2 * gd->arch.csb_clk));
 	return 0;
 }
 

arch/powerpc/cpu/mpc5xxx/i2c.c

@@ -310,7 +310,7 @@ static int mpc_get_fdr(int speed)
 			{126, 128}
 		};
 
-		ipb = gd->ipb_clk;
+		ipb = gd->arch.ipb_clk;
 		for (i = 7; i >= 0; i--) {
 			for (j = 7; j >= 0; j--) {
 				scl = 2 * (scltap[j].scl2tap +

arch/powerpc/cpu/mpc5xxx/ide.c

@@ -75,7 +75,7 @@ int ide_preinit (void)
 	psdma->PtdCntrl |= 1;
 
 	/* Init timings : we use PIO mode 0 timings */
-	period = 1000000000 / gd->ipb_clk;	/* period in ns */
+	period = 1000000000 / gd->arch.ipb_clk;	/* period in ns */
 
 	t0 = CALC_TIMING (600);
 	t2_8 = CALC_TIMING (290);

arch/powerpc/cpu/mpc5xxx/serial.c

@@ -89,7 +89,7 @@ int serial_init_dev (unsigned long dev_base)
 
 	/* select clock sources */
 	psc->psc_clock_select = 0;
-	baseclk = (gd->ipb_clk + 16) / 32;
+	baseclk = (gd->arch.ipb_clk + 16) / 32;
 
 	/* switch to UART mode */
 	psc->sicr = 0;
@@ -169,7 +169,7 @@ void serial_setbrg_dev (unsigned long dev_base)
 	volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
 	unsigned long baseclk, div;
 
-	baseclk = (gd->ipb_clk + 16) / 32;
+	baseclk = (gd->arch.ipb_clk + 16) / 32;
 
 	/* set up UART divisor */
 	div = (baseclk + (gd->baudrate/2)) / gd->baudrate;

arch/powerpc/cpu/mpc5xxx/speed.c

@@ -66,14 +66,20 @@ int get_clocks (void)
 
 	val = *(vu_long *)MPC5XXX_CDM_CFG;
 	if (val & (1 << 8)) {
-		gd->ipb_clk = gd->bus_clk / 2;
+		gd->arch.ipb_clk = gd->bus_clk / 2;
 	} else {
-		gd->ipb_clk = gd->bus_clk;
+		gd->arch.ipb_clk = gd->bus_clk;
 	}
 	switch (val & 3) {
-		case 0: gd->pci_clk = gd->ipb_clk; break;
-		case 1: gd->pci_clk = gd->ipb_clk / 2; break;
-		default: gd->pci_clk = gd->bus_clk / 4; break;
+	case 0:
+		gd->pci_clk = gd->arch.ipb_clk;
+		break;
+	case 1:
+		gd->pci_clk = gd->arch.ipb_clk / 2;
+		break;
+	default:
+		gd->pci_clk = gd->bus_clk / 4;
+		break;
 	}
 
 	return (0);
@@ -85,7 +91,7 @@ int prt_mpc5xxx_clks (void)
 
 	printf ("       Bus %s MHz, IPB %s MHz, PCI %s MHz\n",
 		strmhz(buf1, gd->bus_clk),
-		strmhz(buf2, gd->ipb_clk),
+		strmhz(buf2, gd->arch.ipb_clk),
 		strmhz(buf3, gd->pci_clk)
 	);
 	return (0);

arch/powerpc/cpu/mpc8220/fec.c

@@ -288,9 +288,11 @@ static int mpc8220_fec_init (struct eth_device *dev, bd_t * bis)
 		 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
 		 * and do not drop the Preamble.
 		 */
-		/* tbd - rtm */
-		/*fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); */
-		/* No MII for 7-wire mode */
+		/*
+		 * tbd - rtm
+		 * fec->eth->mii_speed = (((gd->arch.ipb_clk >> 20) / 5) << 1);
+		 * No MII for 7-wire mode
+		 */
 		fec->eth->mii_speed = 0x00000030;
 	}
 

arch/powerpc/cpu/mpc8220/speed.c

@@ -71,7 +71,7 @@ int get_clocks (void)
 #error clock measuring not implemented yet - define CONFIG_SYS_MPC8220_CLKIN
 #endif
 
-	gd->inp_clk = CONFIG_SYS_MPC8220_CLKIN;
+	gd->arch.inp_clk = CONFIG_SYS_MPC8220_CLKIN;
 
 	/* Read XLB to PCI(INP) clock multiplier */
 	pci2bus = (*((volatile u32 *)PCI_REG_PCIGSCR) &
@@ -85,7 +85,7 @@ int get_clocks (void)
 
 	/* FlexBus is temporary set as the same as input clock */
 	/* will do dynamic in the future */
-	gd->flb_clk = CONFIG_SYS_MPC8220_CLKIN;
+	gd->arch.flb_clk = CONFIG_SYS_MPC8220_CLKIN;
 
 	/* CPU Clock - Read HID1 */
 	asm volatile ("mfspr %0, 1009":"=r" (hid1):);
@@ -97,12 +97,14 @@ int get_clocks (void)
 	for (i = 0; i < size; i++)
 		if (hid1 == bus2core[i].hid1) {
 			gd->cpu_clk = (bus2core[i].multi * gd->bus_clk) >> 1;
-			gd->vco_clk = CONFIG_SYS_MPC8220_SYSPLL_VCO_MULTIPLIER * (gd->pci_clk * bus2core[i].vco_div)/2;
+			gd->arch.vco_clk =
+				CONFIG_SYS_MPC8220_SYSPLL_VCO_MULTIPLIER *
+				(gd->pci_clk * bus2core[i].vco_div) / 2;
 			break;
 		}
 
 	/* hardcoded 81MHz for now */
-	gd->pev_clk = 81000000;
+	gd->arch.pev_clk = 81000000;
 
 	return (0);
 }
@@ -115,7 +117,7 @@ int prt_mpc8220_clks (void)
 		strmhz(buf1, gd->bus_clk),
 		strmhz(buf2, gd->cpu_clk),
 		strmhz(buf3, gd->pci_clk),
-		strmhz(buf4, gd->vco_clk)
+		strmhz(buf4, gd->arch.vco_clk)
 	);
 	return (0);
 }

arch/powerpc/cpu/mpc8260/commproc.c

@@ -30,8 +30,8 @@ m8260_cpm_reset(void)
 
 	/* Reclaim the DP memory for our use.
 	*/
-	gd->dp_alloc_base = CPM_DATAONLY_BASE;
-	gd->dp_alloc_top = gd->dp_alloc_base + CPM_DATAONLY_SIZE;
+	gd->arch.dp_alloc_base = CPM_DATAONLY_BASE;
+	gd->arch.dp_alloc_top = gd->arch.dp_alloc_base + CPM_DATAONLY_SIZE;
 
 	/*
 	 * Reset CPM
@@ -60,21 +60,22 @@ m8260_cpm_dpalloc(uint size, uint align)
 	uint	savebase;
 
 	align_mask = align - 1;
-	savebase = gd->dp_alloc_base;
+	savebase = gd->arch.dp_alloc_base;
 
-	if ((off = (gd->dp_alloc_base & align_mask)) != 0)
-		gd->dp_alloc_base += (align - off);
+	off = gd->arch.dp_alloc_base & align_mask;
+	if (off != 0)
+		gd->arch.dp_alloc_base += (align - off);
 
 	if ((off = size & align_mask) != 0)
 		size += align - off;
 
-	if ((gd->dp_alloc_base + size) >= gd->dp_alloc_top) {
-		gd->dp_alloc_base = savebase;
+	if ((gd->arch.dp_alloc_base + size) >= gd->arch.dp_alloc_top) {
+		gd->arch.dp_alloc_base = savebase;
 		panic("m8260_cpm_dpalloc: ran out of dual port ram!");
 	}
 
-	retloc = gd->dp_alloc_base;
-	gd->dp_alloc_base += size;
+	retloc = gd->arch.dp_alloc_base;
+	gd->arch.dp_alloc_base += size;
 
 	memset((void *)&immr->im_dprambase[retloc], 0, size);
 
@@ -101,7 +102,7 @@ m8260_cpm_hostalloc(uint size, uint align)
  * Baud rate clocks are zero-based in the driver code (as that maps
  * to port numbers).  Documentation uses 1-based numbering.
  */
-#define BRG_INT_CLK	gd->brg_clk
+#define BRG_INT_CLK	gd->arch.brg_clk
 #define BRG_UART_CLK	(BRG_INT_CLK / 16)
 
 /* This function is used by UARTs, or anything else that uses a 16x

arch/powerpc/cpu/mpc8260/cpu_init.c

@@ -120,7 +120,7 @@ void cpu_init_f (volatile immap_t * immr)
 	memset ((void *) gd, 0, sizeof (gd_t));
 
 	/* RSR - Reset Status Register - clear all status (5-4) */
-	gd->reset_status = immr->im_clkrst.car_rsr;
+	gd->arch.reset_status = immr->im_clkrst.car_rsr;
 	immr->im_clkrst.car_rsr = RSR_ALLBITS;
 
 	/* RMR - Reset Mode Register - contains checkstop reset enable (5-5) */
@@ -274,7 +274,7 @@ int prt_8260_rsr (void)
 		RSR_EHRS, "External Hard"}
 	};
 	static int n = sizeof bits / sizeof bits[0];
-	ulong rsr = gd->reset_status;
+	ulong rsr = gd->arch.reset_status;
 	int i;
 	char *sep;
 

arch/powerpc/cpu/mpc8260/i2c.c

@@ -259,7 +259,7 @@ void i2c_init(int speed, int slaveadd)
 	 * divide BRGCLK by 1)
 	 */
 	debug("[I2C] Setting rate...\n");
-	i2c_setrate(gd->brg_clk, CONFIG_SYS_I2C_SPEED);
+	i2c_setrate(gd->arch.brg_clk, CONFIG_SYS_I2C_SPEED);
 
 	/* Set I2C controller in master mode */
 	i2c->i2c_i2com = 0x01;

arch/powerpc/cpu/mpc8260/speed.c

@@ -135,17 +135,17 @@ int get_clocks (void)
 	    (get_pvr () == PVR_8260_HIP7R1) ||
 	    (get_pvr () == PVR_8260_HIP7RA)) {
 		pllmf = (scmr & SCMR_PLLMF_MSKH7) >> SCMR_PLLMF_SHIFT;
-		gd->vco_out = clkin * (pllmf + 1);
+		gd->arch.vco_out = clkin * (pllmf + 1);
 	} else {                        /* HiP3, HiP4 */
 		pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT;
 		plldf = (scmr & SCMR_PLLDF) ? 1 : 0;
-		gd->vco_out = (clkin * 2 * (pllmf + 1)) / (plldf + 1);
+		gd->arch.vco_out = (clkin * 2 * (pllmf + 1)) / (plldf + 1);
 	}
 
-	gd->cpm_clk = gd->vco_out / 2;
+	gd->arch.cpm_clk = gd->arch.vco_out / 2;
 	gd->bus_clk = clkin;
-	gd->scc_clk = gd->vco_out / 4;
-	gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1)));
+	gd->arch.scc_clk = gd->arch.vco_out / 4;
+	gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));
 
 	if (cp->b2c_mult > 0) {
 		gd->cpu_clk = (clkin * cp->b2c_mult) / 2;
@@ -173,7 +173,7 @@ int get_clocks (void)
 			pci_div = pcidf + 1;
 		}
 
-		gd->pci_clk = (gd->cpm_clk * 2) / pci_div;
+		gd->pci_clk = (gd->arch.cpm_clk * 2) / pci_div;
 	}
 #endif
 
@@ -231,10 +231,10 @@ int prt_8260_clks (void)
 			plldf, pllmf, pcidf);
 
 	printf (" - vco_out %10ld, scc_clk %10ld, brg_clk %10ld\n",
-			gd->vco_out, gd->scc_clk, gd->brg_clk);
+			gd->arch.vco_out, gd->arch.scc_clk, gd->arch.brg_clk);
 
 	printf (" - cpu_clk %10ld, cpm_clk %10ld, bus_clk %10ld\n",
-			gd->cpu_clk, gd->cpm_clk, gd->bus_clk);
+			gd->cpu_clk, gd->arch.cpm_clk, gd->bus_clk);
 #ifdef CONFIG_PCI
 	printf (" - pci_clk %10ld\n", gd->pci_clk);
 #endif

arch/powerpc/cpu/mpc83xx/cpu.c

@@ -122,7 +122,7 @@ int checkcpu(void)
 
 	printf(" at %s MHz, ", strmhz(buf, clock));
 
-	printf("CSB: %s MHz\n", strmhz(buf, gd->csb_clk));
+	printf("CSB: %s MHz\n", strmhz(buf, gd->arch.csb_clk));
 
 	return 0;
 }

arch/powerpc/cpu/mpc83xx/cpu_init.c

@@ -232,12 +232,12 @@ void cpu_init_f (volatile immap_t * im)
 	clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val);
 
 	/* RSR - Reset Status Register - clear all status (4.6.1.3) */
-	gd->reset_status = __raw_readl(&im->reset.rsr);
+	gd->arch.reset_status = __raw_readl(&im->reset.rsr);
 	__raw_writel(~(RSR_RES), &im->reset.rsr);
 
 	/* AER - Arbiter Event Register - store status */
-	gd->arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr);
-	gd->arbiter_event_address = __raw_readl(&im->arbiter.aeadr);
+	gd->arch.arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr);
+	gd->arch.arbiter_event_address = __raw_readl(&im->arbiter.aeadr);
 
 	/*
 	 * RMR - Reset Mode Register
@@ -440,42 +440,44 @@ static int print_83xx_arb_event(int force)
 		"reserved"
 	};
 
-	int etype = (gd->arbiter_event_attributes & AEATR_EVENT)
+	int etype = (gd->arch.arbiter_event_attributes & AEATR_EVENT)
 	            >> AEATR_EVENT_SHIFT;
-	int mstr_id = (gd->arbiter_event_attributes & AEATR_MSTR_ID)
+	int mstr_id = (gd->arch.arbiter_event_attributes & AEATR_MSTR_ID)
 	              >> AEATR_MSTR_ID_SHIFT;
-	int tbst = (gd->arbiter_event_attributes & AEATR_TBST)
+	int tbst = (gd->arch.arbiter_event_attributes & AEATR_TBST)
 	           >> AEATR_TBST_SHIFT;
-	int tsize = (gd->arbiter_event_attributes & AEATR_TSIZE)
+	int tsize = (gd->arch.arbiter_event_attributes & AEATR_TSIZE)
 	            >> AEATR_TSIZE_SHIFT;
-	int ttype = (gd->arbiter_event_attributes & AEATR_TTYPE)
+	int ttype = (gd->arch.arbiter_event_attributes & AEATR_TTYPE)
 	            >> AEATR_TTYPE_SHIFT;
 
-	if (!force && !gd->arbiter_event_address)
+	if (!force && !gd->arch.arbiter_event_address)
 		return 0;
 
 	puts("Arbiter Event Status:\n");
-	printf("       Event Address: 0x%08lX\n", gd->arbiter_event_address);
+	printf("       Event Address: 0x%08lX\n",
+	       gd->arch.arbiter_event_address);
 	printf("       Event Type:    0x%1x  = %s\n", etype, event[etype]);
 	printf("       Master ID:     0x%02x = %s\n", mstr_id, master[mstr_id]);
 	printf("       Transfer Size: 0x%1x  = %d bytes\n", (tbst<<3) | tsize,
 				tbst ? (tsize ? tsize : 8) : 16 + 8 * tsize);
 	printf("       Transfer Type: 0x%02x = %s\n", ttype, transfer[ttype]);
 
-	return gd->arbiter_event_address;
+	return gd->arch.arbiter_event_address;
 }
 
 #elif defined(CONFIG_DISPLAY_AER_BRIEF)
 
 static int print_83xx_arb_event(int force)
 {
-	if (!force && !gd->arbiter_event_address)
+	if (!force && !gd->arch.arbiter_event_address)
 		return 0;
 
 	printf("Arbiter Event Status: AEATR=0x%08lX, AEADR=0x%08lX\n",
-		gd->arbiter_event_attributes, gd->arbiter_event_address);
+		gd->arch.arbiter_event_attributes,
+		gd->arch.arbiter_event_address);
 
-	return gd->arbiter_event_address;
+	return gd->arch.arbiter_event_address;
 }
 #endif /* CONFIG_DISPLAY_AER_xxxx */
 
@@ -499,7 +501,7 @@ int prt_83xx_rsr(void)
 		RSR_HRS,  "External/Internal Hard"}
 	};
 	static int n = sizeof bits / sizeof bits[0];
-	ulong rsr = gd->reset_status;
+	ulong rsr = gd->arch.reset_status;
 	int i;
 	char *sep;
 

arch/powerpc/cpu/mpc83xx/fdt.c

@@ -118,7 +118,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
 		"bus-frequency", bd->bi_busfreq, 1);
 	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
-		"clock-frequency", gd->core_clk, 1);
+		"clock-frequency", gd->arch.core_clk, 1);
 	do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
 		"bus-frequency", bd->bi_busfreq, 1);
 	do_fixup_by_compat_u32(blob, "fsl,soc",

arch/powerpc/cpu/mpc83xx/pcie.c

@@ -286,8 +286,8 @@ static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg)
 	get_clocks();
 	/* Configure the PCIE controller core clock ratio */
 	out_le32(hose_cfg_base + PEX_GCLK_RATIO,
-		(((bus ? gd->pciexp2_clk : gd->pciexp1_clk) / 1000000) * 16)
-		/ 333);
+		(((bus ? gd->arch.pciexp2_clk : gd->arch.pciexp1_clk)
+			/ 1000000) * 16) / 333);
 	udelay(1000000);
 
 	/* Do Type 1 bridge configuration */

arch/powerpc/cpu/mpc83xx/speed.c

@@ -462,53 +462,53 @@ int get_clocks(void)
 	brg_clk = qe_clk / 2;
 #endif
 
-	gd->csb_clk = csb_clk;
+	gd->arch.csb_clk = csb_clk;
 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
 	defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
-	gd->tsec1_clk = tsec1_clk;
-	gd->tsec2_clk = tsec2_clk;
-	gd->usbdr_clk = usbdr_clk;
+	gd->arch.tsec1_clk = tsec1_clk;
+	gd->arch.tsec2_clk = tsec2_clk;
+	gd->arch.usbdr_clk = usbdr_clk;
 #elif defined(CONFIG_MPC8309)
-	gd->usbdr_clk = usbdr_clk;
+	gd->arch.usbdr_clk = usbdr_clk;
 #endif
 #if defined(CONFIG_MPC834x)
-	gd->usbmph_clk = usbmph_clk;
+	gd->arch.usbmph_clk = usbmph_clk;
 #endif
 #if defined(CONFIG_MPC8315)
-	gd->tdm_clk = tdm_clk;
+	gd->arch.tdm_clk = tdm_clk;
 #endif
 #if defined(CONFIG_FSL_ESDHC)
-	gd->sdhc_clk = sdhc_clk;
+	gd->arch.sdhc_clk = sdhc_clk;
 #endif
-	gd->core_clk = core_clk;
-	gd->i2c1_clk = i2c1_clk;
+	gd->arch.core_clk = core_clk;
+	gd->arch.i2c1_clk = i2c1_clk;
 #if !defined(CONFIG_MPC832x)
-	gd->i2c2_clk = i2c2_clk;
+	gd->arch.i2c2_clk = i2c2_clk;
 #endif
 #if !defined(CONFIG_MPC8309)
-	gd->enc_clk = enc_clk;
+	gd->arch.enc_clk = enc_clk;
 #endif
-	gd->lbiu_clk = lbiu_clk;
-	gd->lclk_clk = lclk_clk;
+	gd->arch.lbiu_clk = lbiu_clk;
+	gd->arch.lclk_clk = lclk_clk;
 	gd->mem_clk = mem_clk;
 #if defined(CONFIG_MPC8360)
-	gd->mem_sec_clk = mem_sec_clk;
+	gd->arch.mem_sec_clk = mem_sec_clk;
 #endif
 #if defined(CONFIG_QE)
-	gd->qe_clk = qe_clk;
-	gd->brg_clk = brg_clk;
+	gd->arch.qe_clk = qe_clk;
+	gd->arch.brg_clk = brg_clk;
 #endif
 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
 	defined(CONFIG_MPC837x)
-	gd->pciexp1_clk = pciexp1_clk;
-	gd->pciexp2_clk = pciexp2_clk;
+	gd->arch.pciexp1_clk = pciexp1_clk;
+	gd->arch.pciexp2_clk = pciexp2_clk;
 #endif
 #if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
-	gd->sata_clk = sata_clk;
+	gd->arch.sata_clk = sata_clk;
 #endif
 	gd->pci_clk = pci_sync_in;
-	gd->cpu_clk = gd->core_clk;
-	gd->bus_clk = gd->csb_clk;
+	gd->cpu_clk = gd->arch.core_clk;
+	gd->bus_clk = gd->arch.csb_clk;
 	return 0;
 
 }
@@ -519,7 +519,7 @@ int get_clocks(void)
  *********************************************/
 ulong get_bus_freq(ulong dummy)
 {
-	return gd->csb_clk;
+	return gd->arch.csb_clk;
 }
 
 /********************************************
@@ -536,49 +536,69 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	char buf[32];
 
 	printf("Clock configuration:\n");
-	printf("  Core:                %-4s MHz\n", strmhz(buf, gd->core_clk));
-	printf("  Coherent System Bus: %-4s MHz\n", strmhz(buf, gd->csb_clk));
+	printf("  Core:                %-4s MHz\n",
+	       strmhz(buf, gd->arch.core_clk));
+	printf("  Coherent System Bus: %-4s MHz\n",
+	       strmhz(buf, gd->arch.csb_clk));
 #if defined(CONFIG_QE)
-	printf("  QE:                  %-4s MHz\n", strmhz(buf, gd->qe_clk));
-	printf("  BRG:                 %-4s MHz\n", strmhz(buf, gd->brg_clk));
-#endif
-	printf("  Local Bus Controller:%-4s MHz\n", strmhz(buf, gd->lbiu_clk));
-	printf("  Local Bus:           %-4s MHz\n", strmhz(buf, gd->lclk_clk));
+	printf("  QE:                  %-4s MHz\n",
+	       strmhz(buf, gd->arch.qe_clk));
+	printf("  BRG:                 %-4s MHz\n",
+	       strmhz(buf, gd->arch.brg_clk));
+#endif
+	printf("  Local Bus Controller:%-4s MHz\n",
+	       strmhz(buf, gd->arch.lbiu_clk));
+	printf("  Local Bus:           %-4s MHz\n",
+	       strmhz(buf, gd->arch.lclk_clk));
 	printf("  DDR:                 %-4s MHz\n", strmhz(buf, gd->mem_clk));
 #if defined(CONFIG_MPC8360)
-	printf("  DDR Secondary:       %-4s MHz\n", strmhz(buf, gd->mem_sec_clk));
+	printf("  DDR Secondary:       %-4s MHz\n",
+	       strmhz(buf, gd->arch.mem_sec_clk));
 #endif
 #if !defined(CONFIG_MPC8309)
-	printf("  SEC:                 %-4s MHz\n", strmhz(buf, gd->enc_clk));
+	printf("  SEC:                 %-4s MHz\n",
+	       strmhz(buf, gd->arch.enc_clk));
 #endif
-	printf("  I2C1:                %-4s MHz\n", strmhz(buf, gd->i2c1_clk));
+	printf("  I2C1:                %-4s MHz\n",
+	       strmhz(buf, gd->arch.i2c1_clk));
 #if !defined(CONFIG_MPC832x)
-	printf("  I2C2:                %-4s MHz\n", strmhz(buf, gd->i2c2_clk));
+	printf("  I2C2:                %-4s MHz\n",
+	       strmhz(buf, gd->arch.i2c2_clk));
 #endif
 #if defined(CONFIG_MPC8315)
-	printf("  TDM:                 %-4s MHz\n", strmhz(buf, gd->tdm_clk));
+	printf("  TDM:                 %-4s MHz\n",
+	       strmhz(buf, gd->arch.tdm_clk));
 #endif
 #if defined(CONFIG_FSL_ESDHC)
-	printf("  SDHC:                %-4s MHz\n", strmhz(buf, gd->sdhc_clk));
+	printf("  SDHC:                %-4s MHz\n",
+	       strmhz(buf, gd->arch.sdhc_clk));
 #endif
 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
 	defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
-	printf("  TSEC1:               %-4s MHz\n", strmhz(buf, gd->tsec1_clk));
-	printf("  TSEC2:               %-4s MHz\n", strmhz(buf, gd->tsec2_clk));
-	printf("  USB DR:              %-4s MHz\n", strmhz(buf, gd->usbdr_clk));
+	printf("  TSEC1:               %-4s MHz\n",
+	       strmhz(buf, gd->arch.tsec1_clk));
+	printf("  TSEC2:               %-4s MHz\n",
+	       strmhz(buf, gd->arch.tsec2_clk));
+	printf("  USB DR:              %-4s MHz\n",
+	       strmhz(buf, gd->arch.usbdr_clk));
 #elif defined(CONFIG_MPC8309)
-	printf("  USB DR:              %-4s MHz\n", strmhz(buf, gd->usbdr_clk));
+	printf("  USB DR:              %-4s MHz\n",
+	       strmhz(buf, gd->arch.usbdr_clk));
 #endif
 #if defined(CONFIG_MPC834x)
-	printf("  USB MPH:             %-4s MHz\n", strmhz(buf, gd->usbmph_clk));
+	printf("  USB MPH:             %-4s MHz\n",
+	       strmhz(buf, gd->arch.usbmph_clk));
 #endif
 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
 	defined(CONFIG_MPC837x)
-	printf("  PCIEXP1:             %-4s MHz\n", strmhz(buf, gd->pciexp1_clk));
-	printf("  PCIEXP2:             %-4s MHz\n", strmhz(buf, gd->pciexp2_clk));
+	printf("  PCIEXP1:             %-4s MHz\n",
+	       strmhz(buf, gd->arch.pciexp1_clk));
+	printf("  PCIEXP2:             %-4s MHz\n",
+	       strmhz(buf, gd->arch.pciexp2_clk));
 #endif
 #if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
-	printf("  SATA:                %-4s MHz\n", strmhz(buf, gd->sata_clk));
+	printf("  SATA:                %-4s MHz\n",
+	       strmhz(buf, gd->arch.sata_clk));
 #endif
 	return 0;
 }

arch/powerpc/cpu/mpc85xx/Makefile

@@ -83,8 +83,10 @@ COBJS-$(CONFIG_PPC_P4080)	+= ddr-gen3.o
 COBJS-$(CONFIG_PPC_P5020)	+= ddr-gen3.o
 COBJS-$(CONFIG_PPC_P5040)	+= ddr-gen3.o
 COBJS-$(CONFIG_PPC_T4240)	+= ddr-gen3.o
+COBJS-$(CONFIG_PPC_B4420)	+= ddr-gen3.o
 COBJS-$(CONFIG_PPC_B4860)	+= ddr-gen3.o
 COBJS-$(CONFIG_BSC9131)		+= ddr-gen3.o
+COBJS-$(CONFIG_BSC9132)		+= ddr-gen3.o
 
 COBJS-$(CONFIG_CPM2)	+= ether_fcc.o
 COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
@@ -100,6 +102,7 @@ COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o
 COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o
 COBJS-$(CONFIG_PPC_P5040) += p5040_ids.o
 COBJS-$(CONFIG_PPC_T4240) += t4240_ids.o
+COBJS-$(CONFIG_PPC_B4420) += b4860_ids.o
 COBJS-$(CONFIG_PPC_B4860) += b4860_ids.o
 
 COBJS-$(CONFIG_QE)	+= qe_io.o
@@ -134,7 +137,9 @@ COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o
 COBJS-$(CONFIG_PPC_P5020) += p5020_serdes.o
 COBJS-$(CONFIG_PPC_P5040) += p5040_serdes.o
 COBJS-$(CONFIG_PPC_T4240) += t4240_serdes.o
+COBJS-$(CONFIG_PPC_B4420) += b4860_serdes.o
 COBJS-$(CONFIG_PPC_B4860) += b4860_serdes.o
+COBJS-$(CONFIG_BSC9132) += bsc9132_serdes.o
 
 COBJS-y	+= cpu.o
 COBJS-y	+= cpu_init.o

arch/powerpc/cpu/mpc85xx/b4860_ids.c

@@ -55,11 +55,13 @@ struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
 };
 #endif
 
+#ifdef CONFIG_SYS_SRIO
 struct srio_liodn_id_table srio_liodn_tbl[] = {
 	SET_SRIO_LIODN_1(1, 307),
 	SET_SRIO_LIODN_1(2, 387),
 };
 int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl);
+#endif
 
 struct liodn_id_table liodn_tbl[] = {
 #ifdef CONFIG_SYS_DPAA_QBMAN
@@ -76,10 +78,12 @@ struct liodn_id_table liodn_tbl[] = {
 	SET_DMA_LIODN(1, 147),
 	SET_DMA_LIODN(2, 227),
 
+#ifndef CONFIG_PPC_B4420
 	SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
 	SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
 	SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0),
 	SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0),
+#endif
 
 	/* SET_NEXUS_LIODN(557), -- not yet implemented */
 };
@@ -93,8 +97,10 @@ struct liodn_id_table fman1_liodn_tbl[] = {
 	SET_FMAN_RX_1G_LIODN(1, 3, 91),
 	SET_FMAN_RX_1G_LIODN(1, 4, 92),
 	SET_FMAN_RX_1G_LIODN(1, 5, 93),
+#ifndef CONFIG_PPC_B4420
 	SET_FMAN_RX_10G_LIODN(1, 0, 94),
 	SET_FMAN_RX_10G_LIODN(1, 1, 95),
+#endif
 };
 int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
 #endif

arch/powerpc/cpu/mpc85xx/b4860_serdes.c

@@ -31,6 +31,7 @@ struct serdes_config {
 	u8 lanes[SRDS_MAX_LANES];
 };
 
+#ifdef CONFIG_PPC_B4860
 static struct serdes_config serdes1_cfg_tbl[] = {
 	/* SerDes 1 */
 	{0x0D, {CPRI8, CPRI7, CPRI6, CPRI5,
@@ -41,6 +42,12 @@ static struct serdes_config serdes1_cfg_tbl[] = {
 		CPRI4, CPRI3, CPRI2, CPRI1}},
 	{0x2a, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
 		CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
+	{0x2C, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+		CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
+	{0x2D, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+		CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
+	{0x2E, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+		CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
 	{0x30, {AURORA, AURORA,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
 		CPRI4, CPRI3, CPRI2, CPRI1}},
@@ -84,6 +91,8 @@ static struct serdes_config serdes2_cfg_tbl[] = {
 	{0x4E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SGMII_FM1_DTSEC3, AURORA,
 		SRIO1, SRIO1, SRIO1, SRIO1}},
+	{0x7A, {SRIO2, SRIO2, SRIO2, SRIO2,
+		SRIO1, SRIO1, SRIO1, SRIO1}},
 	{0x84, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SRIO2, SRIO2, AURORA, AURORA,
 		XFI_FM1_MAC9, XFI_FM1_MAC10}},
@@ -94,6 +103,9 @@ static struct serdes_config serdes2_cfg_tbl[] = {
 		SRIO2, SRIO2,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
 		XFI_FM1_MAC9, XFI_FM1_MAC10}},
+	{0x8D, {SRIO2, SRIO2, SRIO2, SRIO2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		XFI_FM1_MAC9, XFI_FM1_MAC10}},
 	{0x93, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
 		XAUI_FM1_MAC10, XAUI_FM1_MAC10,
@@ -111,8 +123,56 @@ static struct serdes_config serdes2_cfg_tbl[] = {
 	{0xC3, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
 		XAUI_FM1_MAC9, XAUI_FM1_MAC9,
 		SRIO1, SRIO1, SRIO1, SRIO1}},
+	{0x98, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+		XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+		XAUI_FM1_MAC10, XAUI_FM1_MAC10,
+		XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
 	{}
 };
+#endif
+
+#ifdef CONFIG_PPC_B4420
+static struct serdes_config serdes1_cfg_tbl[] = {
+	{0x0D, {NONE, NONE, CPRI6, CPRI5,
+		CPRI4, CPRI3, NONE, NONE} },
+	{0x0E, {NONE, NONE, CPRI8, CPRI5,
+		CPRI4, CPRI3, NONE, NONE} },
+	{0x0F, {NONE, NONE, CPRI6, CPRI5,
+		CPRI4, CPRI3, NONE, NONE} },
+	{0x18, {NONE, NONE,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		NONE, NONE, NONE, NONE} },
+	{0x1B, {NONE, NONE,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		NONE, NONE, NONE, NONE} },
+	{0x1E, {NONE, NONE, AURORA, AURORA,
+		NONE, NONE, NONE, NONE} },
+	{0x21, {NONE, NONE, AURORA, AURORA,
+		NONE, NONE, NONE, NONE} },
+	{0x3E, {NONE, NONE, CPRI6, CPRI5,
+		CPRI4, CPRI3, NONE, NONE} },
+	{}
+};
+static struct serdes_config serdes2_cfg_tbl[] = {
+	{0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, AURORA,
+		NONE, NONE, NONE, NONE} },
+	{0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, AURORA,
+		NONE, NONE, NONE, NONE} },
+	{0x6F, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		AURORA, AURORA,	NONE, NONE, NONE, NONE} },
+	{0x70, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		AURORA, AURORA,	NONE, NONE, NONE, NONE} },
+	{0x9A, {PCIE1, PCIE1,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		NONE, NONE, NONE, NONE} },
+	{0x9E, {PCIE1, PCIE1, PCIE1, PCIE1,
+		NONE, NONE, NONE, NONE} },
+	{}
+};
+#endif
+
 static struct serdes_config *serdes_cfg_tbl[] = {
 	serdes1_cfg_tbl,
 	serdes2_cfg_tbl,

arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c

@@ -0,0 +1,96 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ * Author: Prabhakar Kushwaha <prabhakar@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_serdes.h>
+
+#define SRDS1_MAX_LANES		4
+
+static u32 serdes1_prtcl_map;
+
+static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
+	 [0] = {NONE, NONE, NONE, NONE},
+	 [1] = {PCIE1, PCIE2, CPRI2, CPRI1},
+	 [2] = {PCIE1, PCIE2, CPRI2, CPRI1},
+	 [3] = {PCIE1, PCIE2, CPRI2, CPRI1},
+	 [4] = {PCIE1, PCIE2, CPRI2, CPRI1},
+	 [5] = {PCIE1, PCIE2, CPRI2, CPRI1},
+	 [6] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+	 [7] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+	 [8] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+	 [9] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+	[10] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+	[11] = {PCIE1, PCIE2, SGMII_TSEC1, SGMII_TSEC2},
+	[12] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+	[13] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+	[14] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+	[15] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+	[16] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+	[17] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+	[18] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+	[19] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+	[20] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+	[21] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+	[22] = {PCIE1, PCIE2, CPRI2, CPRI1},
+	[23] = {PCIE1, PCIE2, CPRI2, CPRI1},
+	[24] = {PCIE1, PCIE2, CPRI2, CPRI1},
+	[25] = {PCIE1, PCIE2, CPRI2, CPRI1},
+	[26] = {PCIE1, PCIE2, CPRI2, CPRI1},
+	[27] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+	[28] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+	[29] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+	[30] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+	[31] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+	[32] = {PCIE1, PCIE2, SGMII_TSEC1, SGMII_TSEC2},
+	[33] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+	[34] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+	[35] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+	[36] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+	[37] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+	[38] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+	[39] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+	[40] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+	[41] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+	[42] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+	[43] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
+	[44] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
+	[45] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
+	[46] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
+	[47] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
+};
+
+int is_serdes_configured(enum srds_prtcl prtcl)
+{
+	return (1 << prtcl) & serdes1_prtcl_map;
+}
+
+void fsl_serdes_init(void)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 pordevsr = in_be32(&gur->pordevsr);
+	u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
+				MPC85xx_PORDEVSR_IO_SEL_SHIFT;
+	int lane;
+
+	debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
+
+	if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
+		printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
+		return;
+	}
+
+	for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
+		enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
+		serdes1_prtcl_map |= (1 << lane_prtcl);
+	}
+}

arch/powerpc/cpu/mpc85xx/cmd_errata.c

@@ -240,6 +240,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #ifdef CONFIG_SYS_FSL_ERRATUM_A_004934
 	puts("Work-around for Erratum A004934 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A005871
+	if (IS_SVR_REV(svr, 1, 0))
+		puts("Work-around for Erratum A005871 enabled\n");
+#endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_A004849
 	/* This work-around is implemented in PBI, so just check for it */
 	check_erratum_a4849(svr);

arch/powerpc/cpu/mpc85xx/commproc.c

@@ -43,8 +43,8 @@ m8560_cpm_reset(void)
 
 	/* Reclaim the DP memory for our use.
 	*/
-	gd->dp_alloc_base = CPM_DATAONLY_BASE;
-	gd->dp_alloc_top = gd->dp_alloc_base + CPM_DATAONLY_SIZE;
+	gd->arch.dp_alloc_base = CPM_DATAONLY_BASE;
+	gd->arch.dp_alloc_top = gd->arch.dp_alloc_base + CPM_DATAONLY_SIZE;
 
 	/*
 	 * Reset CPM
@@ -69,21 +69,22 @@ m8560_cpm_dpalloc(uint size, uint align)
 	uint	savebase;
 
 	align_mask = align - 1;
-	savebase = gd->dp_alloc_base;
+	savebase = gd->arch.dp_alloc_base;
 
-	if ((off = (gd->dp_alloc_base & align_mask)) != 0)
-		gd->dp_alloc_base += (align - off);
+	off = gd->arch.dp_alloc_base & align_mask;
+	if (off != 0)
+		gd->arch.dp_alloc_base += (align - off);
 
 	if ((off = size & align_mask) != 0)
 		size += align - off;
 
-	if ((gd->dp_alloc_base + size) >= gd->dp_alloc_top) {
-		gd->dp_alloc_base = savebase;
+	if ((gd->arch.dp_alloc_base + size) >= gd->arch.dp_alloc_top) {
+		gd->arch.dp_alloc_base = savebase;
 		panic("m8560_cpm_dpalloc: ran out of dual port ram!");
 	}
 
-	retloc = gd->dp_alloc_base;
-	gd->dp_alloc_base += size;
+	retloc = gd->arch.dp_alloc_base;
+	gd->arch.dp_alloc_base += size;
 
 	memset((void *)&(cpm->im_dprambase[retloc]), 0, size);
 
@@ -110,7 +111,7 @@ m8560_cpm_hostalloc(uint size, uint align)
  * Baud rate clocks are zero-based in the driver code (as that maps
  * to port numbers).  Documentation uses 1-based numbering.
  */
-#define BRG_INT_CLK	gd->brg_clk
+#define BRG_INT_CLK	gd->arch.brg_clk
 #define BRG_UART_CLK	((BRG_INT_CLK + 15) / 16)
 
 /* This function is used by UARTS, or anything else that uses a 16x

arch/powerpc/cpu/mpc85xx/cpu.c

@@ -104,7 +104,7 @@ int checkcpu (void)
 		puts("CPU:   ");
 	}
 
-	cpu = gd->cpu;
+	cpu = gd->arch.cpu;
 
 	puts(cpu->name);
 	if (IS_E_PROCESSOR(svr))

arch/powerpc/cpu/mpc85xx/cpu_init.c

@@ -312,19 +312,33 @@ int enable_cluster_l2(void)
 
 	/* Look through the remaining clusters, and set up their caches */
 	do {
+		int j, cluster_valid = 0;
+
 		l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
+
 		cluster = in_be32(&gur->tp_cluster[i].lower);
 
-		/* set stash ID to (cluster) * 2 + 32 + 1 */
-		clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
+		/* check that at least one core/accel is enabled in cluster */
+		for (j = 0; j < 4; j++) {
+			u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK;
+			u32 type = in_be32(&gur->tp_ityp[idx]);
+
+			if (type & TP_ITYP_AV)
+				cluster_valid = 1;
+		}
 
-		printf("enable l2 for cluster %d %p\n", i, l2cache);
+		if (cluster_valid) {
+			/* set stash ID to (cluster) * 2 + 32 + 1 */
+			clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
 
-		out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
-		while ((in_be32(&l2cache->l2csr0) &
-			(L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
-			;
-		out_be32(&l2cache->l2csr0, L2CSR0_L2E);
+			printf("enable l2 for cluster %d %p\n", i, l2cache);
+
+			out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
+			while ((in_be32(&l2cache->l2csr0)
+				& (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
+					;
+			out_be32(&l2cache->l2csr0, L2CSR0_L2E);
+		}
 		i++;
 	} while (!(cluster & TP_CLUSTER_EOC));
 
@@ -534,6 +548,20 @@ skip_l2:
 	/* needs to be in ram since code uses global static vars */
 	fsl_serdes_init();
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A005871
+	if (IS_SVR_REV(svr, 1, 0)) {
+		int i;
+		__be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c;
+
+		for (i = 0; i < 12; i++) {
+			p += i + (i > 5 ? 11 : 0);
+			out_be32(p, 0x2);
+		}
+		p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108;
+		out_be32(p, 0x34);
+	}
+#endif
+
 #ifdef CONFIG_SYS_SRIO
 	srio_init();
 #ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER