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@@ -80,6 +80,26 @@ int interrupt_init(void)
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{
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{
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int ret;
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int ret;
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+ /*
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+ * The IRQ0 on Rev 2 is pulled high (low in Rev 1.x) to
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+ * implement PEX10 errata. As INT is active high, it
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+ * will cause core to take 0x500 interrupt.
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+ *
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+ * Due to the PIC's default pass through mode, as soon
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+ * as interrupts are enabled (MSR[EE] = 1), an interrupt
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+ * will be taken and u-boot will hang. This is due to a
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+ * hardware change (per an errata fix) on new revisions
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+ * of the board with Rev 2.x parts.
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+ *
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+ * Setting the PIC to mixed mode prevents the hang.
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+ */
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+ if ((get_svr() & 0xf0) == 0x20) {
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+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
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+ immr->im_pic.gcr = MPC86xx_PICGCR_RST;
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+ while (immr->im_pic.gcr & MPC86xx_PICGCR_RST);
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+ immr->im_pic.gcr = MPC86xx_PICGCR_MODE;
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+ }
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+
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/* call cpu specific function from $(CPU)/interrupts.c */
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/* call cpu specific function from $(CPU)/interrupts.c */
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ret = interrupt_init_cpu(&decrementer_count);
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ret = interrupt_init_cpu(&decrementer_count);
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