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ppc4xx: Fix sending type 1 PCI transactions

The list of 4xx SoCs that should send type 1 PCI transactions
is not defined correctly. As a result PCI-PCI bridges and devices
behind them are not identified. The following 4xx variants should
send type 1 transactions: 440GX, 440GP, 440SP, 440SPE, 460EX and 460GT.

Signed-off-by: Felix Radensky <felix@embedded-sol.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Felix Radensky 15 years ago
parent
57ae8a5cce
commit
97c9f29008
1 changed files with 2 additions and 1 deletions
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  1. 2 1
      drivers/pci/pci_indirect.c

+ 2 - 1
drivers/pci/pci_indirect.c
View File 

@@ -59,7 +59,8 @@ indirect_##rw##_config_##size(struct pci_controller *hose,               \
 
 	cfg_##rw(val, hose->cfg_data + (offset & mask), type, op);       \
 
 	cfg_##rw(val, hose->cfg_data + (offset & mask), type, op);       \
 
 	return 0;                                                        \
 
 	return 0;                                                        \
 
 }
 
 }
 
-#elif defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SPE)
 
+#elif defined(CONFIG_440GX)  || defined(CONFIG_440GP) || defined(CONFIG_440SP) || \
 
+      defined(CONFIG_440SPE) || defined(CONFIG_460EX) || defined(CONFIG_460GT)
 
 #define INDIRECT_PCI_OP(rw, size, type, op, mask)			 \
 
 #define INDIRECT_PCI_OP(rw, size, type, op, mask)			 \
 
 static int								 \
 
 static int								 \
 
 indirect_##rw##_config_##size(struct pci_controller *hose,		 \
 
 indirect_##rw##_config_##size(struct pci_controller *hose,		 \