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+/*
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+ * (C) Copyright 2000-2003
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+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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+ *
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+ * See file CREDITS for list of people who contributed to this
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+ * project.
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License as
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+ * published by the Free Software Foundation; either version 2 of
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+ * the License, or (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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+ * MA 02111-1307 USA
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+ */
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+
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+#include <common.h>
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+
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+#if defined(CONFIG_PCI) && defined(CONFIG_MPC5200)
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+
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+#include <asm/processor.h>
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+#include <asm/io.h>
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+#include <pci.h>
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+#include <mpc5xxx.h>
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+
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+/* System RAM mapped over PCI */
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+#define CONFIG_PCI_MEMORY_BUS CFG_SDRAM_BASE
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+#define CONFIG_PCI_MEMORY_PHYS CFG_SDRAM_BASE
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+#define CONFIG_PCI_MEMORY_SIZE (1024 * 1024 * 1024)
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+
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+/* PCIIWCR bit fields */
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+#define IWCR_MEM (0 << 3)
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+#define IWCR_IO (1 << 3)
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+#define IWCR_READ (0 << 1)
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+#define IWCR_READLINE (1 << 1)
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+#define IWCR_READMULT (2 << 1)
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+#define IWCR_EN (1 << 0)
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+
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+static int mpc5200_read_config_dword(struct pci_controller *hose,
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+ pci_dev_t dev, int offset, u32* value)
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+{
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+ *(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset;
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+ eieio();
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+ *value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS);
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+ eieio();
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+ *(volatile u32 *)MPC5XXX_PCI_CAR = 0;
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+ /* skip MPC5200 */
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+ if (offset == 0 && *value == 0x58031057)
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+ *value = 0xffffffff;
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+ return 0;
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+}
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+
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+static int mpc5200_write_config_dword(struct pci_controller *hose,
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+ pci_dev_t dev, int offset, u32 value)
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+{
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+ *(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset;
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+ eieio();
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+ out_le32((volatile u32 *)CONFIG_PCI_IO_PHYS, value);
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+ eieio();
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+ *(volatile u32 *)MPC5XXX_PCI_CAR = 0;
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+ return 0;
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+}
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+
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+void pci_mpc5xxx_init (struct pci_controller *hose)
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+{
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+ hose->first_busno = 0;
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+ hose->last_busno = 0xff;
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+
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+ /* System space */
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+ pci_set_region(hose->regions + 0,
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+ CONFIG_PCI_MEMORY_BUS,
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+ CONFIG_PCI_MEMORY_PHYS,
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+ CONFIG_PCI_MEMORY_SIZE,
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+ PCI_REGION_MEM | PCI_REGION_MEMORY);
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+
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+ /* PCI memory space */
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+ pci_set_region(hose->regions + 1,
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+ CONFIG_PCI_MEM_BUS,
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+ CONFIG_PCI_MEM_PHYS,
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+ CONFIG_PCI_MEM_SIZE,
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+ PCI_REGION_MEM);
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+
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+ /* PCI IO space */
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+ pci_set_region(hose->regions + 2,
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+ CONFIG_PCI_IO_BUS,
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+ CONFIG_PCI_IO_PHYS,
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+ CONFIG_PCI_IO_SIZE,
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+ PCI_REGION_IO);
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+
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+ hose->region_count = 3;
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+
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+ pci_register_hose(hose);
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+
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+ /* GPIO Multiplexing - enable PCI */
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+ *(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~(1 << 15);
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+
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+ /* Set host bridge as pci master and enable memory decoding */
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+ *(vu_long *)MPC5XXX_PCI_CMD |=
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+ PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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+
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+ /* Set maximum latency timer */
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+ *(vu_long *)MPC5XXX_PCI_CFG |= (0xf800);
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+
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+ /* Set cache line size */
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+ *(vu_long *)MPC5XXX_PCI_CFG = (*(vu_long *)MPC5XXX_PCI_CFG & ~0xff) |
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+ (CFG_CACHELINE_SIZE / 4);
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+
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+ /* Map MBAR to PCI space */
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+ *(vu_long *)MPC5XXX_PCI_BAR0 = CFG_MBAR;
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+ *(vu_long *)MPC5XXX_PCI_TBATR1 = CFG_MBAR | 1;
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+
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+ /* Map RAM to PCI space */
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+ *(vu_long *)MPC5XXX_PCI_BAR1 = CONFIG_PCI_MEMORY_BUS | (1 << 3);
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+ *(vu_long *)MPC5XXX_PCI_TBATR1 = CONFIG_PCI_MEMORY_PHYS | 1;
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+
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+ /* Enable snooping for RAM */
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+ *(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 15);
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+ *(vu_long *)(MPC5XXX_XLBARB + 0x70) = CONFIG_PCI_MEMORY_PHYS | 0x1d;
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+
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+ /* Park XLB on PCI */
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+ *(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~((7 << 8) | (3 << 5));
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+ *(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (3 << 8) | (3 << 5);
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+
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+ /* Enable piplining */
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+ *(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~(1 << 31);
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+
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+ /* Disable interrupts from PCI controller */
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+ *(vu_long *)MPC5XXX_PCI_GSCR &= ~(7 << 12);
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+ *(vu_long *)MPC5XXX_PCI_ICR &= ~(7 << 24);
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+
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+ /* Disable initiator windows */
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+ *(vu_long *)MPC5XXX_PCI_IWCR = 0;
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+
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+ /* Map PCI memory to physical space */
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+ *(vu_long *)MPC5XXX_PCI_IW0BTAR = CONFIG_PCI_MEM_PHYS |
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+ (((CONFIG_PCI_MEM_SIZE - 1) >> 8) & 0x00ff0000) |
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+ (CONFIG_PCI_MEM_BUS >> 16);
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+ *(vu_long *)MPC5XXX_PCI_IWCR |= (IWCR_MEM | IWCR_READ | IWCR_EN) << 24;
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+
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+ /* Map PCI I/O to physical space */
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+ *(vu_long *)MPC5XXX_PCI_IW1BTAR = CONFIG_PCI_IO_PHYS |
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+ (((CONFIG_PCI_IO_SIZE - 1) >> 8) & 0x00ff0000) |
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+ (CONFIG_PCI_IO_BUS >> 16);
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+ *(vu_long *)MPC5XXX_PCI_IWCR |= (IWCR_IO | IWCR_READ | IWCR_EN) << 16;
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+
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+ /* Reset the PCI bus */
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+ *(vu_long *)MPC5XXX_PCI_GSCR |= 1;
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+ udelay(1000);
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+ *(vu_long *)MPC5XXX_PCI_GSCR &= ~1;
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+ udelay(1000);
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+
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+ pci_set_ops(hose,
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+ pci_hose_read_config_byte_via_dword,
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+ pci_hose_read_config_word_via_dword,
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+ mpc5200_read_config_dword,
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+ pci_hose_write_config_byte_via_dword,
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+ pci_hose_write_config_word_via_dword,
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+ mpc5200_write_config_dword);
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+
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+ udelay(1000);
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+
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+#ifdef CONFIG_PCI_SCAN_SHOW
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+ printf("PCI: Bus Dev VenId DevId Class Int\n");
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+#endif
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+
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+ hose->last_busno = pci_hose_scan(hose);
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+}
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+#endif /* CONFIG_PCI && CONFIG_MPC5200 */
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wdenk