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+/*
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+ * (C) Copyright 2010
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+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
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+ *
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+ * See file CREDITS for list of people who contributed to this
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+ * project.
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License as
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+ * published by the Free Software Foundation; either version 2 of
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+ * the License, or (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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+ * MA 02111-1307 USA
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+ *
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+ */
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+
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+#include <common.h>
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+#include <ppc4xx.h>
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+#include <asm/processor.h>
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+#include <asm/io.h>
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+#include <asm/cache.h>
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+
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+#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR) || \
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+ defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
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+#if defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC)
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+
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+#if defined(CONFIG_405EX)
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+/*
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+ * Currently only 405EX uses 16bit data bus width as an alternative
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+ * option to 32bit data width (SDRAM0_MCOPT1_WDTH)
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+ */
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+#define SDRAM_DATA_ALT_WIDTH 2
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+#else
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+#define SDRAM_DATA_ALT_WIDTH 8
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+#endif
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+
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+#if defined(CONFIG_SYS_OCM_BASE)
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+#define CONFIG_FUNC_ISRAM_ADDR CONFIG_SYS_OCM_BASE
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+#endif
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+
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+#if defined(CONFIG_SYS_ISRAM_BASE)
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+#define CONFIG_FUNC_ISRAM_ADDR CONFIG_SYS_ISRAM_BASE
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+#endif
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+
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+#if !defined(CONFIG_FUNC_ISRAM_ADDR)
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+#error "No internal SRAM/OCM provided!"
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+#endif
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+
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+#define force_inline inline __attribute__ ((always_inline))
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+
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+static inline void machine_check_disable(void)
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+{
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+ mtmsr(mfmsr() & ~MSR_ME);
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+}
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+
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+static inline void machine_check_enable(void)
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+{
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+ mtmsr(mfmsr() | MSR_ME);
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+}
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+
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+/*
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+ * These helper functions need to be inlined, since they
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+ * are called from the functions running from internal SRAM.
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+ * SDRAM operation is forbidden at that time, so calling
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+ * functions in SDRAM has to be avoided.
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+ */
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+static force_inline void wait_ddr_idle(void)
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+{
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+ u32 val;
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+
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+ do {
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+ mfsdram(SDRAM_MCSTAT, val);
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+ } while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT);
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+}
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+
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+static force_inline void recalibrate_ddr(void)
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+{
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+ u32 val;
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+
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+ /*
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+ * Rewrite RQDC & RFDC to calibrate again. If this is not
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+ * done, the SDRAM controller is working correctly after
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+ * changing the MCOPT1_MCHK bits.
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+ */
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+ mfsdram(SDRAM_RQDC, val);
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+ mtsdram(SDRAM_RQDC, val);
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+ mfsdram(SDRAM_RFDC, val);
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+ mtsdram(SDRAM_RFDC, val);
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+}
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+
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+static force_inline void set_mcopt1_mchk(u32 bits)
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+{
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+ u32 val;
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+
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+ wait_ddr_idle();
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+ mfsdram(SDRAM_MCOPT1, val);
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+ mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) | bits);
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+ recalibrate_ddr();
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+}
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+
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+/*
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+ * The next 2 functions are copied to internal SRAM/OCM and run
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+ * there. No function calls allowed here. No SDRAM acitivity should
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+ * be done here.
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+ */
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+static void inject_ecc_error(void *ptr, int par)
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+{
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+ u32 val;
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+
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+ /*
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+ * Taken from PPC460EX/EXr/GT users manual (Rev 1.21)
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+ * 22.2.17.13 ECC Diagnostics
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+ *
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+ * Items 1 ... 5 are already done by now, running from RAM
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+ * with ECC enabled
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+ */
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+
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+ out_be32(ptr, 0x00000000);
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+ val = in_be32(ptr);
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+
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+ /* 6. Set memory controller to no error checking */
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+ set_mcopt1_mchk(SDRAM_MCOPT1_MCHK_NON);
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+
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+ /* 7. Modify one or two bits for error simulation */
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+ if (par == 1)
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+ out_be32(ptr, in_be32(ptr) ^ 0x00000001);
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+ else
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+ out_be32(ptr, in_be32(ptr) ^ 0x00000003);
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+
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+ /* 8. Wait for SDRAM idle */
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+ val = in_be32(ptr);
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+ set_mcopt1_mchk(SDRAM_MCOPT1_MCHK_CHK_REP);
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+
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+ /* Wait for SDRAM idle */
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+ wait_ddr_idle();
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+
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+ /* Continue with 9. in calling function... */
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+}
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+
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+static void rewrite_ecc_parity(void *ptr, int par)
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+{
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+ u32 current_address = (u32)ptr;
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+ u32 end_address;
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+ u32 address_increment;
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+ u32 mcopt1;
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+ u32 val;
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+
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+ /*
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+ * Fill ECC parity byte again. Otherwise further accesses to
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+ * the failure address will result in exceptions.
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+ */
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+
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+ /* Wait for SDRAM idle */
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+ val = in_be32(0x00000000);
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+ set_mcopt1_mchk(SDRAM_MCOPT1_MCHK_GEN);
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+
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+ /* ECC bit set method for non-cached memory */
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+ mfsdram(SDRAM_MCOPT1, mcopt1);
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+ if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32)
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+ address_increment = 4;
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+ else
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+ address_increment = SDRAM_DATA_ALT_WIDTH;
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+ end_address = current_address + CONFIG_SYS_CACHELINE_SIZE;
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+
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+ while (current_address < end_address) {
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+ *((unsigned long *)current_address) = 0;
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+ current_address += address_increment;
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+ }
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+
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+ set_mcopt1_mchk(SDRAM_MCOPT1_MCHK_CHK_REP);
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+
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+ /* Wait for SDRAM idle */
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+ wait_ddr_idle();
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+}
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+
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+static int do_ecctest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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+{
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+ u32 old_val;
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+ u32 val;
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+ u32 *ptr;
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+ void (*sram_func)(u32 *, int);
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+ int error;
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+
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+ if (argc < 3) {
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+ cmd_usage(cmdtp);
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+ return 1;
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+ }
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+
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+ ptr = (u32 *)simple_strtoul(argv[1], NULL, 16);
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+ error = simple_strtoul(argv[2], NULL, 16);
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+ if ((error < 1) || (error > 2)) {
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+ cmd_usage(cmdtp);
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+ return 1;
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+ }
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+
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+ printf("Using address %p for %d bit ECC error injection\n",
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+ ptr, error);
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+
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+ /*
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+ * Save value to restore it later on
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+ */
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+ old_val = in_be32(ptr);
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+
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+ /*
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+ * Copy ECC injection function into internal SRAM/OCM
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+ */
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+ sram_func = (void *)CONFIG_FUNC_ISRAM_ADDR;
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+ memcpy((void *)CONFIG_FUNC_ISRAM_ADDR, inject_ecc_error, 0x10000);
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+
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+ /*
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+ * Disable interrupts and exceptions before calling this
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+ * function in internal SRAM/OCM
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+ */
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+ disable_interrupts();
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+ machine_check_disable();
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+ eieio();
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+
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+ /*
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+ * Jump to ECC simulation function in internal SRAM/OCM
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+ */
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+ (*sram_func)(ptr, error);
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+
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+ /* 10. Read the corresponding address */
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+ val = in_be32(ptr);
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+
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+ /*
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+ * Read and print ECC status register/info:
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+ * The faulting address is only known upon uncorrectable ECC
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+ * errors.
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+ */
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+ mfsdram(SDRAM_ECCES, val);
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+ if (val & SDRAM_ECCES_CE)
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+ printf("ECC: Correctable error\n");
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+ if (val & SDRAM_ECCES_UE) {
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+ printf("ECC: Uncorrectable error at 0x%02x%08x\n",
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+ mfdcr(SDRAM_ERRADDULL), mfdcr(SDRAM_ERRADDLLL));
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+ }
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+
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+ /*
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+ * Clear pending interrupts/exceptions
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+ */
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+ mtsdram(SDRAM_ECCES, 0xffffffff);
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+ mtdcr(SDRAM_ERRSTATLL, 0xff000000);
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+ set_mcsr(get_mcsr());
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+
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+ /* Now enable interrupts and exceptions again */
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+ eieio();
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+ machine_check_enable();
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+ enable_interrupts();
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+
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+ /*
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+ * The ECC parity byte need to be re-written for the
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+ * corresponding address. Otherwise future accesses to it
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+ * will result in exceptions.
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+ *
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+ * Jump to ECC parity generation function
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+ */
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+ memcpy((void *)CONFIG_FUNC_ISRAM_ADDR, rewrite_ecc_parity, 0x10000);
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+ (*sram_func)(ptr, 0);
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+
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+ /*
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+ * Restore value in corresponding address
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+ */
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+ out_be32(ptr, old_val);
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+
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+ return 0;
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+}
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+
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+U_BOOT_CMD(
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+ ecctest, 3, 0, do_ecctest,
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+ "Test ECC by single and double error bit injection",
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+ "address 1/2"
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+);
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+
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+#endif /* defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC) */
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+#endif /* defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)... */
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Wolfgang Denk