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@@ -1570,8 +1570,8 @@
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#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */
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#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */
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#if defined(CONFIG_440GX)
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-#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 0 Channel table pointer reg */
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-#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 1 Channel table pointer reg */
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+#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table pointer reg */
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+#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table pointer reg */
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#endif /* CONFIG_440GX */
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#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
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#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */
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