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@@ -0,0 +1,87 @@
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+/*
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+ * Copyright (c) 2011-2013 Xilinx Inc.
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+ *
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+ * See file CREDITS for list of people who contributed to this
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+ * project.
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License as
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+ * published by the Free Software Foundation; either version 2 of
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+ * the License, or (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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+ * MA 02111-1307 USA
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+ */
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+
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+#include <common.h>
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+#include <asm/io.h>
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+#include <asm/microblaze_intc.h>
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+#include <asm/processor.h>
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+#include <watchdog.h>
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+
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+#define XWT_CSR0_WRS_MASK 0x00000008 /* Reset status Mask */
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+#define XWT_CSR0_WDS_MASK 0x00000004 /* Timer state Mask */
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+#define XWT_CSR0_EWDT1_MASK 0x00000002 /* Enable bit 1 Mask*/
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+#define XWT_CSRX_EWDT2_MASK 0x00000001 /* Enable bit 2 Mask */
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+
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+struct watchdog_regs {
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+ u32 twcsr0; /* 0x0 */
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+ u32 twcsr1; /* 0x4 */
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+ u32 tbr; /* 0x8 */
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+};
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+
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+static struct watchdog_regs *watchdog_base =
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+ (struct watchdog_regs *)CONFIG_WATCHDOG_BASEADDR;
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+
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+void hw_watchdog_reset(void)
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+{
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+ u32 reg;
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+
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+ /* Read the current contents of TCSR0 */
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+ reg = readl(&watchdog_base->twcsr0);
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+
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+ /* Clear the watchdog WDS bit */
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+ if (reg & (XWT_CSR0_EWDT1_MASK | XWT_CSRX_EWDT2_MASK))
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+ writel(reg | XWT_CSR0_WDS_MASK, &watchdog_base->twcsr0);
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+}
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+
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+void hw_watchdog_disable(void)
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+{
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+ u32 reg;
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+
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+ /* Read the current contents of TCSR0 */
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+ reg = readl(&watchdog_base->twcsr0);
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+
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+ writel(reg & ~XWT_CSR0_EWDT1_MASK, &watchdog_base->twcsr0);
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+ writel(~XWT_CSRX_EWDT2_MASK, &watchdog_base->twcsr1);
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+
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+ puts("Watchdog disabled!\n");
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+}
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+
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+static void hw_watchdog_isr(void *arg)
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+{
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+ hw_watchdog_reset();
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+}
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+
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+int hw_watchdog_init(void)
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+{
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+ int ret;
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+
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+ writel((XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK | XWT_CSR0_EWDT1_MASK),
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+ &watchdog_base->twcsr0);
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+ writel(XWT_CSRX_EWDT2_MASK, &watchdog_base->twcsr1);
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+
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+ ret = install_interrupt_handler(CONFIG_WATCHDOG_IRQ,
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+ hw_watchdog_isr, NULL);
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+ if (ret)
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+ return 1;
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+
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+ return 0;
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+}
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Tom Rini