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@@ -25,6 +25,8 @@
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#include <asm/arch/hardware.h>
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#include <asm/io.h>
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+DECLARE_GLOBAL_DATA_PTR;
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+
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/* offsets from PLL controller base */
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#define PLLC_PLLCTL 0x100
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#define PLLC_PLLM 0x110
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@@ -187,6 +189,36 @@ unsigned int davinci_clk_get(unsigned int div)
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#endif
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#endif /* !CONFIG_SOC_DA8XX */
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+int set_cpu_clk_info(void)
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+{
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+#ifdef CONFIG_SOC_DA8XX
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+ gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000;
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+ /* DDR PHY uses an x2 input clock */
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+ gd->bd->bi_ddr_freq = clk_get(0x10001) / 1000000;
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+#else
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+
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+ unsigned int pllbase = DAVINCI_PLL_CNTRL0_BASE;
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+#if defined(CONFIG_SOC_DM365)
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+ pllbase = DAVINCI_PLL_CNTRL1_BASE;
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+#endif
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+ gd->bd->bi_arm_freq = pll_sysclk_mhz(pllbase, ARM_PLLDIV);
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+
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+#ifdef DSP_PLLDIV
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+ gd->bd->bi_dsp_freq =
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+ pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV);
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+#else
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+ gd->bd->bi_dsp_freq = 0;
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+#endif
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+
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+ pllbase = DAVINCI_PLL_CNTRL1_BASE;
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+#if defined(CONFIG_SOC_DM365)
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+ pllbase = DAVINCI_PLL_CNTRL0_BASE;
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+#endif
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+ gd->bd->bi_ddr_freq = pll_sysclk_mhz(pllbase, DDR_PLLDIV) / 2;
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+#endif
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+ return 0;
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+}
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+
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/*
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* Initializes on-chip ethernet controllers.
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* to override, implement board_eth_init()
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