Merge branch 'master' of git://git.denx.de/u-boot-mips

arch/mips/config.mk

@@ -23,7 +23,21 @@
 
 CROSS_COMPILE ?= mips_4KC-
 
-CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T mips.lds
+# Handle special prefix in ELDK 4.0 toolchain
+ifneq (,$(findstring 4KCle,$(CROSS_COMPILE)))
+ENDIANNESS := -EL
+endif
+
+ifdef CONFIG_SYS_LITTLE_ENDIAN
+ENDIANNESS := -EL
+endif
+
+ifdef CONFIG_SYS_BIG_ENDIAN
+ENDIANNESS := -EB
+endif
+
+# Default to EB if no endianess is configured
+ENDIANNESS ?= -EB
 
 PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__
 
@@ -47,8 +61,8 @@ PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__
 # On the other hand, we want PIC in the U-Boot code to relocate it from ROM
 # to RAM. $28 is always used as gp.
 #
-PLATFORM_CPPFLAGS		+= -G 0 -mabicalls -fpic
+PLATFORM_CPPFLAGS		+= -G 0 -mabicalls -fpic $(ENDIANNESS)
 PLATFORM_CPPFLAGS		+= -msoft-float
-PLATFORM_LDFLAGS		+= -G 0 -static -n -nostdlib
+PLATFORM_LDFLAGS		+= -G 0 -static -n -nostdlib $(ENDIANNESS)
 PLATFORM_RELFLAGS		+= -ffunction-sections -fdata-sections
 LDFLAGS_FINAL			+= --gc-sections

arch/mips/cpu/mips32/config.mk

@@ -29,21 +29,6 @@
 #
 MIPSFLAGS := -march=mips32r2
 
-# Handle special prefix in ELDK 4.0 toolchain
-ifneq (,$(findstring 4KCle,$(CROSS_COMPILE)))
-ENDIANNESS := -EL
-endif
+PLATFORM_CPPFLAGS += $(MIPSFLAGS)
 
-ifdef CONFIG_SYS_LITTLE_ENDIAN
-ENDIANNESS := -EL
-endif
-
-ifdef CONFIG_SYS_BIG_ENDIAN
-ENDIANNESS := -EB
-endif
-
-# Default to EB if no endianess is configured
-ENDIANNESS ?= -EB
-
-PLATFORM_CPPFLAGS += $(MIPSFLAGS) $(ENDIANNESS)
-PLATFORM_LDFLAGS += $(ENDIANNESS)
+CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T mips.lds

arch/mips/cpu/xburst/config.mk

@@ -20,5 +20,6 @@
 # MA 02111-1307 USA
 #
 
-PLATFORM_CPPFLAGS += -march=mips32 -EL
-PLATFORM_LDFLAGS += -EL
+PLATFORM_CPPFLAGS += -march=mips32
+
+CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T mips.lds

arch/mips/cpu/xburst/cpu.c

@@ -62,7 +62,7 @@ void __attribute__((weak)) _machine_restart(void)
 
 	writew(100, &wdt->tdr); /* wdt_set_data(100) */
 	writew(0, &wdt->tcnt); /* wdt_set_count(0); */
-	writew(TCU_TSSR_WDTSC, &tcu->tscr); /* tcu_start_wdt_clock */
+	writel(TCU_TSSR_WDTSC, &tcu->tscr); /* tcu_start_wdt_clock */
 	writeb(readb(&wdt->tcer) | WDT_TCER_TCEN, &wdt->tcer); /* wdt start */
 
 	while (1)

arch/mips/cpu/xburst/timer.c

@@ -34,13 +34,13 @@ static struct jz4740_tcu *tcu = (struct jz4740_tcu *)JZ4740_TCU_BASE;
 void reset_timer_masked(void)
 {
 	/* reset time */
-	gd->lastinc = readw(&tcu->tcnt0);
+	gd->lastinc = readl(&tcu->tcnt0);
 	gd->tbl = 0;
 }
 
 ulong get_timer_masked(void)
 {
-	ulong now = readw(&tcu->tcnt0);
+	ulong now = readl(&tcu->tcnt0);
 
 	if (gd->lastinc <= now)
 		gd->tbl += now - gd->lastinc; /* normal mode */
@@ -83,11 +83,11 @@ void udelay_masked(unsigned long usec)
 
 int timer_init(void)
 {
-	writew(TCU_TCSR_PRESCALE256 | TCU_TCSR_EXT_EN, &tcu->tcsr0);
+	writel(TCU_TCSR_PRESCALE256 | TCU_TCSR_EXT_EN, &tcu->tcsr0);
 
-	writew(0, &tcu->tcnt0);
-	writew(0, &tcu->tdhr0);
-	writew(TIMER_FDATA, &tcu->tdfr0);
+	writel(0, &tcu->tcnt0);
+	writel(0, &tcu->tdhr0);
+	writel(TIMER_FDATA, &tcu->tdfr0);
 
 	/* mask irqs */
 	writel((1 << TIMER_CHAN) | (1 << (TIMER_CHAN + 16)), &tcu->tmsr);

arch/mips/lib/Makefile

@@ -25,6 +25,13 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(ARCH).o
 
+## Build a couple of necessary functions into a private libgcc
+LIBGCC	= $(obj)libgcc.o
+GLSOBJS	+= ashldi3.o
+GLSOBJS	+= ashrdi3.o
+GLSOBJS	+= lshrdi3.o
+LGOBJS	:= $(addprefix $(obj),$(GLSOBJS))
+
 SOBJS-y	+=
 
 COBJS-y	+= board.o
@@ -37,9 +44,22 @@ endif
 SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
 
+# Always build libmips.o
+TARGETS	:= $(LIB)
+
+# Build private libgcc only when asked for
+ifdef USE_PRIVATE_LIBGCC
+TARGETS	+= $(LIBGCC)
+endif
+
+all:	$(TARGETS)
+
 $(LIB):	$(obj).depend $(OBJS)
 	$(call cmd_link_o_target, $(OBJS))
 
+$(LIBGCC): $(obj).depend $(LGOBJS)
+	$(call cmd_link_o_target, $(LGOBJS))
+
 #########################################################################
 
 # defines $(obj).depend target

arch/mips/lib/ashldi3.c

@@ -0,0 +1,25 @@
+#include "libgcc.h"
+
+long long __ashldi3(long long u, word_type b)
+{
+	DWunion uu, w;
+	word_type bm;
+
+	if (b == 0)
+		return u;
+
+	uu.ll = u;
+	bm = 32 - b;
+
+	if (bm <= 0) {
+		w.s.low = 0;
+		w.s.high = (unsigned int) uu.s.low << -bm;
+	} else {
+		const unsigned int carries = (unsigned int) uu.s.low >> bm;
+
+		w.s.low = (unsigned int) uu.s.low << b;
+		w.s.high = ((unsigned int) uu.s.high << b) | carries;
+	}
+
+	return w.ll;
+}

arch/mips/lib/ashrdi3.c

@@ -0,0 +1,27 @@
+#include "libgcc.h"
+
+long long __ashrdi3(long long u, word_type b)
+{
+	DWunion uu, w;
+	word_type bm;
+
+	if (b == 0)
+		return u;
+
+	uu.ll = u;
+	bm = 32 - b;
+
+	if (bm <= 0) {
+		/* w.s.high = 1..1 or 0..0 */
+		w.s.high =
+		    uu.s.high >> 31;
+		w.s.low = uu.s.high >> -bm;
+	} else {
+		const unsigned int carries = (unsigned int) uu.s.high << bm;
+
+		w.s.high = uu.s.high >> b;
+		w.s.low = ((unsigned int) uu.s.low >> b) | carries;
+	}
+
+	return w.ll;
+}

arch/mips/lib/libgcc.h

@@ -0,0 +1,25 @@
+#ifndef __ASM_LIBGCC_H
+#define __ASM_LIBGCC_H
+
+#include <asm/byteorder.h>
+
+typedef int word_type __attribute__ ((mode (__word__)));
+
+#ifdef __BIG_ENDIAN
+struct DWstruct {
+	int high, low;
+};
+#elif defined(__LITTLE_ENDIAN)
+struct DWstruct {
+	int low, high;
+};
+#else
+#error I feel sick.
+#endif
+
+typedef union {
+	struct DWstruct s;
+	long long ll;
+} DWunion;
+
+#endif /* __ASM_LIBGCC_H */

arch/mips/lib/lshrdi3.c

@@ -0,0 +1,25 @@
+#include "libgcc.h"
+
+long long __lshrdi3(long long u, word_type b)
+{
+	DWunion uu, w;
+	word_type bm;
+
+	if (b == 0)
+		return u;
+
+	uu.ll = u;
+	bm = 32 - b;
+
+	if (bm <= 0) {
+		w.s.high = 0;
+		w.s.low = (unsigned int) uu.s.high >> -bm;
+	} else {
+		const unsigned int carries = (unsigned int) uu.s.high << bm;
+
+		w.s.high = (unsigned int) uu.s.high >> b;
+		w.s.low = ((unsigned int) uu.s.low >> b) | carries;
+	}
+
+	return w.ll;
+}

board/qi/qi_lb60/qi_lb60.c

@@ -69,7 +69,7 @@ static void gpio_init(void)
 static void cpm_init(void)
 {
 	struct jz4740_cpm *cpm = (struct jz4740_cpm *)JZ4740_CPM_BASE;
-	uint32_t reg = readw(&cpm->clkgr);
+	uint32_t reg = readl(&cpm->clkgr);
 
 	reg |=	CPM_CLKGR_IPU |
 		CPM_CLKGR_CIM |
@@ -81,7 +81,7 @@ static void cpm_init(void)
 		CPM_CLKGR_UDC |
 		CPM_CLKGR_AIC1;
 
-	writew(reg, &cpm->clkgr);
+	writel(reg, &cpm->clkgr);
 }
 
 int board_early_init_f(void)

boards.cfg

@@ -390,7 +390,8 @@ M5485FFE		     m68k	 mcf547x_8x  m548xevb            freescale      -
 M5485GFE		     m68k        mcf547x_8x  m548xevb            freescale      -           M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=4,SYS_DRAMSZ=64
 M5485HFE		     m68k        mcf547x_8x  m548xevb            freescale      -           M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO
 microblaze-generic           microblaze  microblaze  microblaze-generic  xilinx
-qemu_mips                    mips        mips32      qemu-mips           -              -           qemu-mips
+qemu_mips                    mips        mips32      qemu-mips           -              -           qemu-mips:SYS_BIG_ENDIAN
+qemu_mipsel                  mips        mips32      qemu-mips           -              -           qemu-mips:SYS_LITTLE_ENDIAN
 vct_platinum                 mips        mips32      vct                 micronas       -           vct:VCT_PLATINUM
 vct_platinumavc              mips        mips32      vct                 micronas       -           vct:VCT_PLATINUMAVC
 vct_platinumavc_onenand      mips        mips32      vct                 micronas       -           vct:VCT_PLATINUMAVC,VCT_ONENAND

include/configs/qemu-mips.h

@@ -100,7 +100,12 @@
  */
 #define CONFIG_SYS_LONGHELP				/* undef to save memory */
 
-#define CONFIG_SYS_PROMPT		"qemu-mips # "	/* Monitor Command Prompt */
+/* Monitor Command Prompt */
+#if defined(CONFIG_SYS_LITTLE_ENDIAN)
+#define CONFIG_SYS_PROMPT		"qemu-mipsel # "
+#else
+#define CONFIG_SYS_PROMPT		"qemu-mips # "
+#endif
 
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_CMDLINE_EDITING

include/configs/qi_lb60.h

@@ -11,6 +11,7 @@
 #define __CONFIG_QI_LB60_H
 
 #define CONFIG_MIPS32		/* MIPS32 CPU core */
+#define CONFIG_SYS_LITTLE_ENDIAN
 #define CONFIG_JZSOC		/* Jz SoC */
 #define CONFIG_JZ4740		/* Jz4740 SoC */
 #define CONFIG_NAND_JZ4740