Coding Style cleanup

CHANGELOG

@@ -2,6 +2,8 @@
 Changes since U-Boot 1.1.4:
 ======================================================================
 
+* Coding Style cleanup
+
 * Avoid dereferencing NULL in find_cmd() if no valid commands were found
   Patch by Andrew Dyer, 13 Jun 2005
 
@@ -34,7 +36,7 @@ Changes since U-Boot 1.1.4:
 * Add support for Adder boards with 16MB SDRAM;
   add support for second FEC on Adder87x board.
   Patch by Yuli Barcohen, 05 Jun 2005
-  
+
 * Fix conditional for including ks8695eth driver
   Patch by Greg Ungerer, 04 Jun 2005
 

Makefile

@@ -1899,7 +1899,7 @@ clean:
 	rm -f tools/env/fw_printenv tools/env/fw_setenv
 	rm -f board/cray/L1/bootscript.c board/cray/L1/bootscript.image
 	rm -f board/netstar/eeprom board/netstar/crcek
-	rm -f board/netstar/*.srec board/netstar/*.bin 
+	rm -f board/netstar/*.srec board/netstar/*.bin
 	rm -f board/trab/trab_fkt board/voiceblue/eeprom
 	rm -f board/integratorap/u-boot.lds board/integratorcp/u-boot.lds
 

board/ezkit533/config.mk

@@ -23,4 +23,3 @@
 
 TEXT_BASE = 0x01FC0000
 PLATFORM_CPPFLAGS += -I$(TOPDIR)
-

board/ezkit533/flash.c

@@ -142,15 +142,15 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
 	int prot,sect;
 
 	prot = 0;
-        for (sect = s_first; sect <= s_last; ++sect) {
-                if (info->protect[sect])
-                        prot++;
-        }
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect])
+			prot++;
+	}
 
 	if (prot)
-                printf ("- Warning: %d protected sectors will not be erased!\n", prot);
-        else
-                printf ("\n");	
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	else
+		printf ("\n");
 
 	cnt = s_last - s_first + 1;
 

board/ezkit533/psd4256.h

@@ -65,4 +65,3 @@
 #define	PSDA_LED6	0x04		/* LED 6, 1 = LED ON			*/
 #define	PSDA_LED5	0x02		/* LED 5, 1 = LED ON			*/
 #define	PSDA_LED4	0x01		/* LED 4, 1 = LED ON			*/
-

board/ezkit533/u-boot.lds

@@ -146,4 +146,3 @@ SECTIONS
   _end = . ;
   PROVIDE (end = .);
 }
-

board/stamp/config.mk

@@ -23,4 +23,3 @@
 
 TEXT_BASE = 0x07FC0000
 PLATFORM_CPPFLAGS += -I$(TOPDIR)
-

board/stamp/stamp.c

@@ -30,71 +30,71 @@
 #include "stamp.h"
 
 #define STATUS_LED_OFF 0
-#define STATUS_LED_ON  1 	
+#define STATUS_LED_ON  1
 
 #ifdef CONFIG_SHOW_BOOT_PROGRESS
 # define SHOW_BOOT_PROGRESS(arg)	show_boot_progress(arg)
 #else
-# define SHOW_BOOT_PROGRESS(arg)	
+# define SHOW_BOOT_PROGRESS(arg)
 #endif
 
-int checkboard(void)
+int checkboard (void)
 {
-	printf("CPU:   ADSP BF533 Rev.: 0.%d\n", *pCHIPID >> 28);
-	printf("Board: ADI BF533 Stamp board\n");
-	printf("       Support: http://blackfin.uclinux.org/\n");
-	printf("       Richard Klingler <richard@uclinux.net>\n");
+	printf ("CPU:   ADSP BF533 Rev.: 0.%d\n", *pCHIPID >> 28);
+	printf ("Board: ADI BF533 Stamp board\n");
+	printf ("       Support: http://blackfin.uclinux.org/\n");
+	printf ("       Richard Klingler <richard@uclinux.net>\n");
 	return 0;
 }
 
-long int initdram(int board_type)
+long int initdram (int board_type)
 {
 	DECLARE_GLOBAL_DATA_PTR;
 #ifdef DEBUG
-	printf("SDRAM attributes:\n");
-	printf("  tRCD:%d Cycles; tRP:%d Cycles; tRAS:%d Cycles; tWR:%d Cycles; "
-		"CAS Latency:%d cycles\n", (SDRAM_tRCD >> 15), (SDRAM_tRP >> 11),
-	(SDRAM_tRAS >> 6), ( SDRAM_tWR >> 19), (SDRAM_CL >> 2 ));
-	printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE);
-	printf("Bank size = %d MB\n", 128);
+	printf ("SDRAM attributes:\n");
+	printf ("  tRCD:%d Cycles; tRP:%d Cycles; tRAS:%d Cycles; tWR:%d Cycles; "
+		"CAS Latency:%d cycles\n",
+		(SDRAM_tRCD >> 15),
+		(SDRAM_tRP >> 11),
+		(SDRAM_tRAS >> 6),
+		(SDRAM_tWR >> 19),
+		(SDRAM_CL >> 2));
+	printf ("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE);
+	printf ("Bank size = %d MB\n", 128);
 #endif
 	gd->bd->bi_memstart = CFG_SDRAM_BASE;
 	gd->bd->bi_memsize = CFG_MAX_RAM_SIZE;
 	return (gd->bd->bi_memsize);
 }
 
-void swap_to(int device_id)
+void swap_to (int device_id)
 {
 
-	if (device_id == ETHERNET)
-	{
+	if (device_id == ETHERNET) {
 		*pFIO_DIR = PF0;
-		asm("ssync;");
+		asm ("ssync;");
 		*pFIO_FLAG_S = PF0;
-		asm("ssync;");
-	}
-	else if (device_id == FLASH)
-	{
+		asm ("ssync;");
+	} else if (device_id == FLASH) {
 		*pFIO_DIR = (PF4 | PF3 | PF2 | PF1 | PF0);
-		*pFIO_FLAG_S = (PF4 | PF3 | PF2 );
+		*pFIO_FLAG_S = (PF4 | PF3 | PF2);
 		*pFIO_MASKA_D = (PF8 | PF6 | PF5);
 		*pFIO_MASKB_D = (PF7);
-		*pFIO_POLAR = (PF8 | PF6 | PF5 );
+		*pFIO_POLAR = (PF8 | PF6 | PF5);
 		*pFIO_EDGE = (PF8 | PF7 | PF6 | PF5);
 		*pFIO_INEN = (PF8 | PF7 | PF6 | PF5);
-		*pFIO_FLAG_D = (PF4 | PF3 | PF2 );
-		asm("ssync;");
+		*pFIO_FLAG_D = (PF4 | PF3 | PF2);
+		asm ("ssync;");
+	} else {
+		printf ("Unknown bank to switch\n");
 	}
-	else {
-		printf("Unknown bank to switch\n");
-	}	
-	
+
 	return;
 }
 
 #if defined(CONFIG_MISC_INIT_R)
 /* miscellaneous platform dependent initialisations */
-int misc_init_r(void)
+int misc_init_r (void)
 {
 	int i;
 	int cf_stat = 0;
@@ -102,40 +102,39 @@ int misc_init_r(void)
 	/* Check whether CF card is inserted */
 	*pFIO_EDGE = FIO_EDGE_CF_BITS;
 	*pFIO_POLAR = FIO_POLAR_CF_BITS;
-	for (i=0; i < 0x300 ; i++) asm("nop;");
-			
-	if ( (*pFIO_FLAG_S) & CF_STAT_BITS)
-	{
+	for (i = 0; i < 0x300; i++)
+		asm ("nop;");
+
+	if ((*pFIO_FLAG_S) & CF_STAT_BITS) {
 		cf_stat = 0;
-	}
-	else
-	{
+	} else {
 		cf_stat = 1;
 	}
 
-	*pFIO_EDGE  = FIO_EDGE_BITS;
+	*pFIO_EDGE = FIO_EDGE_BITS;
 	*pFIO_POLAR = FIO_POLAR_BITS;
-	
 
-	if (cf_stat)
-	{
-                printf ("Booting from COMPACT flash\n");
+
+	if (cf_stat) {
+		printf ("Booting from COMPACT flash\n");
 
 		/* Set cycle time for CF */
 		*(volatile unsigned long *) ambctl1 = CF_AMBCTL1VAL;
 
-		for (i=0; i < 0x1000 ; i++) asm("nop;");
-		for (i=0; i < 0x1000 ; i++) asm("nop;");
-		for (i=0; i < 0x1000 ; i++) asm("nop;");
+		for (i = 0; i < 0x1000; i++)
+			asm ("nop;");
+		for (i = 0; i < 0x1000; i++)
+			asm ("nop;");
+		for (i = 0; i < 0x1000; i++)
+			asm ("nop;");
 
-		serial_setbrg();
-		ide_init();
+		serial_setbrg ();
+		ide_init ();
 
 		setenv ("bootargs", "");
-		setenv ("bootcmd", "fatload ide 0:1 0x1000000 uImage-stamp;bootm 0x1000000;bootm 0x20100000" );
-	}
-	else
-        {
+		setenv ("bootcmd",
+			"fatload ide 0:1 0x1000000 uImage-stamp;bootm 0x1000000;bootm 0x20100000");
+	} else {
 		printf ("Booting from FLASH\n");
 	}
 
@@ -145,134 +144,132 @@ int misc_init_r(void)
 
 #ifdef CONFIG_STAMP_CF
 
-void cf_outb(unsigned char val, volatile unsigned char* addr)
+void cf_outb (unsigned char val, volatile unsigned char *addr)
 {
-	/* 
+	/*
 	 * Set PF1 PF0 respectively to 0 1 to divert address
-	 * to the expansion memory banks  
+	 * to the expansion memory banks
 	 */
 	*pFIO_FLAG_S = CF_PF0;
 	*pFIO_FLAG_C = CF_PF1;
-	asm("ssync;");
+	asm ("ssync;");
 
 	*(addr) = val;
-	asm("ssync;");
+	asm ("ssync;");
 
-	/* Setback PF1 PF0 to 0 0 to address external 
+	/* Setback PF1 PF0 to 0 0 to address external
 	 * memory banks  */
 	*(volatile unsigned short *) pFIO_FLAG_C = CF_PF1_PF0;
-	asm("ssync;");
+	asm ("ssync;");
 }
 
-unsigned char cf_inb(volatile unsigned char *addr)
+unsigned char cf_inb (volatile unsigned char *addr)
 {
 	volatile unsigned char c;
 
 	*pFIO_FLAG_S = CF_PF0;
 	*pFIO_FLAG_C = CF_PF1;
-	asm("ssync;");
+	asm ("ssync;");
 
 	c = *(addr);
-	asm("ssync;");
+	asm ("ssync;");
 
 	*pFIO_FLAG_C = CF_PF1_PF0;
-	asm("ssync;");
+	asm ("ssync;");
 
 	return c;
 }
 
-void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words)
+void cf_insw (unsigned short *sect_buf, unsigned short *addr, int words)
 {
 	int i;
 
 	*pFIO_FLAG_S = CF_PF0;
 	*pFIO_FLAG_C = CF_PF1;
-	asm("ssync;");
+	asm ("ssync;");
 
-	for (i = 0;i < words; i++)
-	{
+	for (i = 0; i < words; i++) {
 		*(sect_buf + i) = *(addr);
-		asm("ssync;");
+		asm ("ssync;");
 	}
 
 	*pFIO_FLAG_C = CF_PF1_PF0;
-	asm("ssync;");
+	asm ("ssync;");
 }
 
-void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
+void cf_outsw (unsigned short *addr, unsigned short *sect_buf, int words)
 {
 	int i;
 
 	*pFIO_FLAG_S = CF_PF0;
 	*pFIO_FLAG_C = CF_PF1;
-	asm("ssync;");
+	asm ("ssync;");
 
-	for (i = 0;i < words; i++)
-	{
+	for (i = 0; i < words; i++) {
 		*(addr) = *(sect_buf + i);
-		asm("ssync;");
+		asm ("ssync;");
 	}
 
 	*pFIO_FLAG_C = CF_PF1_PF0;
-	asm("ssync;");
+	asm ("ssync;");
 }
 #endif
 
-void stamp_led_set(int LED1, int LED2, int LED3)
+void stamp_led_set (int LED1, int LED2, int LED3)
 {
-	*pFIO_INEN  &= ~( PF2 | PF3 | PF4);
-	*pFIO_DIR   |=  ( PF2 | PF3 | PF4);
-	
-	if(LED1 == STATUS_LED_OFF)
+	*pFIO_INEN &= ~(PF2 | PF3 | PF4);
+	*pFIO_DIR |= (PF2 | PF3 | PF4);
+
+	if (LED1 == STATUS_LED_OFF)
 		*pFIO_FLAG_S = PF2;
 	else
 		*pFIO_FLAG_C = PF2;
-	if(LED2 == STATUS_LED_OFF)
+	if (LED2 == STATUS_LED_OFF)
 		*pFIO_FLAG_S = PF3;
 	else
 		*pFIO_FLAG_C = PF3;
-	if(LED3 == STATUS_LED_OFF)
+	if (LED3 == STATUS_LED_OFF)
 		*pFIO_FLAG_S = PF4;
 	else
 		*pFIO_FLAG_C = PF4;
-	asm("ssync;");
+	asm ("ssync;");
 }
 
-void show_boot_progress(int status)
+void show_boot_progress (int status)
 {
-	switch(status){
-		case 1:	
-			stamp_led_set(STATUS_LED_OFF,STATUS_LED_OFF,STATUS_LED_ON);
-			break;
-		case 2:
-			stamp_led_set(STATUS_LED_OFF,STATUS_LED_ON,STATUS_LED_OFF);
-			break;
-		case 3:
-			stamp_led_set(STATUS_LED_OFF,STATUS_LED_ON,STATUS_LED_ON);
-			break;	
-		case 4:
-			stamp_led_set(STATUS_LED_ON,STATUS_LED_OFF,STATUS_LED_OFF);			
-			break;
-		case 5:
-		case 6:
-			stamp_led_set(STATUS_LED_ON,STATUS_LED_OFF,STATUS_LED_ON);			
-			break;
-		case 7:
-		case 8:
-			stamp_led_set(STATUS_LED_ON,STATUS_LED_ON,STATUS_LED_OFF);			
-			break;
-		case 9:
-		case 10:
-		case 11:
-		case 12:
-		case 13:
-		case 14:
-		case 15:
-			stamp_led_set(STATUS_LED_OFF,STATUS_LED_OFF,STATUS_LED_OFF);			
-			break;
-		default:
-			stamp_led_set(STATUS_LED_ON,STATUS_LED_ON,STATUS_LED_ON);			
-			break;
+	switch (status) {
+	case 1:
+		stamp_led_set (STATUS_LED_OFF, STATUS_LED_OFF, STATUS_LED_ON);
+		break;
+	case 2:
+		stamp_led_set (STATUS_LED_OFF, STATUS_LED_ON, STATUS_LED_OFF);
+		break;
+	case 3:
+		stamp_led_set (STATUS_LED_OFF, STATUS_LED_ON, STATUS_LED_ON);
+		break;
+	case 4:
+		stamp_led_set (STATUS_LED_ON, STATUS_LED_OFF, STATUS_LED_OFF);
+		break;
+	case 5:
+	case 6:
+		stamp_led_set (STATUS_LED_ON, STATUS_LED_OFF, STATUS_LED_ON);
+		break;
+	case 7:
+	case 8:
+		stamp_led_set (STATUS_LED_ON, STATUS_LED_ON, STATUS_LED_OFF);
+		break;
+	case 9:
+	case 10:
+	case 11:
+	case 12:
+	case 13:
+	case 14:
+	case 15:
+		stamp_led_set (STATUS_LED_OFF, STATUS_LED_OFF,
+			       STATUS_LED_OFF);
+		break;
+	default:
+		stamp_led_set (STATUS_LED_ON, STATUS_LED_ON, STATUS_LED_ON);
+		break;
 	}
 }
-

board/stamp/u-boot.lds

@@ -145,4 +145,3 @@ SECTIONS
   _end = . ;
   PROVIDE (end = .);
 }
-

common/soft_i2c.c

@@ -289,7 +289,7 @@ int i2c_probe(uchar addr)
 	int rc;
 
 	/*
-	 * perform 1 byte write transaction with just address byte 
+	 * perform 1 byte write transaction with just address byte
 	 * (fake write)
 	 */
 	send_start();

cpu/bf533/bf533_serial.h

@@ -3,7 +3,7 @@
  *
  * Copyright (c) 2005 blackfin.uclinux.org
  *
- * This file is based on 
+ * This file is based on
  * bf533_serial.h: Definitions for the BlackFin BF533 DSP serial driver.
  * Copyright (C) 2003	Bas Vermeulen <bas@buyways.nl>
  * 			BuyWays B.V. (www.buyways.nl)

cpu/bf533/cache.S

@@ -22,88 +22,88 @@ ENTRY(blackfin_icache_flush_range)
 
 ENTRY(blackfin_dcache_flush_range)
 	R2 = -32;
-        R2 = R0 & R2;
-        P0 = R2;
-        P1 = R1;
-        CSYNC;
+	R2 = R0 & R2;
+	P0 = R2;
+	P1 = R1;
+	CSYNC;
 1:
-        FLUSH[P0++];
-        CC = P0 < P1(iu);
-        IF CC JUMP 1b(bp);
-        FLUSH[P0];
-        SSYNC;
-        RTS;
+	FLUSH[P0++];
+	CC = P0 < P1(iu);
+	IF CC JUMP 1b(bp);
+	FLUSH[P0];
+	SSYNC;
+	RTS;
 
 ENTRY(_icache_invalidate)
 ENTRY(invalidate_entire_icache)
-        [--SP] = ( R7:5);
-                                                                                                                                                             
-        P0.L = (IMEM_CONTROL & 0xFFFF);
-        P0.H = (IMEM_CONTROL >> 16);
-        R7 = [P0];
-                                                                                                                                                             
-        /* Clear the IMC bit , All valid bits in the instruction
-         * cache are set to the invalid state
-         */
-        BITCLR(R7,IMC_P);
-        CLI R6;
-        SSYNC;          /* SSYNC required before invalidating cache. */
-        .align 8;
-        [P0] = R7;
-        SSYNC;
-        STI R6;
-                                                                                                                                                             
-        /* Configures the instruction cache agian */
-        R6 = (IMC | ENICPLB);
-        R7 = R7 | R6;
-                                                                                                                                                             
-        CLI R6;
-        SSYNC;          /* SSYNC required before writing to IMEM_CONTROL. */
-        .align 8;
-        [P0] = R7;
-        SSYNC;
-        STI R6;
-                                                                                                                                                             
-        ( R7:5) = [SP++];
-        RTS;
+	[--SP] = ( R7:5);
+
+	P0.L = (IMEM_CONTROL & 0xFFFF);
+	P0.H = (IMEM_CONTROL >> 16);
+	R7 = [P0];
+
+	/* Clear the IMC bit , All valid bits in the instruction
+	 * cache are set to the invalid state
+	 */
+	BITCLR(R7,IMC_P);
+	CLI R6;
+	SSYNC;		/* SSYNC required before invalidating cache. */
+	.align 8;
+	[P0] = R7;
+	SSYNC;
+	STI R6;
+
+	/* Configures the instruction cache agian */
+	R6 = (IMC | ENICPLB);
+	R7 = R7 | R6;
+
+	CLI R6;
+	SSYNC;		/* SSYNC required before writing to IMEM_CONTROL. */
+	.align 8;
+	[P0] = R7;
+	SSYNC;
+	STI R6;
+
+	( R7:5) = [SP++];
+	RTS;
 
 /* Invalidate the Entire Data cache by
  * clearing DMC[1:0] bits
  */
 ENTRY(invalidate_entire_dcache)
 ENTRY(_dcache_invalidate)
-        [--SP] = ( R7:6);
-                                                                                                                                                             
-        P0.L = (DMEM_CONTROL & 0xFFFF);
-        P0.H = (DMEM_CONTROL >> 16);
-        R7 = [P0];
-                                                                                                                                                             
-        /* Clear the DMC[1:0] bits, All valid bits in the data
-         * cache are set to the invalid state
-         */
-        BITCLR(R7,DMC0_P);
-        BITCLR(R7,DMC1_P);
-        CLI R6;
-        SSYNC;          /* SSYNC required before writing to DMEM_CONTROL. */
-        .align 8;
-        [P0] = R7;
-        SSYNC;
-        STI R6;
-                                                                                                                                                             
-        /* Configures the data cache again */
-                                                                                                                                                             
-        R6 = (ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
-        R7 = R7 | R6;
-                                                                                                                                                             
-        CLI R6;
-        SSYNC;          /* SSYNC required before writing to DMEM_CONTROL. */
-        .align 8;
-        [P0] = R7;
-        SSYNC;
-        STI R6;
-                                                                                                                                                             
-        ( R7:6) = [SP++];
-        RTS;
+	[--SP] = ( R7:6);
+
+	P0.L = (DMEM_CONTROL & 0xFFFF);
+	P0.H = (DMEM_CONTROL >> 16);
+	R7 = [P0];
+
+	/* Clear the DMC[1:0] bits, All valid bits in the data
+	 * cache are set to the invalid state
+	 */
+	BITCLR(R7,DMC0_P);
+	BITCLR(R7,DMC1_P);
+	CLI R6;
+	SSYNC;		/* SSYNC required before writing to DMEM_CONTROL. */
+	.align 8;
+	[P0] = R7;
+	SSYNC;
+	STI R6;
+
+	/* Configures the data cache again */
+
+	R6 = (ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
+	R7 = R7 | R6;
+
+	CLI R6;
+	SSYNC;		/* SSYNC required before writing to DMEM_CONTROL. */
+	.align 8;
+	[P0] = R7;
+	SSYNC;
+	STI R6;
+
+	( R7:6) = [SP++];
+	RTS;
 
 ENTRY(blackfin_dcache_invalidate_range)
 	R2 = -32;

cpu/bf533/cplbhdlr.S

@@ -1,9 +1,9 @@
-/* Copyright (C) 2003 Analog Devices, Inc. All Rights Reserved. 
+/* Copyright (C) 2003 Analog Devices, Inc. All Rights Reserved.
  *
  * This file is subject to the terms and conditions of the GNU General Public
- * License. 
+ * License.
  *
- * Blackfin BF533/2.6 support : LG Soft India	
+ * Blackfin BF533/2.6 support : LG Soft India
  */
 
 
@@ -16,7 +16,7 @@
 
 
 .text
- 
+
 .globl _cplb_hdr;
 .type _cplb_hdr, STT_FUNC;
 .extern _cplb_mgr;
@@ -76,19 +76,19 @@ is_icplb_miss:
 
 #if ( defined (CONFIG_BLKFIN_CACHE) || defined (CONFIG_BLKFIN_DCACHE))
 #if ( defined (CONFIG_BLKFIN_CACHE) && !defined (CONFIG_BLKFIN_DCACHE))
-	R1 = CPLB_ENABLE_ICACHE; 
+	R1 = CPLB_ENABLE_ICACHE;
 #endif
 #if ( !defined (CONFIG_BLKFIN_CACHE) && defined (CONFIG_BLKFIN_DCACHE))
-	R1 = CPLB_ENABLE_DCACHE; 
+	R1 = CPLB_ENABLE_DCACHE;
 #endif
 #if ( defined (CONFIG_BLKFIN_CACHE) && defined (CONFIG_BLKFIN_DCACHE))
-	R1 = CPLB_ENABLE_DCACHE | CPLB_ENABLE_ICACHE; 
+	R1 = CPLB_ENABLE_DCACHE | CPLB_ENABLE_ICACHE;
 #endif
 #else
 	R1 = 0;
 #endif
 
-	[--SP] = RETS;			
+	[--SP] = RETS;
 	CALL _cplb_mgr;
 	RETS = [SP++];
 	CC = R0 == 0;
@@ -109,27 +109,27 @@ is_icplb_miss:
 	RTS;
 
 unknown:
-	[--SP] = RETS;			
+	[--SP] = RETS;
 	CALL __unknown_exception_occurred;
 	RETS = [SP++];
 	JUMP unknown;
 not_replaced:
 	CC = R0 == CPLB_NO_UNLOCKED;
 	IF !CC JUMP next_check;
-	[--SP] = RETS;			
+	[--SP] = RETS;
 	CALL __cplb_miss_all_locked;
 	RETS = [SP++];
 next_check:
 	CC = R0 == CPLB_NO_ADDR_MATCH;
 	IF !CC JUMP next_check2;
-	[--SP] = RETS;			
+	[--SP] = RETS;
 	CALL __cplb_miss_without_replacement;
 	RETS = [SP++];
 	JUMP not_replaced;
 next_check2:
 	CC = R0 == CPLB_PROT_VIOL;
 	IF !CC JUMP strange_return_from_cplb_mgr;
-	[--SP] = RETS;			
+	[--SP] = RETS;
 	CALL __cplb_protection_violation;
 	RETS = [SP++];
 	JUMP not_replaced;
@@ -139,8 +139,8 @@ strange_return_from_cplb_mgr:
 	JUMP strange_return_from_cplb_mgr;
 
 /************************************
- * Diagnostic exception handlers 
- */	
+ * Diagnostic exception handlers
+ */
 
 __cplb_miss_all_locked:
 	sp += -12;
@@ -174,11 +174,11 @@ __unknown_exception_occurred:
 	 * other kinds of exceptions, you must replace the
 	 * default handler with your own, that handles all the
 	 * exceptions you will use.
-	 * 
+	 *
 	 * Since there's nothing we can do, we just loop here
 	 * at what we hope is a suitably informative label.
 	 */
-	
+
 	IDLE;
 do_not_know_what_to_do:
 	CSYNC;
@@ -191,4 +191,3 @@ do_not_know_what_to_do:
 
 panic_bfin:
 	RTS;
-

cpu/bf533/cplbmgr.S

@@ -3,7 +3,7 @@
  *
  * Blackfin BF533/2.6 support : LG Soft India
  * Modification: Dec 07 2004
- *	1. Correction in icheck_lock.  Valid lock entries were 
+ *	1. Correction in icheck_lock.  Valid lock entries were
  *	   geting victimized, for instruction cplb replacement.
  *	2. Setup loop's are modified as now toolchain support's P Indexed
  *	   addressing
@@ -18,15 +18,15 @@
  *
  * Returns:
  * CPLB_RELOADED	=> Successfully updated CPLB table.
- * CPLB_NO_UNLOCKED	=> All CPLBs are locked, so cannot be evicted.This indicates 
- *				that the CPLBs in the configuration tablei are badly 
+ * CPLB_NO_UNLOCKED	=> All CPLBs are locked, so cannot be evicted.This indicates
+ *				that the CPLBs in the configuration tablei are badly
  *				configured, as this should never occur.
- * CPLB_NO_ADDR_MATCH	=> The address being accessed, that triggered the exception, 
- *				is not covered by any of the CPLBs in the configuration 
+ * CPLB_NO_ADDR_MATCH	=> The address being accessed, that triggered the exception,
+ *				is not covered by any of the CPLBs in the configuration
  *				table. The application isi presumably misbehaving.
- * CPLB_PROT_VIOL	=> The address being accessed, that triggered thei exception, 
- *				was not a first-write to a clean Write Back Data page, 
- *				and so presumably is a genuine violation of the page's 
+ * CPLB_PROT_VIOL	=> The address being accessed, that triggered thei exception,
+ *				was not a first-write to a clean Write Back Data page,
+ *				and so presumably is a genuine violation of the page's
  *				protection attributes. The application is misbehaving.
  */
 #define ASSEMBLY
@@ -35,9 +35,9 @@
 #include <asm-blackfin/blackfin.h>
 #include <asm-blackfin/cplbtab.h>
 #include <asm-blackfin/cplb.h>
- 	
+
 .text
- 
+
 .align 2;
 ENTRY(_cplb_mgr)
 
@@ -51,8 +51,8 @@ ENTRY(_cplb_mgr)
 
 	/* ICPLB Miss Exception. We need to choose one of the
 	* currently-installed CPLBs, and replace it with one
-	* from the configuration table.	
- 	*/
+	* from the configuration table.
+	*/
 
 	P4.L = (ICPLB_FAULT_ADDR & 0xFFFF);
 	P4.H = (ICPLB_FAULT_ADDR >> 16);
@@ -72,7 +72,7 @@ ENTRY(_cplb_mgr)
 isearch:
 
 	R1 = [P0-0x100];	/* Address for this CPLB */
-	
+
 	R0 = [P0++];		/* Info for this CPLB*/
 	CC = BITTST(R0,0);	/* Is the CPLB valid?*/
 	IF !CC JUMP nomatch;	/* Skip it, if not.*/
@@ -94,7 +94,7 @@ nomatch:
 
 isearch_done:
 	I0 = R4;		/* Fault address we'll search for*/
-	
+
 	/* set up pointers */
 	P0.L = (ICPLB_DATA0 & 0xFFFF);
 	P0.H = (ICPLB_DATA0 >> 16);
@@ -138,7 +138,7 @@ ifound_victim:
 	P3.H = ipdt_swapcount_table;
 	P3 += -4;
 icount:
-	R2 = [P2];	/* address from config table */			
+	R2 = [P2];	/* address from config table */
 	P2 += 8;
 	P3 += 8;
 	CC = R2==-1;
@@ -153,13 +153,13 @@ icount_done:
 #endif
 	LC0=R3;
 	LSETUP(is_move,ie_move) LC0;
-is_move: 
+is_move:
 	R0 = [P0];
 	[P0 - 4] = R0;
 	R0 = [P0 - 0x100];
-	[P0-0x104] = R0; 
+	[P0-0x104] = R0;
 ie_move:P0+=4;
-	
+
 	/* We've made space in the ICPLB table, so that ICPLB15
 	 * is now free to be overwritten. Next, we have to determine
 	 * which CPLB we need to install, from the configuration
@@ -167,8 +167,8 @@ ie_move:P0+=4;
 	 * addresses and page-lengths from the config table, and
 	 * determining whether the fault address falls within that
 	 * range.
- 	 */
-	
+	 */
+
 	P2.L = ipdt_table;
 	P2.H = ipdt_table;
 #ifdef	CONFIG_CPLB_INFO
@@ -190,7 +190,7 @@ ie_move:P0+=4;
 	 */
 
 	R1 = ((16<<8)|2);
-inext:	R4 = [P2++];	/* address from config table */			
+inext:	R4 = [P2++];	/* address from config table */
 	R2 = [P2++];	/* data from config table */
 #ifdef	CONFIG_CPLB_INFO
 	P3 += 8;
@@ -201,7 +201,7 @@ inext:	R4 = [P2++];	/* address from config table */
 
 	/* See if failed address > start address */
 	CC = R4 <= R0(IU);
- 	IF !CC JUMP inext;
+	IF !CC JUMP inext;
 
 	/* extract page size (17:16)*/
 	R3 = EXTRACT(R2, R1.L) (Z);
@@ -250,17 +250,17 @@ inext:	R4 = [P2++];	/* address from config table */
 
 /* FAILED CASES*/
 no_page_in_table:
-        ( R7:0,P5:0 ) = [SP++];
-        R0 = CPLB_NO_ADDR_MATCH;
-        RTS;
+	( R7:0,P5:0 ) = [SP++];
+	R0 = CPLB_NO_ADDR_MATCH;
+	RTS;
 all_locked:
-        ( R7:0,P5:0 ) = [SP++];
-        R0 = CPLB_NO_UNLOCKED;
-        RTS;
+	( R7:0,P5:0 ) = [SP++];
+	R0 = CPLB_NO_UNLOCKED;
+	RTS;
 prot_violation:
-        ( R7:0,P5:0 ) = [SP++];
-        R0 = CPLB_PROT_VIOL;
-        RTS;
+	( R7:0,P5:0 ) = [SP++];
+	R0 = CPLB_PROT_VIOL;
+	RTS;
 
 dcplb_write:
 
@@ -275,7 +275,7 @@ dcplb_write:
 	P4.H = (DCPLB_STATUS >> 16);
 	P3.L = (DCPLB_DATA0 & 0xFFFF);
 	P3.H = (DCPLB_DATA0 >> 16);
-	R5 = [P4];	
+	R5 = [P4];
 
 	/* A protection violation can be caused by more than just writes
 	 * to a clean WB page, so we have to ensure that:
@@ -315,7 +315,7 @@ dcplb_write:
 	R2 <<= R5;		/* if was super, check write in super mode*/
 	R2 = R3 & R2;
 	CC = R2 == 0;
-	IF CC JUMP prot_violation;	
+	IF CC JUMP prot_violation;
 
 	/* It's a genuine write-to-clean-page.*/
 
@@ -333,7 +333,7 @@ dcplb_miss_compare:
 	 * config table, that covers the faulting address.
 	 */
 
-	P1.L = (DCPLB_DATA15 & 0xFFFF);	
+	P1.L = (DCPLB_DATA15 & 0xFFFF);
 	P1.H = (DCPLB_DATA15 >> 16);
 
 	P4.L = (DCPLB_FAULT_ADDR & 0xFFFF);
@@ -379,7 +379,7 @@ sdsearch2:
 	CC = R2 == 0;		/* If none are set, it'll do.*/
 	IF !CC JUMP skip_stack_check;
 
-	R2 = [P0 - 0x104]; 	/* R2 - PageStart */
+	R2 = [P0 - 0x104];	/* R2 - PageStart */
 	P3.L = page_size_table; /* retrive end address */
 	P3.H = page_size_table; /* retrive end address */
 	R3 = 0x2;		/* 0th - position, 2 bits -length */
@@ -392,13 +392,13 @@ sdsearch2:
 
 	R7 = R7 << 0xA;		/* in bytes * 1024*/
 	R7 = R2 + R7;		/* R7 - PageEnd */
-	R4 = SP; 		/* Test SP is in range */
+	R4 = SP;		/* Test SP is in range */
 
 	CC = R7 < R4;		/* if PageEnd < SP */
 	IF CC JUMP dfound_victim;
 	R3 = 0x284;		/* stack length from start of trap till the point */
 				/* 20 stack locations for future modifications */
-	R4 = R4 + R3;	
+	R4 = R4 + R3;
 	CC = R4 < R2;		/* if SP + stacklen < PageStart */
 	IF CC JUMP dfound_victim;
 skip_stack_check:
@@ -409,7 +409,7 @@ edsearch1: NOP;
 	/* If we got here, we didn't find a DCPLB we considered
 	 * replacable, which means all of them were locked.
 	 */
-	
+
 	JUMP all_locked;
 dfound_victim:
 
@@ -450,14 +450,14 @@ dicount_done:
 	CC = BITTST(R1, 7);	/* Is it dirty?*/
 	IF !CC JUMP Ddoverwrite (BP);	/* Nope.*/
 	CC = BITTST(R1, 14);	/* Is it Write-Through?*/
-	IF CC JUMP Ddoverwrite;	/* Yep*/
+	IF CC JUMP Ddoverwrite; /* Yep*/
 
 	/* This is a dirty page, so we need to flush all writes
 	 * that are pending on the page.
 	 */
 
 	/* Retrieve the page start address*/
-        R0 = [P0 - 0x104];
+	R0 = [P0 - 0x104];
 	[--sp] = rets;
 	CALL dcplb_flush;	/* R0==CPLB addr, R1==CPLB data*/
 	rets = [sp++];
@@ -467,7 +467,7 @@ Ddoverwrite:
 	 * overwrite it by moving all the following CPLBs
 	 * one space closer to the start.
 	 */
-	
+
 	R1.L = ((DCPLB_DATA15+4) & 0xFFFF);		/*DCPLB_DATA15+4*/
 	R1.H = ((DCPLB_DATA15+4) >> 16);
 	R0 = P0;
@@ -485,7 +485,7 @@ Ddoverwrite:
 ds_move:
 	 R0 = [P0++];	/* move data */
 	[P0 - 8] = R0;
-	R0 = [P0-0x104]	/* move address */
+	R0 = [P0-0x104] /* move address */
 de_move: [P0-0x108] = R0;
 
 	/* We've now made space in DCPLB15 for the new CPLB to be
@@ -510,7 +510,7 @@ de_moved:NOP;
 	/* An extraction pattern, to retrieve bits 17:16.*/
 
 	R1 = (16<<8)|2;
-dnext:	R4 = [P2++];	/* address */			
+dnext:	R4 = [P2++];	/* address */
 	R2 = [P2++];	/* data */
 #ifdef	CONFIG_CPLB_INFO
 	P3 += 8;
@@ -521,7 +521,7 @@ dnext:	R4 = [P2++];	/* address */
 
 	/* See if failed address > start address */
 	CC = R4 <= R0(IU);
- 	IF !CC JUMP dnext;
+	IF !CC JUMP dnext;
 
 	/* extract page size (17:16)*/
 	R3 = EXTRACT(R2, R1.L) (Z);

cpu/bf533/cpu.c

@@ -41,7 +41,7 @@
 #define L1_IMEMORY            	(PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
 #define SDRAM_INON_CHBL		(PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
 
-#define ANOMALY_05000158		0x200	
+#define ANOMALY_05000158		0x200
 #define SDRAM_DGENERIC          (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
 #define SDRAM_DNON_CHBL         (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
 #define SDRAM_DKERNEL           (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
@@ -68,7 +68,7 @@ static unsigned int icplb_table[16][2]={
 };
 
 static unsigned int dcplb_table[16][2]={
-			{0xFFA00000,L1_DMEMORY},	
+			{0xFFA00000,L1_DMEMORY},
 			{0x00000000,SDRAM_DKERNEL},	/*SDRAM_Page1*/
 			{0x00400000,SDRAM_DKERNEL},	/*SDRAM_Page1*/
 			{0x07C00000,SDRAM_DKERNEL},	/*SDRAM_Page15*/
@@ -83,13 +83,9 @@ static unsigned int dcplb_table[16][2]={
 			{0x02800000,SDRAM_DGENERIC},	/*SDRAM_Page10*/
 			{0x02C00000,SDRAM_DGENERIC},	/*SDRAM_Page11*/
 			{0x03000000,SDRAM_DGENERIC},	/*SDRAM_Page12*/
-			{0x20000000,SDRAM_EBIU},	/*For Network */	
+			{0x20000000,SDRAM_EBIU},	/*For Network */
 };
 
-
-			
-			
-
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	__asm__ __volatile__
@@ -121,7 +117,7 @@ void icache_enable(void)
 
 	I0 = (unsigned int *)ICPLB_ADDR0;
 	I1 = (unsigned int *)ICPLB_DATA0;
-	
+
 	for(i=0;i<16;i++){
 		*I0++ = icplb_table[i][0];
 		*I1++ = icplb_table[i][1];
@@ -166,13 +162,12 @@ void dcache_enable(void)
 		*I1++ = dcplb_table[i][1];
 		}
 	cli();
-	temp = *(unsigned int *)DMEM_CONTROL; 
+	temp = *(unsigned int *)DMEM_CONTROL;
 	SSYNC();
 	*(unsigned int *)DMEM_CONTROL = ACACHE_BCACHE |ENDCPLB |PORT_PREF0|temp;
 	SSYNC();
 	sti();
 }
-		
 
 void dcache_disable(void)
 {

cpu/bf533/flush.S

@@ -60,7 +60,7 @@ ENTRY(icplb_flush)
 	[--SP] = LC1;
 	[--SP] = LT1;
 	[--SP] = LB1;
-	
+
 	/* If it's a 1K or 4K page, then it's quickest to
 	 * just systematically flush all the addresses in
 	 * the page, regardless of whether they're in the
@@ -90,7 +90,7 @@ ENTRY(icplb_flush)
 	R4 = EXTRACT(R0, R3.L) (Z);	/* Extract bits*/
 	R3.H = R4.L << 0 ;		/* Save in extraction pattern for later deposit.*/
 
-	
+
 	/* So:
 	 * R0 = Page start
 	 * R1 = Page length (actually, offset into size/prefix tables)
@@ -101,7 +101,7 @@ ENTRY(icplb_flush)
 	 * sub-bank, looking for dirty, valid tags that match our
 	 * address prefix.
 	 */
-	
+
 	P5.L = (ITEST_COMMAND & 0xFFFF);
 	P5.H = (ITEST_COMMAND >> 16);
 	P4.L = (ITEST_DATA0 & 0xFFFF);
@@ -119,7 +119,7 @@ ENTRY(icplb_flush)
 	 * fetching tags, so we only have to set Set, Bank,
 	 * Sub-bank and Way.
 	 */
-	
+
 	P2 = 4;
 	LSETUP (ifs1, ife1) LC1 = P2;
 ifs1:	P0 = 32;		/* iterate over all sets*/
@@ -142,7 +142,7 @@ ifs0:	R6 = R5 << 5;		/* Combine set*/
 	IF !CC JUMP ifskip;	/* Skip it if it doesn't match.*/
 
 	/* Tag address matches against page, so this is an entry
-	 * we must flush. 
+	 * we must flush.
 	 */
 
 	R7 >>= 10;		/* Mask off the non-address bits*/
@@ -181,11 +181,11 @@ iflush_whole_page:
 	IFLUSH [P0++];		/* because CSYNC can't end loops.*/
 	LSETUP (isall, ieall) LC0 = P1;
 isall:IFLUSH [P0++];
-ieall: NOP;	
+ieall: NOP;
 	SSYNC;
 	JUMP ifinished;
 
-/* This is an external function being called by the user 
+/* This is an external function being called by the user
  * application through __flush_cache_all. Currently this function
  * serves the purpose of flushing all the pending writes in
  * in the data cache.
@@ -222,7 +222,7 @@ skip:	R6 += -1;
 
 /* This is an internal function to flush all pending
  * writes in the cache associated with a particular DCPLB.
- * 
+ *
  * R0 -  page's start address
  * R1 -  CPLB's data field.
  */
@@ -236,7 +236,7 @@ ENTRY(dcplb_flush)
 	[--SP] = LC1;
 	[--SP] = LT1;
 	[--SP] = LB1;
-	
+
 	/* If it's a 1K or 4K page, then it's quickest to
 	 * just systematically flush all the addresses in
 	 * the page, regardless of whether they're in the
@@ -250,9 +250,9 @@ ENTRY(dcplb_flush)
 
 	/* We're only interested in the page's size, so extract
 	 * this from the CPLB (bits 17:16), and scale to give an
-	 * offset into the page_size and page_prefix tables.	
+	 * offset into the page_size and page_prefix tables.
 	 */
-		
+
 	R1 <<= 14;
 	R1 >>= 30;
 	R1 <<= 2;
@@ -260,9 +260,9 @@ ENTRY(dcplb_flush)
 	/* The page could be mapped into Bank A or Bank B, depending
 	 * on (a) whether both banks are configured as cache, and
 	 * (b) on whether address bit A[x] is set. x is determined
-	 * by DCBS in DMEM_CONTROL		
+	 * by DCBS in DMEM_CONTROL
 	 */
-	
+
 	R2 = 0;			/* Default to Bank A (Bank B would be 1)*/
 
 	P0.L = (DMEM_CONTROL & 0xFFFF);
@@ -303,7 +303,7 @@ bank_chosen:
 	 * sub-bank, looking for dirty, valid tags that match our
 	 * address prefix.
 	 */
-	
+
 	P5.L = (DTEST_COMMAND & 0xFFFF);
 	P5.H = (DTEST_COMMAND >> 16);
 	P4.L = (DTEST_DATA0 & 0xFFFF);
@@ -322,7 +322,7 @@ bank_chosen:
 	 * fetching tags, so we only have to set Set, Bank,
 	 * Sub-bank and Way.
 	 */
-	
+
 	P2 = 2;
 	LSETUP (fs1, fe1) LC1 = P2;
 fs1:	P0 = 64;		/* iterate over all sets*/

cpu/bf533/interrupt.S

@@ -240,7 +240,7 @@ evt_rst:
 	sp += 12;
 
 _evt_rst_exit:
-	rtn; 
+	rtn;
 
 irq_panic:
 	r0 = IRQ_EVX;
@@ -279,7 +279,7 @@ evt_evt7:
 
 evt_evt7_exit:
 	RESTORE_CONTEXT
-	rti; 
+	rti;
 
 .global evt_evt8
 evt_evt8:

cpu/bf533/serial.c

@@ -13,12 +13,12 @@
  * Copyright(c) 2003	Metrowerks	<mwaddel@metrowerks.com>
  * Copyright(c)	2001	Tony Z. Kou	<tonyko@arcturusnetworks.com>
  * Copyright(c)	2001-2002 Arcturus Networks Inc. <www.arcturusnetworks.com>
- * 
+ *
  * Based on code from 68328 version serial driver imlpementation which was:
  * Copyright (C) 1995       David S. Miller    <davem@caip.rutgers.edu>
  * Copyright (C) 1998       Kenneth Albanowski <kjahds@kjahds.com>
  * Copyright (C) 1998, 1999 D. Jeff Dionne     <jeff@uclinux.org>
- * Copyright (C) 1999       Vladimir Gurevich  <vgurevic@cisco.com> 
+ * Copyright (C) 1999       Vladimir Gurevich  <vgurevic@cisco.com>
  *
  * (C) Copyright 2000-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -178,9 +178,9 @@ static void local_put_char(char ch)
 
 	save_and_cli(flags);
 
-        /* Poll for TX Interruput */
-        while (!((isr_val = *pSIC_ISR) & IRQ_UART_TX_BIT));
-        asm("csync;");
+	/* Poll for TX Interruput */
+	while (!((isr_val = *pSIC_ISR) & IRQ_UART_TX_BIT));
+	asm("csync;");
 
 	*pUART_THR = ch;			/* putc() */
 

cpu/bf533/start.S

@@ -32,7 +32,7 @@
 
 /*
  * Note: A change in this file subsequently requires a change in
- *       board/$(board_name)/config.mk for a valid u-boot.bin 
+ *       board/$(board_name)/config.mk for a valid u-boot.bin
  */
 
 #define ASSEMBLY
@@ -82,7 +82,7 @@ _stext:
 	SSYNC;
 
 	/* As per HW reference manual DAG registers,
-	 * DATA and Address resgister shall be zero'd 
+	 * DATA and Address resgister shall be zero'd
 	 * in initialization, after a reset state
 	 */
 	r1 = 0;	/* Data registers zero'd */
@@ -99,7 +99,7 @@ _stext:
 	p3 = 0;
 	p4 = 0;
 	p5 = 0;
-	
+
 	i0 = 0; /* DAG Registers zero'd */
 	i1 = 0;
 	i2 = 0;
@@ -242,9 +242,9 @@ loop1:
 	r1 = [p1];
 	[p2] = r1;
 	p3=0x4;
-	p1=p1+p3;	
+	p1=p1+p3;
 	p2=p2+p3;
-	r2=0x4;	
+	r2=0x4;
 	r0=r0-r2;
 	cc=r0==0x0;
 	if !cc jump loop1;

examples/stubs.c

@@ -131,7 +131,7 @@ gd_t *global_data;
  * register
  */
 #define EXPORT_FUNC(x)			\
-        asm volatile (			\
+	asm volatile (			\
 "       .globl " #x "\n"		\
 #x ":\n"				\
 "	P0 = [P5 + %0]\n"		\

include/asm-blackfin/cplbtab.h

@@ -3,9 +3,9 @@
  *
  * Blackfin BF533/2.6 support : LG Soft India
  * Updated : Ashutosh Singh / Jahid Khan : Rrap Software Pvt Ltd
- * Updated : 1. SDRAM_KERNEL, SDRAM_DKENEL are added as initial cplb's 
+ * Updated : 1. SDRAM_KERNEL, SDRAM_DKENEL are added as initial cplb's
  *	        shouldn't be victimized. cplbmgr.S search logic is corrected
- *	        to findout the appropriate victim.	
+ *	        to findout the appropriate victim.
  *	     2. SDRAM_IGENERIC in dpdt_table is replaced with SDRAM_DGENERIC
  *	     : LG Soft India
  */
@@ -15,12 +15,12 @@
 #define __ARCH_BFINNOMMU_CPLBTAB_H
 
 /*************************************************************************
- *  			ICPLB TABLE					  	
+ *  			ICPLB TABLE
  *************************************************************************/
 
 .data
 
-/* This table is configurable */ 	
+/* This table is configurable */
 
 .align 4;
 
@@ -33,7 +33,7 @@
 
 /*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
 
-#define ANOMALY_05000158		0x200	
+#define ANOMALY_05000158		0x200
 #ifdef CONFIG_BLKFIN_WB 	/*Write Back Policy */
 	#define SDRAM_DGENERIC  	(PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
 	#define SDRAM_DNON_CHBL         (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
@@ -45,14 +45,14 @@
 	#define SDRAM_DGENERIC 		(PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
 	#define SDRAM_DNON_CHBL         (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
 	#define SDRAM_DKERNEL 		(PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
-	#define L1_DMEMORY		(PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)	
+	#define L1_DMEMORY		(PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
 	#define SDRAM_EBIU		(PAGE_SIZE_1MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
-#endif 
+#endif
 
 .global icplb_table
 icplb_table:
 .byte4 0xFFA00000;
-.byte4 (L1_IMEMORY);	
+.byte4 (L1_IMEMORY);
 .byte4 0x00000000;
 .byte4 (SDRAM_IKERNEL);			/*SDRAM_Page1*/
 .byte4 0x00400000;
@@ -174,20 +174,20 @@ ipdt_table:
 .byte4 0xffffffff;                    /* end of section - termination*/
 
 /*********************************************************************
- *			DCPLB TABLE		
+ *			DCPLB TABLE
  ********************************************************************/
 
 .global dcplb_table
 dcplb_table:
 .byte4	0x00000000;
 .byte4	(SDRAM_DKERNEL);	/*SDRAM_Page1*/
-.byte4	0x00400000; 
+.byte4	0x00400000;
 .byte4	(SDRAM_DKERNEL);	/*SDRAM_Page1*/
 .byte4	0x07C00000;
 .byte4	(SDRAM_DKERNEL);	/*SDRAM_Page15*/
-.byte4	0x00800000; 
+.byte4	0x00800000;
 .byte4 	(SDRAM_DGENERIC);	/*SDRAM_Page2*/
-.byte4 	0x00C00000; 
+.byte4 	0x00C00000;
 .byte4	(SDRAM_DGENERIC);	/*SDRAM_Page3*/
 .byte4	0x01000000;
 .byte4	(SDRAM_DGENERIC);	/*SDRAM_Page4*/
@@ -197,7 +197,7 @@ dcplb_table:
 .byte4	(SDRAM_DGENERIC);	/*SDRAM_Page6*/
 .byte4	0x01C00000;
 .byte4	(SDRAM_DGENERIC);	/*SDRAM_Page7*/
-#ifndef CONFIG_EZKIT	
+#ifndef CONFIG_EZKIT
 .byte4	0x02000000;
 .byte4	(SDRAM_DGENERIC);	/*SDRAM_Page8*/
 .byte4	0x02400000;
@@ -217,7 +217,7 @@ dcplb_table:
 
 /**********************************************************************
  *		PAGE DESCRIPTOR TABLE
- * 
+ *
  **********************************************************************/
 
 /* Till here we are discussing about the static memory management model.
@@ -225,15 +225,15 @@ dcplb_table:
  * descriptors to cover the entire addressable memory than will fit into
  * the available on-chip 16 CPLB MMRs. When this happens, the below table
  * will be used which will hold all the potentially required CPLB descriptors
- * 
+ *
  * This is how Page descriptor Table is implemented in uClinux/Blackfin.
- */   
+ */
 .global dpdt_table
 dpdt_table:
 #ifdef CONFIG_CPLB_INFO
 .byte4        0x00000000;
 .byte4        (SDRAM_DKERNEL);        /*SDRAM_Page0*/
-.byte4        0x00400000; 
+.byte4        0x00400000;
 .byte4        (SDRAM_DKERNEL);        /*SDRAM_Page1*/
 #endif
 .byte4        0x00800000;
@@ -271,12 +271,12 @@ dpdt_table:
 .byte4	(SDRAM_EBIU);	/* Async Memory Bank 2 (Secnd)*/
 .byte4	0x20100000;
 .byte4	(SDRAM_EBIU);	/* Async Memory Bank 1 (Prim B)*/
-.byte4	0x20000000;	
+.byte4	0x20000000;
 .byte4	(SDRAM_EBIU);	/* Async Memory Bank 0 (Prim A)*/
 .byte4	0x20300000;		/*Fix for Network*/
 .byte4  (SDRAM_EBIU);	/*Async Memory bank 3*/
 
-#ifdef CONFIG_STAMP	
+#ifdef CONFIG_STAMP
 .byte4	0x04000000;
 .byte4  (SDRAM_DGENERIC);
 .byte4	0x04400000;

include/asm-blackfin/cpu/bf533_irq.h

@@ -81,7 +81,7 @@
 
 /* The ABSTRACT IRQ definitions */
 
-/* The first seven of the following are fixed, 
+/* The first seven of the following are fixed,
  * the rest you change if you need to
  */
 

include/asm-blackfin/cpu/defBF532.h

@@ -30,7 +30,7 @@
 /* include all Core registers and bit definitions */
 #include <asm/cpu/def_LPBlackfin.h>
 
-/* Helper macros 
+/* Helper macros
  * usage:
  *  P0.H = HI(UART_THR);
  *  P0.L = LO(UART_THR);
@@ -789,7 +789,7 @@
 #define ERR_TYP_P0		0x0E
 #define ERR_TYP_P1		0x0F
 
-/* 
+/*
  * PROGRAMMABLE FLAG MASKS
  */
 

include/asm-blackfin/cpu/def_LPBlackfin.h

@@ -21,7 +21,7 @@
 #ifndef _DEF_LPBLACKFIN_H
 #define _DEF_LPBLACKFIN_H
 
-/* 
+/*
  * #if !defined(__ADSPLPBLACKFIN__)
  * #warning def_LPBlackfin.h should only be included for 532 compatible chips.
  * #endif
@@ -344,9 +344,9 @@
 /* ** Masks */
 #define ENDM			0x00000001	/* (doesn't really exist) Enable Data Memory L1 */
 #define ENDCPLB			0x00000002	/* Enable DCPLB */
-#define ASRAM_BSRAM		0x00000000	
+#define ASRAM_BSRAM		0x00000000
 #define ACACHE_BSRAM		0x00000008
-#define ACACHE_BCACHE		0x0000000C  
+#define ACACHE_BCACHE		0x0000000C
 #define DCBS			0x00000010	/*  L1 Data Cache Bank Select */
 #define PORT_PREF0		0x00001000	/* DAG0 Port Preference */
 #define PORT_PREF1		0x00002000	/* DAG1 Port Preference */

include/asm-blackfin/page_offset.h

@@ -22,7 +22,7 @@
  * MA 02111-1307 USA
  */
 
-/* 
+/*
  * Changes made by Akbar Hussain April 10, 2001
  */
 

include/asm-blackfin/uaccess.h

@@ -3,7 +3,7 @@
  *
  * Copyright (c) 2005 blackfin.uclinux.org
  *
- * This file is based on 
+ * This file is based on
  * Based on: include/asm-m68knommu/uaccess.h
  * Changes made by Lineo Inc.    May 2001
  *

include/configs/ezkit533.h

@@ -9,111 +9,111 @@
 #define CONFIG_DRIVER_SMC91111	1
 #define CONFIG_SMC91111_BASE	0x20310300
 #if 0
-#define	CONFIG_MII
+#define CONFIG_MII
 #define CFG_DISCOVER_PHY
 #endif
 
 #define CONFIG_RTC_BF533	1
 #define CONFIG_BOOT_RETRY_TIME	-1	/* Enable this if bootretry required, currently its disabled */
 
-/* CONFIG_CLKIN_HZ is any value in Hz                            */
-#define CONFIG_CLKIN_HZ          27000000
-/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN      */
-/*                                                  1=CLKIN/2    */
-#define CONFIG_CLKIN_HALF               0
-/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass  */
-/*                                               1=bypass PLL    */
-#define CONFIG_PLL_BYPASS               0
-/* CONFIG_VCO_MULT controls what the multiplier of the PLL is.   */
-/* Values can range from 1-64                                    */
+/* CONFIG_CLKIN_HZ is any value in Hz				 */
+#define CONFIG_CLKIN_HZ		 27000000
+/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN	 */
+/*						    1=CLKIN/2	 */
+#define CONFIG_CLKIN_HALF		0
+/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass	 */
+/*						 1=bypass PLL	 */
+#define CONFIG_PLL_BYPASS		0
+/* CONFIG_VCO_MULT controls what the multiplier of the PLL is.	 */
+/* Values can range from 1-64					 */
 #define CONFIG_VCO_MULT			22
-/* CONFIG_CCLK_DIV controls what the core clock divider is       */
-/* Values can be 1, 2, 4, or 8 ONLY                              */
+/* CONFIG_CCLK_DIV controls what the core clock divider is	 */
+/* Values can be 1, 2, 4, or 8 ONLY				 */
 #define CONFIG_CCLK_DIV			1
 /* CONFIG_SCLK_DIV controls what the peripheral clock divider is */
-/* Values can range from 1-15                                    */
+/* Values can range from 1-15					 */
 #define CONFIG_SCLK_DIV			5
 
 #if ( CONFIG_CLKIN_HALF == 0 )
-#define CONFIG_VCO_HZ           ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
+#define CONFIG_VCO_HZ		( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
 #else
-#define CONFIG_VCO_HZ           (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
+#define CONFIG_VCO_HZ		(( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
 #endif
 
 #if (CONFIG_PLL_BYPASS == 0)
-#define CONFIG_CCLK_HZ          ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
-#define CONFIG_SCLK_HZ          ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
+#define CONFIG_CCLK_HZ		( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
+#define CONFIG_SCLK_HZ		( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
 #else
-#define CONFIG_CCLK_HZ          CONFIG_CLKIN_HZ
-#define CONFIG_SCLK_HZ          CONFIG_CLKIN_HZ
+#define CONFIG_CCLK_HZ		CONFIG_CLKIN_HZ
+#define CONFIG_SCLK_HZ		CONFIG_CLKIN_HZ
 #endif
 
-#define CONFIG_MEM_SIZE                 32             /* 128, 64, 32, 16 */
-#define CONFIG_MEM_ADD_WDTH              9             /* 8, 9, 10, 11    */
-#define CONFIG_MEM_MT48LC16M16A2TG_75    1
+#define CONFIG_MEM_SIZE			32	       /* 128, 64, 32, 16 */
+#define CONFIG_MEM_ADD_WDTH		 9	       /* 8, 9, 10, 11	  */
+#define CONFIG_MEM_MT48LC16M16A2TG_75	 1
 
 #define CONFIG_LOADS_ECHO	1
 
 
-#define CONFIG_COMMANDS			(CONFIG_CMD_DFL	| \
+#define CONFIG_COMMANDS			(CONFIG_CMD_DFL | \
 					 CFG_CMD_PING	| \
 					 CFG_CMD_ELF	| \
 					 CFG_CMD_I2C	| \
 					 CFG_CMD_JFFS2	| \
 					 CFG_CMD_DATE)
-#define CONFIG_BOOTARGS "root=/dev/mtdblock0 ip=192.168.0.15:192.168.0.2:192.168.0.1:255.255.255.0:ezkit:eth0:off"	
+#define CONFIG_BOOTARGS "root=/dev/mtdblock0 ip=192.168.0.15:192.168.0.2:192.168.0.1:255.255.255.0:ezkit:eth0:off"
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
-#define	CFG_PROMPT		"ezkit> "	/* Monitor Command Prompt */
+#define CFG_PROMPT		"ezkit> "	/* Monitor Command Prompt */
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size */
+#define CFG_CBSIZE		1024	/* Console I/O Buffer Size */
 #else
-#define	CFG_CBSIZE		256	/* Console I/O Buffer Size */
+#define CFG_CBSIZE		256	/* Console I/O Buffer Size */
 #endif
-#define	CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define	CFG_MAXARGS		16	/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define CFG_MAXARGS		16	/* max number of command args */
 #define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
 #define CFG_MEMTEST_START	0x00100000	/* memtest works on */
 #define CFG_MEMTEST_END		0x01F00000	/* 1 ... 31 MB in DRAM */
-#define	CFG_LOAD_ADDR		0x01000000	/* default load address */
-#define	CFG_HZ			1000	/* decrementer freq: 10 ms ticks */
+#define CFG_LOAD_ADDR		0x01000000	/* default load address */
+#define CFG_HZ			1000	/* decrementer freq: 10 ms ticks */
 #define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_SDRAM_BASE		0x00000000
 #define CFG_MAX_RAM_SIZE	0x02000000
 #define CFG_FLASH_BASE		0x20000000
 
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
 #define CFG_MONITOR_BASE	(CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 #define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
 #define CFG_GBL_DATA_SIZE	0x4000
 #define CFG_GBL_DATA_ADDR	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
 #define CONFIG_STACKBASE	(CFG_GBL_DATA_ADDR  - 4)
 
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 #define CFG_FLASH0_BASE		0x20000000
 #define CFG_FLASH1_BASE		0x20200000
 #define CFG_FLASH2_BASE		0x20280000
 #define CFG_MAX_FLASH_BANKS	3	/* max number of memory banks */
 #define CFG_MAX_FLASH_SECT	40	/* max number of sectors on one chip */
 
-#define	CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_IS_IN_FLASH	1
 #define CFG_ENV_ADDR		0x20020000
-#define	CFG_ENV_SECT_SIZE	0x10000	/* Total Size of Environment Sector */
+#define CFG_ENV_SECT_SIZE	0x10000 /* Total Size of Environment Sector */
 
 /* JFFS Partition offset set  */
 #define CFG_JFFS2_FIRST_BANK 0
 #define CFG_JFFS2_NUM_BANKS  1
 /* 512k reserved for u-boot */
-#define CFG_JFFS2_FIRST_SECTOR                 11
+#define CFG_JFFS2_FIRST_SECTOR		       11
 
 
 /*
  * Stack sizes
  */
-#define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
 
 #define POLL_MODE		1
 #define FLASH_TOT_SECT		40
@@ -123,7 +123,7 @@
 /*
  * Initialize PSD4256 registers for using I2C
  */
-#define	CONFIG_MISC_INIT_R
+#define CONFIG_MISC_INIT_R
 
 /*
  * I2C settings
@@ -144,7 +144,7 @@
 							*pFIO_FLAG_S = PF_SDA; \
 							asm("ssync;"); \
 						} \
-					else    { \
+					else	{ \
 							*pFIO_FLAG_C = PF_SDA; \
 							asm("ssync;"); \
 						}
@@ -152,7 +152,7 @@
 							*pFIO_FLAG_S = PF_SCL; \
 							asm("ssync;"); \
 						} \
-					else    { \
+					else	{ \
 							*pFIO_FLAG_C = PF_SCL; \
 							asm("ssync;"); \
 						}
@@ -166,15 +166,15 @@
 #define __ADSPBF533__		1
 
 /* 0xFF, 0x7BB07BB0, 0x22547BB0 */
-/* #define AMGCTLVAL            (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
-#define AMBCTL0VAL              (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL |    \
-                                ~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN)
-#define AMBCTL1VAL              (B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN |   \
-                                B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN)
+/* #define AMGCTLVAL		(AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
+#define AMBCTL0VAL		(B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL |	\
+				~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN)
+#define AMBCTL1VAL		(B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN |	\
+				B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN)
 */
-#define AMGCTLVAL               0xFF
-#define AMBCTL0VAL              0x7BB07BB0
-#define AMBCTL1VAL              0xFFC27BB0
+#define AMGCTLVAL		0xFF
+#define AMBCTL0VAL		0x7BB07BB0
+#define AMBCTL1VAL		0xFFC27BB0
 
 #define CONFIG_VDSP		1
 

include/configs/stamp.h

@@ -17,7 +17,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -40,7 +40,7 @@
 #define CONFIG_RTC_BF533		1
 
 /* FLASH/ETHERNET uses the same address range */
-#define SHARED_RESOURCES 		1
+#define SHARED_RESOURCES		1
 
 #define CONFIG_VDSP			1
 
@@ -49,37 +49,37 @@
  *
  */
 
-/* CONFIG_CLKIN_HZ is any value in Hz                            */
+/* CONFIG_CLKIN_HZ is any value in Hz				 */
 #define CONFIG_CLKIN_HZ			11059200
-/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN      */
-/*                                                  1=CLKIN/2    */
+/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN	 */
+/*						    1=CLKIN/2	 */
 #define CONFIG_CLKIN_HALF		0
-/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass  */
-/*                                               1=bypass PLL    */
-#define CONFIG_PLL_BYPASS       	0
-/* CONFIG_VCO_MULT controls what the multiplier of the PLL is.   */
-/* Values can range from 1-64                                    */
+/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass	 */
+/*						 1=bypass PLL	 */
+#define CONFIG_PLL_BYPASS		0
+/* CONFIG_VCO_MULT controls what the multiplier of the PLL is.	 */
+/* Values can range from 1-64					 */
 #define CONFIG_VCO_MULT			45
-/* CONFIG_CCLK_DIV controls what the core clock divider is       */
-/* Values can be 1, 2, 4, or 8 ONLY                              */
+/* CONFIG_CCLK_DIV controls what the core clock divider is	 */
+/* Values can be 1, 2, 4, or 8 ONLY				 */
 #define CONFIG_CCLK_DIV			1
 /* CONFIG_SCLK_DIV controls what the peripheral clock divider is */
-/* Values can range from 1-15                                    */
+/* Values can range from 1-15					 */
 #define CONFIG_SCLK_DIV			6
 
 /*
  * Network Settings
  */
 /* network support */
-#define CONFIG_IPADDR           192.168.0.15
-#define CONFIG_NETMASK          255.255.255.0
-#define CONFIG_GATEWAYIP        192.168.0.1
-#define CONFIG_SERVERIP         192.168.0.2
-#define CONFIG_HOSTNAME         STAMP
+#define CONFIG_IPADDR		192.168.0.15
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_GATEWAYIP	192.168.0.1
+#define CONFIG_SERVERIP		192.168.0.2
+#define CONFIG_HOSTNAME		STAMP
 #define CONFIG_ROOTPATH			/checkout/uClinux-dist/romfs
 
 /* To remove hardcoding and enable MAC storage in EEPROM  */
-/* #define CONFIG_ETHADDR               02:80:ad:20:31:b8 */
+/* #define CONFIG_ETHADDR		02:80:ad:20:31:b8 */
 
 /*
  * Command settings
@@ -90,17 +90,17 @@
 
 #define CONFIG_BOOTDELAY		5
 #define CONFIG_BOOT_RETRY_TIME		-1	/* Enable this if bootretry required, currently its disabled */
-#define CONFIG_BOOTCOMMAND 		"run ramboot"
+#define CONFIG_BOOTCOMMAND		"run ramboot"
 #define CONFIG_AUTOBOOT_PROMPT		"autoboot in %d seconds\n"
 
-#define CONFIG_COMMANDS			(CONFIG_CMD_DFL	| \
+#define CONFIG_COMMANDS			(CONFIG_CMD_DFL | \
 					 CFG_CMD_PING	| \
 					 CFG_CMD_ELF	| \
 					 CFG_CMD_I2C	| \
 					 CFG_CMD_CACHE	| \
-					 CFG_CMD_JFFS2  | \
+					 CFG_CMD_JFFS2	| \
 					 CFG_CMD_DATE)
-#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw"	
+#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw"
 
 #define CONFIG_EXTRA_ENV_SETTINGS												\
 	"ramargs=setenv bootargs root=/dev/mtdblock0 rw\0"							\
@@ -127,14 +127,14 @@
 #define CONFIG_BAUDRATE			57600
 #define CFG_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600, 115200 }
 
-#define	CFG_PROMPT			"stamp>"	/* Monitor Command Prompt */
+#define CFG_PROMPT			"stamp>"	/* Monitor Command Prompt */
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE			1024	/* Console I/O Buffer Size */
+#define CFG_CBSIZE			1024	/* Console I/O Buffer Size */
 #else
-#define	CFG_CBSIZE			256	/* Console I/O Buffer Size */
+#define CFG_CBSIZE			256	/* Console I/O Buffer Size */
 #endif
-#define	CFG_PBSIZE			(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define	CFG_MAXARGS			16	/* max number of command args */
+#define CFG_PBSIZE			(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define CFG_MAXARGS			16	/* max number of command args */
 #define CFG_BARGSIZE			CFG_CBSIZE	/* Boot Argument Buffer Size */
 
 #define CONFIG_LOADS_ECHO		1
@@ -154,9 +154,9 @@
  *
  */
 
-#define CFG_FLASH_CFI				/* The flash is CFI compatible  */
-#define CFG_FLASH_CFI_DRIVER			/* Use common CFI driver        */
-#define	CFG_FLASH_CFI_AMD_RESET
+#define CFG_FLASH_CFI				/* The flash is CFI compatible	*/
+#define CFG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
+#define CFG_FLASH_CFI_AMD_RESET
 
 #define CFG_ENV_IS_IN_FLASH		1
 
@@ -165,8 +165,8 @@
 #define CFG_MAX_FLASH_SECT		67		/* max number of sectors on one chip */
 
 #define CFG_ENV_ADDR			0x20020000
-#define	CFG_ENV_SIZE			0x10000
-#define CFG_ENV_SECT_SIZE 		0x10000	/* Total Size of Environment Sector */
+#define CFG_ENV_SIZE			0x10000
+#define CFG_ENV_SECT_SIZE		0x10000 /* Total Size of Environment Sector */
 
 #define CFG_FLASH_ERASE_TOUT		30000	/* Timeout for Chip Erase (in ms) */
 #define CFG_FLASH_ERASEBLOCK_TOUT	5000	/* Timeout for Block Erase (in ms) */
@@ -176,10 +176,10 @@
 #define CFG_JFFS2_FIRST_BANK 0
 #define CFG_JFFS2_NUM_BANKS  1
 /* 512k reserved for u-boot */
-#define CFG_JFFS2_FIRST_SECTOR 		11
+#define CFG_JFFS2_FIRST_SECTOR		11
 
-/* 
- * following timeouts shall be used once the 
+/*
+ * following timeouts shall be used once the
  * Flash real protection is enabled
  */
 #define CFG_FLASH_LOCK_TOUT		5	/* Timeout for Flash Set Lock Bit (in ms) */
@@ -204,7 +204,7 @@
 							*pFIO_FLAG_S = PF_SDA; \
 							asm("ssync;"); \
 						} \
-					else    { \
+					else	{ \
 							*pFIO_FLAG_C = PF_SDA; \
 							asm("ssync;"); \
 						}
@@ -212,7 +212,7 @@
 							*pFIO_FLAG_S = PF_SCL; \
 							asm("ssync;"); \
 						} \
-					else    { \
+					else	{ \
 							*pFIO_FLAG_C = PF_SCL; \
 							asm("ssync;"); \
 						}
@@ -236,9 +236,9 @@
 /*
  * IDE/ATA stuff
  */
-#undef  CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
-#undef  CONFIG_IDE_LED			/* no led for ide supported */
-#undef  CONFIG_IDE_RESET		/* no reset for ide supported */
+#undef	CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
+#undef	CONFIG_IDE_LED			/* no led for ide supported */
+#undef	CONFIG_IDE_RESET		/* no reset for ide supported */
 
 #define CFG_IDE_MAXBUS	1		/* max. 1 IDE busses */
 #define CFG_IDE_MAXDEVICE		(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
@@ -246,9 +246,9 @@
 #define CFG_ATA_BASE_ADDR		0x20200000
 #define CFG_ATA_IDE0_OFFSET		0x0000
 
-#define CFG_ATA_DATA_OFFSET		0x0020  /* Offset for data I/O */
-#define CFG_ATA_REG_OFFSET		0x0020  /* Offset for normal register accesses */
-#define CFG_ATA_ALT_OFFSET		0x0007  /* Offset for alternate registers */
+#define CFG_ATA_DATA_OFFSET		0x0020	/* Offset for data I/O */
+#define CFG_ATA_REG_OFFSET		0x0020	/* Offset for normal register accesses */
+#define CFG_ATA_ALT_OFFSET		0x0007	/* Offset for alternate registers */
 
 #define CFG_ATA_STRIDE			2
 #endif
@@ -258,23 +258,20 @@
  *
  */
 
-#define CONFIG_MEM_SIZE			128             /* 128, 64, 32, 16 */
-#define CONFIG_MEM_ADD_WDTH     	11             /* 8, 9, 10, 11    */
+#define CONFIG_MEM_SIZE			128		/* 128, 64, 32, 16 */
+#define CONFIG_MEM_ADD_WDTH		11	       /* 8, 9, 10, 11	  */
 #define CONFIG_MEM_MT48LC64M4A2FB_7E	1
 
 #define CFG_MEMTEST_START		0x00100000	/* memtest works on */
 #define CFG_MEMTEST_END			0x07EFFFFF	/* 1 ... 127 MB in DRAM */
-#define	CFG_LOAD_ADDR			0x01000000	/* default load address */
+#define CFG_LOAD_ADDR			0x01000000	/* default load address */
 
-#define	CFG_SDRAM_BASE			0x00000000
+#define CFG_SDRAM_BASE			0x00000000
 #define CFG_MAX_RAM_SIZE		0x08000000
 
-#define	CFG_MONITOR_LEN			(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MONITOR_LEN			(256 << 10)	/* Reserve 256 kB for Monitor	*/
 #define CFG_MONITOR_BASE		(CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)
 
-
-
-
 #if ( CONFIG_CLKIN_HALF == 0 )
 #define CONFIG_VCO_HZ			( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
 #else
@@ -289,14 +286,12 @@
 #define CONFIG_SCLK_HZ			CONFIG_CLKIN_HZ
 #endif
 
-
-
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_HZ				1000		/* 1ms time tick */ 
+#define CFG_HZ				1000		/* 1ms time tick */
 
-#define	CFG_MALLOC_LEN			(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CFG_MALLOC_LEN			(128 << 10)	/* Reserve 128 kB for malloc()	*/
 #define CFG_MALLOC_BASE			(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
 #define CFG_GBL_DATA_SIZE		0x4000
 #define CFG_GBL_DATA_ADDR		(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
@@ -309,25 +304,24 @@
 /*
  * Stack sizes
  */
-#define CONFIG_STACKSIZE        	(128*1024)      /* regular stack */
-
+#define CONFIG_STACKSIZE		(128*1024)	/* regular stack */
 
 /*
  * FLASH organization and environment definitions
  */
-#define	CFG_BOOTMAPSZ			(8 << 20)	/* Initial Memory map for Linux */
+#define CFG_BOOTMAPSZ			(8 << 20)	/* Initial Memory map for Linux */
 
 /* 0xFF, 0xBBC3BBc3, 0x99B39983 */
-/*#define AMGCTLVAL             (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
-#define AMBCTL0VAL              (B1WAT_11 | B1RAT_11 | B1HT_3 | B1ST_4 | B1TT_4 | B1RDYPOL |    \
-                                B1RDYEN | B0WAT_11 | B0RAT_11 | B0HT_3 | B0ST_4 | B0TT_4 | B0RDYPOL | B0RDYEN)
-#define AMBCTL1VAL              (B3WAT_9 | B3RAT_9 | B3HT_2 | B3ST_3 | B3TT_4 | B3RDYPOL |      \
-                                B3RDYEN | B2WAT_9 | B2RAT_9 | B2HT_2 | B2ST_4 | B2TT_4 | B2RDYPOL | B2RDYEN)
+/*#define AMGCTLVAL		(AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
+#define AMBCTL0VAL		(B1WAT_11 | B1RAT_11 | B1HT_3 | B1ST_4 | B1TT_4 | B1RDYPOL |	\
+				B1RDYEN | B0WAT_11 | B0RAT_11 | B0HT_3 | B0ST_4 | B0TT_4 | B0RDYPOL | B0RDYEN)
+#define AMBCTL1VAL		(B3WAT_9 | B3RAT_9 | B3HT_2 | B3ST_3 | B3TT_4 | B3RDYPOL |	\
+				B3RDYEN | B2WAT_9 | B2RAT_9 | B2HT_2 | B2ST_4 | B2TT_4 | B2RDYPOL | B2RDYEN)
 */
-#define AMGCTLVAL               0xFF
-#define AMBCTL0VAL              0xBBC3BBC3
-#define AMBCTL1VAL              0x99B39983
-#define CF_AMBCTL1VAL           0x99B3ffc2
+#define AMGCTLVAL		0xFF
+#define AMBCTL0VAL		0xBBC3BBC3
+#define AMBCTL1VAL		0x99B39983
+#define CF_AMBCTL1VAL		0x99B3ffc2
 
 #ifdef CONFIG_VDSP
 #define ET_EXEC_VDSP		0x8
@@ -336,5 +330,4 @@
 #define VDSP_ENTRY_ADDR		0xFFA00000
 #endif
 
-
 #endif

lib_blackfin/bf533_linux.c

@@ -46,7 +46,7 @@
 #define CMD_LINE_ADDR 0xFF900000  /* L1 scratchpad */
 
 #ifdef SHARED_RESOURCES
-        extern void swap_to(int device_id);
+	extern void swap_to(int device_id);
 #endif
 
 static char *make_command_line(void);

lib_blackfin/bf533_string.c

@@ -127,7 +127,7 @@ int strncmp(const char *cs, const char *ct, size_t count)
 void * memcpy(void * dest,const void *src,size_t count)
 {
 	char *tmp = (char *) dest, *s = (char *) src;
-	
+
 /* Turn off the cache, if destination in the L1 memory */
 	if ( (tmp >= (char *)L1_ISRAM) && (tmp < (char *)L1_ISRAM_END)
 		|| (tmp >= (char *)DATA_BANKA_SRAM) && (tmp < DATA_BANKA_SRAM_END)
@@ -150,7 +150,7 @@ void * memcpy(void * dest,const void *src,size_t count)
 
 void *dma_memcpy(void * dest,const void *src,size_t count)
 {
-	
+
 		*pMDMA_D0_IRQ_STATUS = DMA_DONE | DMA_ERR;
 
 		/* Copy sram functions from sdram to sram */
@@ -173,7 +173,7 @@ void *dma_memcpy(void * dest,const void *src,size_t count)
 		asm("ssync;");
 
 		*pMDMA_D0_CONFIG = ( WNR | DMAEN);
-		
+
 		while(*pMDMA_D0_IRQ_STATUS & DMA_RUN){
 			*pMDMA_D0_IRQ_STATUS |= (DMA_DONE | DMA_ERR);
 		}

lib_blackfin/blackfin_board.h

@@ -38,7 +38,7 @@ extern ulong uboot_end;
 ulong monitor_flash_len;
 
 
-#define VERSION_STRING_SIZE  150 /* including 40 bytes buffer to change any string */ 
+#define VERSION_STRING_SIZE  150 /* including 40 bytes buffer to change any string */
 #define VERSION_STRING_FORMAT "%s (%s - %s)\n"
 #define VERSION_STRING		U_BOOT_VERSION, __DATE__, __TIME__
 

lib_blackfin/board.c

@@ -147,7 +147,7 @@ void board_init_f(ulong bootflag)
 	addr = (CFG_GBL_DATA_ADDR + sizeof(gd_t));
 
 	/* Align to 4 byte boundary */
-        addr &= ~(4 - 1);
+	addr &= ~(4 - 1);
 	bd = (bd_t*)addr;
 	gd->bd = bd;
 	memset((void *) bd, 0, sizeof(bd_t));

lib_blackfin/cache.c

@@ -26,16 +26,15 @@
  */
 
 /* for now: just dummy functions to satisfy the linker */
-extern void blackfin_icache_range(unsigned long *,unsigned long *);
-extern void blackfin_dcache_range(unsigned long *,unsigned long *);
-void flush_cache(unsigned long dummy1, unsigned long dummy2)
+extern void blackfin_icache_range (unsigned long *, unsigned long *);
+extern void blackfin_dcache_range (unsigned long *, unsigned long *);
+void flush_cache (unsigned long dummy1, unsigned long dummy2)
 {
-	if(icache_status()){
-		blackfin_icache_flush_range(dummy1,dummy1+dummy2);
-		}
-	if(dcache_status()){
-		blackfin_dcache_flush_range(dummy1,dummy1+dummy2);
-		}
+	if (icache_status ()) {
+		blackfin_icache_flush_range (dummy1, dummy1 + dummy2);
+	}
+	if (dcache_status ()) {
+		blackfin_dcache_flush_range (dummy1, dummy1 + dummy2);
+	}
 	return;
 }
-

lib_blackfin/muldi3.c

@@ -80,13 +80,13 @@ DItype __muldi3 (DItype u, DItype v)
 {
 	DIunion w;
 	DIunion uu, vv;
- 
+
 	uu.ll = u,
 	vv.ll = v;
 	/*  panic("kernel panic for __muldi3"); */
 	w.ll = __umulsidi3 (uu.s.low, vv.s.low);
 	w.s.high += ((USItype) uu.s.low * (USItype) vv.s.high
 	+ (USItype) uu.s.high * (USItype) vv.s.low);
- 
+
 	return w.ll;
 }

rtc/bf533_rtc.c

@@ -19,7 +19,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
- * Real Time Clock interface of ADI21535 (Blackfin) for uCLinux 
+ * Real Time Clock interface of ADI21535 (Blackfin) for uCLinux
  *
  * Copyright (C) 2003 Motorola Corporation.  All rights reserved.
  * 				Richard Xiao (A2590C@email.mot.com)
@@ -42,7 +42,7 @@
  *	1.10b	Andrew Morton: SMP lock fix
  *	1.10c	Cesar Barros: SMP locking fixes and cleanup
  *	1.10d	Paul Gortmaker: delete paranoia check in rtc_exit
- *	1.10e   LG Soft India: Register access is different in BF533. 	
+ *	1.10e   LG Soft India: Register access is different in BF533.
  */
 
 #include <common.h>
@@ -54,62 +54,64 @@
 #include <asm/blackfin.h>
 #include <asm/cpu/bf533_rtc.h>
 
-void rtc_reset(void)
+void rtc_reset (void)
 {
 	return;			/* nothing to do */
 }
 
 /* Wait for pending writes to complete */
-void wait_for_complete(void)
+void wait_for_complete (void)
 {
 	while (!(*(volatile unsigned short *) RTC_ISTAT & 0x8000)) {
-		printf("");
+		printf ("");
 	}
 	*(volatile unsigned short *) RTC_ISTAT = 0x8000;
 }
 
 /* Enable the RTC prescaler enable register */
-void rtc_init()
+void rtc_init ()
 {
 	*(volatile unsigned short *) RTC_PREN = 0x1;
-	wait_for_complete();
+	wait_for_complete ();
 }
 
-/* Set the time. Get the time_in_secs which is the number of seconds since Jan 1970 and set the RTC registers 
+/* Set the time. Get the time_in_secs which is the number of seconds since Jan 1970 and set the RTC registers
  * based on this value.
  */
 void rtc_set (struct rtc_time *tmp)
 {
 	unsigned long n_days_1970 = 0;
-	unsigned long n_secs_rem  = 0;
-	unsigned long n_hrs	  = 0;
-	unsigned long n_mins	  = 0;
-	unsigned long n_secs	  = 0;
+	unsigned long n_secs_rem = 0;
+	unsigned long n_hrs = 0;
+	unsigned long n_mins = 0;
+	unsigned long n_secs = 0;
 	unsigned long time_in_secs;
 
-	if(tmp == NULL) {
-		printf("Error setting the date/time \n");
+	if (tmp == NULL) {
+		printf ("Error setting the date/time \n");
 		return;
 	}
 
-	time_in_secs = mktime(tmp->tm_year, tmp->tm_mon, tmp->tm_mday,tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+	time_in_secs =
+		mktime (tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_hour,
+			tmp->tm_min, tmp->tm_sec);
 
 	/* Compute no. of days since 1970 */
 	n_days_1970 = (unsigned long) (time_in_secs / (NUM_SECS_IN_DAY));
 
 	/* From the remining secs, compute the hrs(0-23), mins(0-59) and secs(0-59) */
-	n_secs_rem = (unsigned long)(time_in_secs % (NUM_SECS_IN_DAY));
-	n_hrs 	= n_secs_rem / (NUM_SECS_IN_HOUR);
+	n_secs_rem = (unsigned long) (time_in_secs % (NUM_SECS_IN_DAY));
+	n_hrs = n_secs_rem / (NUM_SECS_IN_HOUR);
 	n_secs_rem = n_secs_rem % (NUM_SECS_IN_HOUR);
 	n_mins = n_secs_rem / (NUM_SECS_IN_MIN);
 	n_secs = n_secs_rem % (NUM_SECS_IN_MIN);
-	
+
 	/* Store the new time in the RTC_STAT register */
 	*(volatile unsigned long *) RTC_STAT =
 		((n_days_1970 << DAY_BITS_OFF) | (n_hrs << HOUR_BITS_OFF) |
-		(n_mins << MIN_BITS_OFF) | (n_secs << SEC_BITS_OFF));
+		 (n_mins << MIN_BITS_OFF) | (n_secs << SEC_BITS_OFF));
 
-	wait_for_complete();
+	wait_for_complete ();
 }
 
 /* Read the time from the RTC_STAT. time_in_seconds is seconds since Jan 1970 */
@@ -117,16 +119,16 @@ void rtc_get (struct rtc_time *tmp)
 {
 	unsigned long cur_rtc_stat = 0;
 	unsigned long time_in_sec;
-	unsigned long tm_sec = 0, tm_min = 0, tm_hour = 0, tm_day = 0; 
+	unsigned long tm_sec = 0, tm_min = 0, tm_hour = 0, tm_day = 0;
 
-	if(tmp == NULL) {
-		printf("Error getting the date/time \n");
+	if (tmp == NULL) {
+		printf ("Error getting the date/time \n");
 		return;
 	}
 
 	/* Read the RTC_STAT register */
 	cur_rtc_stat = *(volatile unsigned long *) RTC_STAT;
-	
+
 	/* Get the secs (0-59), mins (0-59), hrs (0-23) and the days since Jan 1970 */
 	tm_sec = (cur_rtc_stat >> SEC_BITS_OFF) & 0x3f;
 	tm_min = (cur_rtc_stat >> MIN_BITS_OFF) & 0x3f;
@@ -134,10 +136,10 @@ void rtc_get (struct rtc_time *tmp)
 	tm_day = (cur_rtc_stat >> DAY_BITS_OFF) & 0x7fff;
 
 	/* Calculate the total number of seconds since Jan 1970 */
-	time_in_sec 	= 	(tm_sec) + 
-					MIN_TO_SECS(tm_min) + 
-						HRS_TO_SECS(tm_hour) + 
-							DAYS_TO_SECS(tm_day);
-	to_tm(time_in_sec,tmp);	
+	time_in_sec = (tm_sec) +
+		MIN_TO_SECS (tm_min) +
+		HRS_TO_SECS (tm_hour) +
+		DAYS_TO_SECS (tm_day);
+	to_tm (time_in_sec, tmp);
 }
-#endif	/* CONFIG_RTC_BF533 && CFG_CMD_DATE */
+#endif /* CONFIG_RTC_BF533 && CFG_CMD_DATE */