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@@ -88,15 +88,20 @@
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/* unused GPT0 COMP reg */
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#define CFG_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
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/* 440EPx errata CHIP 11 */
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+#define CFG_OCM_SIZE (16 << 10)
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/* Additional registers for watchdog timer post test */
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#define CFG_WATCHDOG_TIME_ADDR (CFG_PERIPHERAL_BASE + GPT0_MASK2)
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#define CFG_WATCHDOG_FLAGS_ADDR (CFG_PERIPHERAL_BASE + GPT0_MASK1)
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#define CFG_DSPIC_TEST_ADDR CFG_WATCHDOG_FLAGS_ADDR
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+#define CFG_OCM_STATUS_ADDR CFG_WATCHDOG_FLAGS_ADDR
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#define CFG_WATCHDOG_MAGIC 0x12480000
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#define CFG_WATCHDOG_MAGIC_MASK 0xFFFF0000
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#define CFG_DSPIC_TEST_MASK 0x00000001
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+#define CFG_OCM_STATUS_OK 0x00009A00
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+#define CFG_OCM_STATUS_FAIL 0x0000A300
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+#define CFG_OCM_STATUS_MASK 0x0000FF00
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/*-----------------------------------------------------------------------
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* Serial Port
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@@ -162,6 +167,7 @@
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CFG_POST_FPU | \
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CFG_POST_I2C | \
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CFG_POST_MEMORY | \
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+ CFG_POST_OCM | \
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CFG_POST_RTC | \
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CFG_POST_SPR | \
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CFG_POST_UART | \
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Yuri Tikhonov