|
@@ -71,10 +71,10 @@
|
|
#define EXYNOS5_GPIO_PART1_BASE 0x11400000
|
|
#define EXYNOS5_GPIO_PART1_BASE 0x11400000
|
|
#define EXYNOS5_MIPI_DSIM_BASE 0x11D00000
|
|
#define EXYNOS5_MIPI_DSIM_BASE 0x11D00000
|
|
#define EXYNOS5_USB_HOST_EHCI_BASE 0x12110000
|
|
#define EXYNOS5_USB_HOST_EHCI_BASE 0x12110000
|
|
|
|
+#define EXYNOS5_USBPHY_BASE 0x12130000
|
|
|
|
+#define EXYNOS5_USBOTG_BASE 0x12140000
|
|
#define EXYNOS5_MMC_BASE 0x12200000
|
|
#define EXYNOS5_MMC_BASE 0x12200000
|
|
#define EXYNOS5_SROMC_BASE 0x12250000
|
|
#define EXYNOS5_SROMC_BASE 0x12250000
|
|
-#define EXYNOS5_USBOTG_BASE 0x12480000
|
|
|
|
-#define EXYNOS5_USBPHY_BASE 0x12480000
|
|
|
|
#define EXYNOS5_UART_BASE 0x12C00000
|
|
#define EXYNOS5_UART_BASE 0x12C00000
|
|
#define EXYNOS5_PWMTIMER_BASE 0x12DD0000
|
|
#define EXYNOS5_PWMTIMER_BASE 0x12DD0000
|
|
#define EXYNOS5_GPIO_PART2_BASE 0x13400000
|
|
#define EXYNOS5_GPIO_PART2_BASE 0x13400000
|