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@@ -904,6 +904,20 @@ static int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon)
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return 0;
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}
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+void clock_ll_start_uart(enum periph_id periph_id)
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+{
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+ /* Assert UART reset and enable clock */
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+ reset_set_enable(periph_id, 1);
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+ clock_enable(periph_id);
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+ clock_ll_set_source(periph_id, 0); /* UARTx_CLK_SRC = 00, PLLP_OUT0 */
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+
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+ /* wait for 2us */
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+ udelay(2);
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+
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+ /* De-assert reset to UART */
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+ reset_set_enable(periph_id, 0);
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+}
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+
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int clock_verify(void)
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{
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struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH);
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