MPC512x: use I/O accessors instead of pointer accesses

This commit changes the MPC512x code to use I/O accessor calls (i.e.
out_*() and in_*()) instead of using deprecated pointer accesses.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: John Rigby <jcrigby@gmail.com>

board/freescale/mpc5121ads/mpc5121ads.c

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2007 DENX Software Engineering
+ * (C) Copyright 2007-2009 DENX Software Engineering
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -22,9 +22,9 @@
  */
 
 #include <common.h>
-#include <mpc512x.h>
 #include <asm/bitops.h>
 #include <command.h>
+#include <asm/io.h>
 #include <asm/processor.h>
 #include <fdt_support.h>
 #ifdef CONFIG_MISC_INIT_R
@@ -34,6 +34,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 extern int mpc5121_diu_init(void);
+extern void ide_set_reset(int idereset);
 
 /* Clocks in use */
 #define SCCR1_CLOCKS_EN	(CLOCK_SCCR1_CFG_EN |				\
@@ -59,22 +60,24 @@ long int fixed_sdram(void);
 int board_early_init_f (void)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	u32 lpcaw;
+	u32 lpcaw, spridr;
 
 	/*
 	 * Initialize Local Window for the CPLD registers access (CS2 selects
 	 * the CPLD chip)
 	 */
-	im->sysconf.lpcs2aw = CSAW_START(CONFIG_SYS_CPLD_BASE) |
-			      CSAW_STOP(CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_SIZE);
-	im->lpc.cs_cfg[2] = CONFIG_SYS_CS2_CFG;
+	out_be32(&im->sysconf.lpcs2aw,
+		CSAW_START(CONFIG_SYS_CPLD_BASE) |
+		CSAW_STOP(CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_SIZE)
+	);
+	out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG);
 
 	/*
 	 * According to MPC5121e RM, configuring local access windows should
 	 * be followed by a dummy read of the config register that was
 	 * modified last and an isync
 	 */
-	lpcaw = im->sysconf.lpcs2aw;
+	lpcaw = in_be32(&im->sysconf.lpcs6aw);
 	__asm__ __volatile__ ("isync");
 
 	/*
@@ -85,29 +88,32 @@ int board_early_init_f (void)
 	 */
 
 #ifdef CONFIG_ADS5121_REV2
-	*((volatile u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) = 0xC1;
+	out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1);
 #else
-	if (*((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) & 0x04) {
-		*((volatile u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) = 0xC1;
+	if (in_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) & 0x04) {
+		out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1);
 	} else {
 		/* running from Backup flash */
-		*((volatile u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) = 0x32;
+		out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0x32);
 	}
 #endif
 	/*
 	 * Configure Flash Speed
 	 */
-	*((volatile u32 *)(CONFIG_SYS_IMMR + LPC_OFFSET + CS0_CONFIG)) = CONFIG_SYS_CS0_CFG;
-	if (SVR_MJREV (im->sysconf.spridr) >= 2) {
-		*((volatile u32 *)(CONFIG_SYS_IMMR + LPC_OFFSET + CS_ALE_TIMING_CONFIG)) = CONFIG_SYS_CS_ALETIMING;
-	}
+	out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
+
+	spridr = in_be32(&im->sysconf.spridr);
+
+	if (SVR_MJREV (spridr) >= 2)
+		out_be32 (&im->lpc.altr, CONFIG_SYS_CS_ALETIMING);
+
 	/*
 	 * Enable clocks
 	 */
-	im->clk.sccr[0] = SCCR1_CLOCKS_EN;
-	im->clk.sccr[1] = SCCR2_CLOCKS_EN;
+	out_be32 (&im->clk.sccr[0], SCCR1_CLOCKS_EN);
+	out_be32 (&im->clk.sccr[1], SCCR2_CLOCKS_EN);
 #if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
-	im->clk.sccr[1] |= CLOCK_SCCR2_IIM_EN;
+	setbits_be32 (&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
 #endif
 
 	return 0;
@@ -134,83 +140,83 @@ long int fixed_sdram (void)
 	u32 i;
 
 	/* Initialize IO Control */
-	im->io_ctrl.io_control_mem = IOCTRL_MUX_DDR;
+	out_be32 (&im->io_ctrl.io_control_mem, IOCTRL_MUX_DDR);
 
 	/* Initialize DDR Local Window */
-	im->sysconf.ddrlaw.bar = CONFIG_SYS_DDR_BASE & 0xFFFFF000;
-	im->sysconf.ddrlaw.ar = msize_log2 - 1;
+	out_be32 (&im->sysconf.ddrlaw.bar, CONFIG_SYS_DDR_BASE & 0xFFFFF000);
+	out_be32 (&im->sysconf.ddrlaw.ar, msize_log2 - 1);
 
 	/*
 	 * According to MPC5121e RM, configuring local access windows should
 	 * be followed by a dummy read of the config register that was
 	 * modified last and an isync
 	 */
-	i = im->sysconf.ddrlaw.ar;
+	in_be32(&im->sysconf.ddrlaw.ar);
 	__asm__ __volatile__ ("isync");
 
 	/* Enable DDR */
-	im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_EN;
+	out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_EN);
 
 	/* Initialize DDR Priority Manager */
-	im->mddrc.prioman_config1 = CONFIG_SYS_MDDRCGRP_PM_CFG1;
-	im->mddrc.prioman_config2 = CONFIG_SYS_MDDRCGRP_PM_CFG2;
-	im->mddrc.hiprio_config = CONFIG_SYS_MDDRCGRP_HIPRIO_CFG;
-	im->mddrc.lut_table0_main_upper = CONFIG_SYS_MDDRCGRP_LUT0_MU;
-	im->mddrc.lut_table0_main_lower = CONFIG_SYS_MDDRCGRP_LUT0_ML;
-	im->mddrc.lut_table1_main_upper = CONFIG_SYS_MDDRCGRP_LUT1_MU;
-	im->mddrc.lut_table1_main_lower = CONFIG_SYS_MDDRCGRP_LUT1_ML;
-	im->mddrc.lut_table2_main_upper = CONFIG_SYS_MDDRCGRP_LUT2_MU;
-	im->mddrc.lut_table2_main_lower = CONFIG_SYS_MDDRCGRP_LUT2_ML;
-	im->mddrc.lut_table3_main_upper = CONFIG_SYS_MDDRCGRP_LUT3_MU;
-	im->mddrc.lut_table3_main_lower = CONFIG_SYS_MDDRCGRP_LUT3_ML;
-	im->mddrc.lut_table4_main_upper = CONFIG_SYS_MDDRCGRP_LUT4_MU;
-	im->mddrc.lut_table4_main_lower = CONFIG_SYS_MDDRCGRP_LUT4_ML;
-	im->mddrc.lut_table0_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT0_AU;
-	im->mddrc.lut_table0_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT0_AL;
-	im->mddrc.lut_table1_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT1_AU;
-	im->mddrc.lut_table1_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT1_AL;
-	im->mddrc.lut_table2_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT2_AU;
-	im->mddrc.lut_table2_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT2_AL;
-	im->mddrc.lut_table3_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT3_AU;
-	im->mddrc.lut_table3_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT3_AL;
-	im->mddrc.lut_table4_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT4_AU;
-	im->mddrc.lut_table4_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT4_AL;
+	out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1);
+	out_be32(&im->mddrc.prioman_config2, CONFIG_SYS_MDDRCGRP_PM_CFG2);
+	out_be32(&im->mddrc.hiprio_config, CONFIG_SYS_MDDRCGRP_HIPRIO_CFG);
+	out_be32(&im->mddrc.lut_table0_main_upper, CONFIG_SYS_MDDRCGRP_LUT0_MU);
+	out_be32(&im->mddrc.lut_table0_main_lower, CONFIG_SYS_MDDRCGRP_LUT0_ML);
+	out_be32(&im->mddrc.lut_table1_main_upper, CONFIG_SYS_MDDRCGRP_LUT1_MU);
+	out_be32(&im->mddrc.lut_table1_main_lower, CONFIG_SYS_MDDRCGRP_LUT1_ML);
+	out_be32(&im->mddrc.lut_table2_main_upper, CONFIG_SYS_MDDRCGRP_LUT2_MU);
+	out_be32(&im->mddrc.lut_table2_main_lower, CONFIG_SYS_MDDRCGRP_LUT2_ML);
+	out_be32(&im->mddrc.lut_table3_main_upper, CONFIG_SYS_MDDRCGRP_LUT3_MU);
+	out_be32(&im->mddrc.lut_table3_main_lower, CONFIG_SYS_MDDRCGRP_LUT3_ML);
+	out_be32(&im->mddrc.lut_table4_main_upper, CONFIG_SYS_MDDRCGRP_LUT4_MU);
+	out_be32(&im->mddrc.lut_table4_main_lower, CONFIG_SYS_MDDRCGRP_LUT4_ML);
+	out_be32(&im->mddrc.lut_table0_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT0_AU);
+	out_be32(&im->mddrc.lut_table0_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT0_AL);
+	out_be32(&im->mddrc.lut_table1_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT1_AU);
+	out_be32(&im->mddrc.lut_table1_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT1_AL);
+	out_be32(&im->mddrc.lut_table2_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT2_AU);
+	out_be32(&im->mddrc.lut_table2_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT2_AL);
+	out_be32(&im->mddrc.lut_table3_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT3_AU);
+	out_be32(&im->mddrc.lut_table3_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT3_AL);
+	out_be32(&im->mddrc.lut_table4_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT4_AU);
+	out_be32(&im->mddrc.lut_table4_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT4_AL);
 
 	/* Initialize MDDRC */
-	im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG;
-	im->mddrc.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0;
-	im->mddrc.ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1;
-	im->mddrc.ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2;
+	out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG);
+	out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0);
+	out_be32(&im->mddrc.ddr_time_config1, CONFIG_SYS_MDDRC_TIME_CFG1);
+	out_be32(&im->mddrc.ddr_time_config2, CONFIG_SYS_MDDRC_TIME_CFG2);
 
 	/* Initialize DDR */
 	for (i = 0; i < 10; i++)
-		im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
-
-	im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
-	im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
-	im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH;
-	im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
-	im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH;
-	im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
-	im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP;
-	im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
-	im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM2;
-	im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
-	im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
-	im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM2;
-	im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM3;
-	im->mddrc.ddr_command = CONFIG_SYS_MICRON_EN_DLL;
-	im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP;
-	im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
-	im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH;
-	im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP;
-	im->mddrc.ddr_command = CONFIG_SYS_MICRON_OCD_DEFAULT;
-	im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
-	im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
+		out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
+
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM3);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EN_DLL);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_OCD_DEFAULT);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
 
 	/* Start MDDRC */
-	im->mddrc.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0_RUN;
-	im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_RUN;
+	out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0_RUN);
+	out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_RUN);
 
 	return msize;
 }
@@ -249,49 +255,49 @@ int misc_init_r(void)
 static  iopin_t ioregs_init[] = {
 	/* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
 	{
-		IOCTL_SPDIF_TXCLK, 3, 0,
+		offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
 		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
 	},
 	/* Set highest Slew on 9 PATA pins */
 	{
-		IOCTL_PATA_CE1, 9, 1,
+		offsetof(struct ioctrl512x, io_control_pata_ce1), 9, 1,
 		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
 	},
 	/* FUNC1=FEC_COL Sets Next 15 to FEC pads */
 	{
-		IOCTL_PSC0_0, 15, 0,
+		offsetof(struct ioctrl512x, io_control_psc0_0), 15, 0,
 		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
 	},
 	/* FUNC1=SPDIF_TXCLK */
 	{
-		IOCTL_LPC_CS1, 1, 0,
+		offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, 0,
 		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 		IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
 	},
 	/* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */
 	{
-		IOCTL_I2C1_SCL, 2, 0,
+		offsetof(struct ioctrl512x, io_control_i2c1_scl), 2, 0,
 		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 		IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
 	},
 	/* FUNC2=DIU CLK */
 	{
-		IOCTL_PSC6_0, 1, 0,
+		offsetof(struct ioctrl512x, io_control_psc6_0), 1, 0,
 		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 		IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
 	},
 	/* FUNC2=DIU_HSYNC */
 	{
-		IOCTL_PSC6_1, 1, 0,
+		offsetof(struct ioctrl512x, io_control_psc6_1), 1, 0,
 		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
 	},
 	/* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
 	{
-		IOCTL_PSC6_4, 26, 0,
+		offsetof(struct ioctrl512x, io_control_psc6_4), 26, 0,
 		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
 	}
@@ -300,7 +306,7 @@ static  iopin_t ioregs_init[] = {
 static  iopin_t rev2_silicon_pci_ioregs_init[] = {
 	/* FUNC0=PCI Sets next 54 to PCI pads */
 	{
-		IOCTL_PCI_AD31, 54, 0,
+		offsetof(struct ioctrl512x, io_control_pci_ad31), 54, 0,
 		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0)
 	}
 };
@@ -310,6 +316,7 @@ int checkboard (void)
 	ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00);
 	uchar cpld_rev = *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x02);
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	u32 spridr = in_be32(&im->sysconf.spridr);
 
 	printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n",
 		brd_rev, cpld_rev);
@@ -317,7 +324,7 @@ int checkboard (void)
 	/* initialize function mux & slew rate IO inter alia on IO Pins  */
 	iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
 
-	if (SVR_MJREV (im->sysconf.spridr) >= 2)
+	if (SVR_MJREV (spridr) >= 2)
 		iopin_initialize(rev2_silicon_pci_ioregs_init, 1);
 
 	return 0;

cpu/mpc512x/cpu_init.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
- * (C) Copyright 2007 DENX Software Engineering
+ * Copyright (C) 2007-2009 DENX Software Engineering
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -26,6 +26,8 @@
 
 #include <common.h>
 #include <mpc512x.h>
+#include <asm/io.h>
+#include <asm/processor.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -46,30 +48,34 @@ void cpu_init_f (volatile immap_t * im)
 
 #ifdef CONFIG_SYS_ACR_PIPE_DEP
 	/* Arbiter pipeline depth */
-	im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) |
-			  (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
+	out_be32(&im->arbiter.acr,
+		(im->arbiter.acr & ~ACR_PIPE_DEP) |
+		(CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT)
+	);
 #endif
 
 #ifdef CONFIG_SYS_ACR_RPTCNT
 	/* Arbiter repeat count */
-	im->arbiter.acr = ((im->arbiter.acr & ~(ACR_RPTCNT)) |
-			   (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT));
+	out_be32(im->arbiter.acr,
+		(im->arbiter.acr & ~(ACR_RPTCNT)) |
+		(CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT)
+	);
 #endif
 
 	/* RSR - Reset Status Register - clear all status */
 	gd->reset_status = im->reset.rsr;
-	im->reset.rsr = ~(RSR_RES);
+	out_be32(&im->reset.rsr, ~RSR_RES);
 
 	/*
 	 * RMR - Reset Mode Register - enable checkstop reset
 	 */
-	im->reset.rmr = (RMR_CSRE & (1 << RMR_CSRE_SHIFT));
+	out_be32(&im->reset.rmr, RMR_CSRE & (1 << RMR_CSRE_SHIFT));
 
 	/* Set IPS-CSB divider: IPS = 1/2 CSB */
-	ips_div = im->clk.scfr[0];
+	ips_div = in_be32(&im->clk.scfr[0]);
 	ips_div &= ~(SCFR1_IPS_DIV_MASK);
 	ips_div |= SCFR1_IPS_DIV << SCFR1_IPS_DIV_SHIFT;
-	im->clk.scfr[0] = ips_div;
+	out_be32(&im->clk.scfr[0], ips_div);
 
 	/*
 	 * Enable Time Base/Decrementer
@@ -78,7 +84,7 @@ void cpu_init_f (volatile immap_t * im)
 	 * have udelay() working; if not enabled, usually leads to a hang, like
 	 * during FLASH chip identification etc.
 	 */
-	im->sysconf.spcr |= SPCR_TBEN;
+	setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
 }
 
 int cpu_init_r (void)

cpu/mpc512x/i2c.c

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2003 - 2007
+ * (C) Copyright 2003 - 2009
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -24,6 +24,7 @@
  */
 
 #include <common.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -32,8 +33,6 @@ DECLARE_GLOBAL_DATA_PTR;
 #include <mpc512x.h>
 #include <i2c.h>
 
-#define immr ((immap_t *)CONFIG_SYS_IMMR)
-
 /* by default set I2C bus 0 active */
 static unsigned int bus_num = 0;
 
@@ -56,29 +55,24 @@ static int  mpc_get_fdr(int);
 
 static int mpc_reg_in (volatile u32 *reg)
 {
-	int ret = *reg >> 24;
-	__asm__ __volatile__ ("eieio");
+	int ret = in_be32(reg) >> 24;
+
 	return ret;
 }
 
 static void mpc_reg_out (volatile u32 *reg, int val, int mask)
 {
-	int tmp;
-
 	if (!mask) {
-		*reg = val << 24;
+		out_be32(reg, val << 24);
 	} else {
-		tmp = mpc_reg_in (reg);
-		*reg = ((tmp & ~mask) | (val & mask)) << 24;
+		clrsetbits_be32(reg, mask << 24, (val & mask) << 24);
 	}
-	__asm__ __volatile__ ("eieio");
-
-	return;
 }
 
 static int wait_for_bb (void)
 {
-	i2c512x_dev_t *regs = &immr->i2c.dev[bus_num];
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num];
 	int timeout = I2C_TIMEOUT;
 	int status;
 
@@ -101,7 +95,8 @@ static int wait_for_bb (void)
 
 static int wait_for_pin (int *status)
 {
-	i2c512x_dev_t *regs = &immr->i2c.dev[bus_num];
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num];
 	int timeout = I2C_TIMEOUT;
 
 	*status = mpc_reg_in (&regs->msr);
@@ -122,7 +117,8 @@ static int wait_for_pin (int *status)
 
 static int do_address (uchar chip, char rdwr_flag)
 {
-	i2c512x_dev_t *regs = &immr->i2c.dev[bus_num];
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num];
 	int status;
 
 	chip <<= 1;
@@ -147,7 +143,8 @@ static int do_address (uchar chip, char rdwr_flag)
 
 static int send_bytes (uchar chip, char *buf, int len)
 {
-	i2c512x_dev_t *regs = &immr->i2c.dev[bus_num];
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num];
 	int wrcount;
 	int status;
 
@@ -170,7 +167,8 @@ static int send_bytes (uchar chip, char *buf, int len)
 
 static int receive_bytes (uchar chip, char *buf, int len)
 {
-	i2c512x_dev_t *regs = &immr->i2c.dev[bus_num];
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num];
 	int dummy   = 1;
 	int rdcount = 0;
 	int status;
@@ -208,9 +206,12 @@ static int receive_bytes (uchar chip, char *buf, int len)
 
 void i2c_init (int speed, int saddr)
 {
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	int i;
-	for(i = 0; i < I2C_BUS_CNT; i++){
-		i2c512x_dev_t *regs = &immr->i2c.dev[i];
+
+	for (i = 0; i < I2C_BUS_CNT; i++){
+		volatile i2c512x_dev_t *regs = &im->i2c.dev[i];
+
 		mpc_reg_out (&regs->mcr, 0, 0);
 
 		/* Set clock */
@@ -223,10 +224,10 @@ void i2c_init (int speed, int saddr)
 	}
 
 	/* Disable interrupts */
-	immr->i2c.icr = 0;
+	out_be32(&im->i2c.icr, 0);
+
 	/* Turn off filters */
-	immr->i2c.mifr = 0;
-	return;
+	out_be32(&im->i2c.mifr, 0);
 }
 
 static int mpc_get_fdr (int speed)
@@ -281,7 +282,8 @@ static int mpc_get_fdr (int speed)
 
 int i2c_probe (uchar chip)
 {
-	i2c512x_dev_t *regs = &immr->i2c.dev[bus_num];
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num];
 	int i;
 
 	for (i = 0; i < I2C_RETRIES; i++) {
@@ -302,8 +304,9 @@ int i2c_probe (uchar chip)
 
 int i2c_read (uchar chip, uint addr, int alen, uchar *buf, int len)
 {
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num];
 	char xaddr[4];
-	i2c512x_dev_t *regs = &immr->i2c.dev[bus_num];
 	int ret = -1;
 
 	xaddr[0] = (addr >> 24) & 0xFF;
@@ -346,8 +349,9 @@ Done:
 
 int i2c_write (uchar chip, uint addr, int alen, uchar *buf, int len)
 {
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num];
 	char xaddr[4];
-	i2c512x_dev_t *regs = &immr->i2c.dev[bus_num];
 	int ret = -1;
 
 	xaddr[0] = (addr >> 24) & 0xFF;

cpu/mpc512x/ide.c

@@ -23,47 +23,46 @@
 
 #include <common.h>
 #include <command.h>
+#include <asm/io.h>
 #include <asm/processor.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 #if defined(CONFIG_IDE_RESET)
 
+void ide_set_reset (int idereset)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	debug ("ide_set_reset(%d)\n", idereset);
+
+	if (idereset) {
+		out_be32(&im->pata.pata_ata_control, 0);
+	} else {
+		out_be32(&im->pata.pata_ata_control, FSL_ATA_CTRL_ATA_RST_B);
+	}
+	udelay(100);
+}
+
 void init_ide_reset (void)
 {
-	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 	debug ("init_ide_reset\n");
 
 	/*
 	 * Clear the reset bit to reset the interface
 	 * cf. RefMan MPC5121EE: 28.4.1 Resetting the ATA Bus
 	 */
-	immr->pata.pata_ata_control = 0;
-	udelay(100);
-	/* Assert the reset bit to enable the interface */
-	immr->pata.pata_ata_control = FSL_ATA_CTRL_ATA_RST_B;
-	udelay(100);
-}
+	ide_set_reset(1);
 
-void ide_set_reset (int idereset)
-{
-	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
-	debug ("ide_set_reset(%d)\n", idereset);
+	/* Assert the reset bit to enable the interface */
+	ide_set_reset(0);
 
-	if (idereset) {
-		immr->pata.pata_ata_control = 0;
-		udelay(100);
-	} else {
-		immr->pata.pata_ata_control = FSL_ATA_CTRL_ATA_RST_B;
-		udelay(100);
-	}
 }
 
 #define CALC_TIMING(t) (t + period - 1) / period
 
 int ide_preinit (void)
 {
-	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	long t;
 	const struct {
 		short t0;
@@ -92,13 +91,13 @@ int ide_preinit (void)
 			u8 field3;
 			u8 field4;
 		}bytes;
-	}cfg;
+	} cfg;
 
 	debug ("IDE preinit using PATA peripheral at IMMR-ADDR %08x\n",
-		(u32)&immr->pata);
+		(u32)&im->pata);
 
 	/* Set the reset bit to 1 to enable the interface */
-	immr->pata.pata_ata_control = FSL_ATA_CTRL_ATA_RST_B;
+	ide_set_reset(0);
 
 	/* Init timings : we use PIO mode 0 timings */
 	t = 1000000000 / gd->ips_clk;	/* period in ns */
@@ -107,19 +106,20 @@ int ide_preinit (void)
 	cfg.bytes.field3 = (pio_specs.t1 + t) / t;
 	cfg.bytes.field4 = (pio_specs.t2_8 + t) / t;
 
-	immr->pata.pata_time1 = cfg.config;
+	out_be32(&im->pata.pata_time1, cfg.config);
 
 	cfg.bytes.field1 = (pio_specs.t2_8 + t) / t;
 	cfg.bytes.field2 = (pio_specs.tA + t) / t + 2;
 	cfg.bytes.field3 = 1;
 	cfg.bytes.field4 = (pio_specs.t4 + t) / t;
 
-	immr->pata.pata_time2 = cfg.config;
+	out_be32(&im->pata.pata_time2, cfg.config);
 
-	cfg.config = immr->pata.pata_time3;
+	cfg.config = in_be32(&im->pata.pata_time3);
 	cfg.bytes.field1 = (pio_specs.t9 + t) / t;
 
-	immr->pata.pata_time3 = cfg.config;
+	out_be32(&im->pata.pata_time3, cfg.config);
+
 	debug ("PATA preinit complete.\n");
 
 	return 0;

cpu/mpc512x/iopin.c

@@ -23,7 +23,7 @@
 
 #include <common.h>
 #include <linux/types.h>
-#include <asm/immap_512x.h>
+#include <asm/io.h>
 
 void iopin_initialize(iopin_t *ioregs_init, int len)
 {
@@ -40,9 +40,9 @@ void iopin_initialize(iopin_t *ioregs_init, int len)
 		for (p = 0, j = ioregs_init[i].p_offset / sizeof(u_long);
 			p < ioregs_init[i].nr_pins; p++, j++) {
 			if (ioregs_init[i].bit_or)
-				reg[j] |= ioregs_init[i].val;
+				setbits_be32(reg + j, ioregs_init[i].val);
 			else
-				reg[j] = ioregs_init[i].val;
+				out_be32 (reg + j, ioregs_init[i].val);
 		}
 	}
 	return;

cpu/mpc512x/pci.c

@@ -1,5 +1,6 @@
 /*
  * Copyright (C) Freescale Semiconductor, Inc. 2006, 2007. All rights reserved.
+ * Copyright (C) 2009 DENX Software Engineering <wd@denx.de>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -22,6 +23,7 @@
 
 #include <common.h>
 
+#include <asm/io.h>
 #include <asm/mmu.h>
 #include <asm/global_data.h>
 #include <pci.h>
@@ -46,7 +48,7 @@ static struct pci_controller pci_hose;
 void
 pci_init_board(void)
 {
-	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	volatile law512x_t *pci_law;
 	volatile pot512x_t *pci_pot;
 	volatile pcictrl512x_t *pci_ctrl;
@@ -58,24 +60,29 @@ pci_init_board(void)
 	struct pci_controller *hose;
 
 	/* Set PCI divider for 33MHz */
-	reg32 = immr->clk.scfr[0];
+	reg32 = im->clk.scfr[0];
 	reg32 &= ~(SCFR1_PCI_DIV_MASK);
 	reg32 |= SCFR1_PCI_DIV << SCFR1_PCI_DIV_SHIFT;
-	immr->clk.scfr[0] = reg32;
+	im->clk.scfr[0] = reg32;
 
-	pci_law = immr->sysconf.pcilaw;
-	pci_pot = immr->ios.pot;
-	pci_ctrl = &immr->pci_ctrl;
-	pci_conf = &immr->pci_conf;
+	clrsetbits_be32(&im->clk.scfr[0],
+			SCFR1_PCI_DIV_MASK,
+			SCFR1_PCI_DIV << SCFR1_PCI_DIV_SHIFT
+	);
+
+	pci_law = im->sysconf.pcilaw;
+	pci_pot = im->ios.pot;
+	pci_ctrl = &im->pci_ctrl;
+	pci_conf = &im->pci_conf;
 
 	hose = &pci_hose;
 
 	/*
 	 * Release PCI RST Output signal
 	 */
-	pci_ctrl->gcr = 0;
+	out_be32(&pci_ctrl->gcr, 0);
 	udelay(2000);
-	pci_ctrl->gcr = 1;
+	out_be32(&pci_ctrl->gcr, 1);
 
 	/* We need to wait at least a 1sec based on PCI specs */
 	for (i = 0; i < 1000; i++)
@@ -84,30 +91,39 @@ pci_init_board(void)
 	/*
 	 * Configure PCI Local Access Windows
 	 */
-	pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
-	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
+	out_be32(&pci_law[0].bar, CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR);
+	out_be32(&pci_law[0].ar, LAWAR_EN | LAWAR_SIZE_512M);
 
-	pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
-	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M;
+	out_be32(&pci_law[1].bar, CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR);
+	out_be32(&pci_law[1].ar, LAWAR_EN | LAWAR_SIZE_16M);
 
 	/*
 	 * Configure PCI Outbound Translation Windows
 	 */
 
 	/* PCI mem space - prefetch */
-	pci_pot[0].potar = (CONFIG_SYS_PCI_MEM_BASE >> 12) & POTAR_TA_MASK;
-	pci_pot[0].pobar = (CONFIG_SYS_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK;
-	pci_pot[0].pocmr = POCMR_EN | POCMR_PRE | POCMR_CM_256M;
+	out_be32(&pci_pot[0].potar,
+		(CONFIG_SYS_PCI_MEM_BASE >> 12) & POTAR_TA_MASK);
+	out_be32(&pci_pot[0].pobar,
+		(CONFIG_SYS_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK);
+	out_be32(&pci_pot[0].pocmr,
+		POCMR_EN | POCMR_PRE | POCMR_CM_256M);
 
 	/* PCI IO space */
-	pci_pot[1].potar = (CONFIG_SYS_PCI_IO_BASE >> 12) & POTAR_TA_MASK;
-	pci_pot[1].pobar = (CONFIG_SYS_PCI_IO_PHYS >> 12) & POBAR_BA_MASK;
-	pci_pot[1].pocmr = POCMR_EN | POCMR_IO | POCMR_CM_16M;
+	out_be32(&pci_pot[1].potar,
+		(CONFIG_SYS_PCI_IO_BASE >> 12) & POTAR_TA_MASK);
+	out_be32(&pci_pot[1].pobar,
+		(CONFIG_SYS_PCI_IO_PHYS >> 12) & POBAR_BA_MASK);
+	out_be32(&pci_pot[1].pocmr,
+		POCMR_EN | POCMR_IO | POCMR_CM_16M);
 
 	/* PCI mmio - non-prefetch mem space */
-	pci_pot[2].potar = (CONFIG_SYS_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK;
-	pci_pot[2].pobar = (CONFIG_SYS_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK;
-	pci_pot[2].pocmr = POCMR_EN | POCMR_CM_256M;
+	out_be32(&pci_pot[2].potar,
+		(CONFIG_SYS_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK);
+	out_be32(&pci_pot[2].pobar,
+		(CONFIG_SYS_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK);
+	out_be32(&pci_pot[2].pocmr,
+		POCMR_EN | POCMR_CM_256M);
 
 	/*
 	 * Configure PCI Inbound Translation Windows
@@ -115,11 +131,12 @@ pci_init_board(void)
 
 	/* we need RAM mapped to PCI space for the devices to
 	 * access main memory */
-	pci_ctrl[0].pitar1 = 0x0;
-	pci_ctrl[0].pibar1 = 0x0;
-	pci_ctrl[0].piebar1 = 0x0;
-	pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
-	    PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
+	out_be32(&pci_ctrl[0].pitar1, 0x0);
+	out_be32(&pci_ctrl[0].pibar1, 0x0);
+	out_be32(&pci_ctrl[0].piebar1, 0x0);
+	out_be32(&pci_ctrl[0].piwar1,
+		PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
+		PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1));
 
 	hose->first_busno = 0;
 	hose->last_busno = 0xff;

cpu/mpc512x/serial.c

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000 - 2007
+ * (C) Copyright 2000 - 2009
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -30,6 +30,8 @@
  */
 
 #include <common.h>
+#include <asm/io.h>
+#include <asm/processor.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -40,21 +42,21 @@ static void fifo_init (volatile psc512x_t *psc)
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 
 	/* reset Rx & Tx fifo slice */
-	psc->rfcmd = PSC_FIFO_RESET_SLICE;
-	psc->tfcmd = PSC_FIFO_RESET_SLICE;
+	out_be32(&psc->rfcmd, PSC_FIFO_RESET_SLICE);
+	out_be32(&psc->tfcmd, PSC_FIFO_RESET_SLICE);
 
 	/* disable Tx & Rx FIFO interrupts */
-	psc->rfintmask = 0;
-	psc->tfintmask = 0;
+	out_be32(&psc->rfintmask, 0);
+	out_be32(&psc->tfintmask, 0);
 
-	psc->tfsize = CONSOLE_FIFO_TX_SIZE | (CONSOLE_FIFO_TX_ADDR << 16);
-	psc->rfsize = CONSOLE_FIFO_RX_SIZE | (CONSOLE_FIFO_RX_ADDR << 16);
+	out_be32(&psc->tfsize, CONSOLE_FIFO_TX_SIZE | (CONSOLE_FIFO_TX_ADDR << 16));
+	out_be32(&psc->rfsize, CONSOLE_FIFO_RX_SIZE | (CONSOLE_FIFO_RX_ADDR << 16));
 
 	/* enable Tx & Rx FIFO slice */
-	psc->rfcmd = PSC_FIFO_ENABLE_SLICE;
-	psc->tfcmd = PSC_FIFO_ENABLE_SLICE;
+	out_be32(&psc->rfcmd, PSC_FIFO_ENABLE_SLICE);
+	out_be32(&psc->tfcmd, PSC_FIFO_ENABLE_SLICE);
 
-	im->fifoc.fifoc_cmd = FIFOC_DISABLE_CLOCK_GATE;
+	out_be32(&im->fifoc.fifoc_cmd, FIFOC_DISABLE_CLOCK_GATE);
 	__asm__ volatile ("sync");
 }
 
@@ -68,38 +70,38 @@ int serial_init(void)
 	fifo_init (psc);
 
 	/* set MR register to point to MR1 */
-	psc->command = PSC_SEL_MODE_REG_1;
+	out_8(&psc->command, PSC_SEL_MODE_REG_1);
 
 	/* disable Tx/Rx */
-	psc->command = PSC_TX_DISABLE | PSC_RX_DISABLE;
+	out_8(&psc->command, PSC_TX_DISABLE | PSC_RX_DISABLE);
 
 	/* choose the prescaler	by 16 for the Tx/Rx clock generation */
-	psc->psc_clock_select =  0xdd00;
+	out_be16(&psc->psc_clock_select, 0xdd00);
 
 	/* switch to UART mode */
-	psc->sicr = 0;
+	out_be32(&psc->sicr, 0);
 
 	/* mode register points to mr1 */
 	/* configure parity, bit length and so on in mode register 1*/
-	psc->mode = PSC_MODE_8_BITS | PSC_MODE_PARNONE;
+	out_8(&psc->mode, PSC_MODE_8_BITS | PSC_MODE_PARNONE);
 	/* now, mode register points to mr2 */
-	psc->mode = PSC_MODE_1_STOPBIT;
+	out_8(&psc->mode, PSC_MODE_1_STOPBIT);
 
 	/* calculate dividor for setting PSC CTUR and CTLR registers */
 	baseclk = (gd->ips_clk + 8) / 16;
 	div = (baseclk + (gd->baudrate / 2)) / gd->baudrate;
 
-	psc->ctur = (div >> 8) & 0xff;
+	out_8(&psc->ctur, (div >> 8) & 0xff);
 	/* set baudrate */
-	psc->ctlr = div & 0xff;
+	out_8(&psc->ctlr, div & 0xff);
 
 	/* disable all interrupts */
-	psc->psc_imr = 0;
+	out_be16(&psc->psc_imr, 0);
 
 	/* reset and enable Rx/Tx */
-	psc->command = PSC_RST_RX;
-	psc->command = PSC_RST_TX;
-	psc->command = PSC_RX_ENABLE | PSC_TX_ENABLE;
+	out_8(&psc->command, PSC_RST_RX);
+	out_8(&psc->command, PSC_RST_TX);
+	out_8(&psc->command, PSC_RX_ENABLE | PSC_TX_ENABLE);
 
 	return 0;
 }
@@ -113,7 +115,7 @@ void serial_putc (const char c)
 		serial_putc ('\r');
 
 	/* Wait for last character to go. */
-	while (!(psc->psc_status & PSC_SR_TXEMP))
+	while (!(in_be16(&psc->psc_status) & PSC_SR_TXEMP))
 		;
 
 	psc->tfdata_8 = c;
@@ -125,7 +127,7 @@ void serial_putc_raw (const char c)
 	volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
 
 	/* Wait for last character to go. */
-	while (!(psc->psc_status & PSC_SR_TXEMP))
+	while (!(in_be16(&psc->psc_status) & PSC_SR_TXEMP))
 		;
 
 	psc->tfdata_8 = c;
@@ -145,7 +147,7 @@ int serial_getc (void)
 	volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
 
 	/* Wait for a character to arrive. */
-	while (psc->rfstat & PSC_FIFO_EMPTY)
+	while (in_be32(&psc->rfstat) & PSC_FIFO_EMPTY)
 		;
 
 	return psc->rfdata_8;
@@ -156,7 +158,7 @@ int serial_tstc (void)
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
 
-	return !(psc->rfstat & PSC_FIFO_EMPTY);
+	return !(in_be32(&psc->rfstat) & PSC_FIFO_EMPTY);
 }
 
 void serial_setbrg (void)
@@ -168,8 +170,8 @@ void serial_setbrg (void)
 	baseclk = (gd->csb_clk + 8) / 16;
 	div = (baseclk + (gd->baudrate / 2)) / gd->baudrate;
 
-	psc->ctur = (div >> 8) & 0xFF;
-	psc->ctlr =  div & 0xff; /* set baudrate */
+	out_8(&psc->ctur, (div >> 8) & 0xFF);
+	out_8(&psc->ctlr,  div & 0xff); /* set baudrate */
 }
 
 void serial_setrts(int s)
@@ -179,11 +181,11 @@ void serial_setrts(int s)
 
 	if (s) {
 		/* Assert RTS (become LOW) */
-		psc->op1 = 0x1;
+		out_8(&psc->op1, 0x1);
 	}
 	else {
 		/* Negate RTS (become HIGH) */
-		psc->op0 = 0x1;
+		out_8(&psc->op0, 0x1);
 	}
 }
 
@@ -192,6 +194,6 @@ int serial_getcts(void)
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
 
-	return (psc->ip & 0x1) ? 0 : 1;
+	return (in_8(&psc->ip) & 0x1) ? 0 : 1;
 }
 #endif /* CONFIG_PSC_CONSOLE */

cpu/mpc512x/speed.c

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2007
+ * (C) Copyright 2000-2009
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
@@ -28,6 +28,7 @@
 #include <common.h>
 #include <mpc512x.h>
 #include <command.h>
+#include <asm/io.h>
 #include <asm/processor.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -75,29 +76,37 @@ int get_clocks (void)
 	u32 csb_clk;
 	u32 ips_clk;
 	u32 pci_clk;
+	u32 reg;
 
-	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
+	reg = in_be32(&im->sysconf.immrbar);
+	if ((reg & IMMRBAR_BASE_ADDR) != (u32) im)
 		return -1;
 
-	spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
+	reg = in_be32(&im->clk.spmr);
+	spmf = (reg & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
 	spll = ref_clk * spmf_mult[spmf];
 
-	sys_div = (im->clk.scfr[1] & SCFR2_SYS_DIV) >> SCFR2_SYS_DIV_SHIFT;
+	reg = in_be32(&im->clk.scfr[1]);
+	sys_div = (reg & SCFR2_SYS_DIV) >> SCFR2_SYS_DIV_SHIFT;
 	sys_clk = (spll * sys_dividors[sys_div][1]) / sys_dividors[sys_div][0];
 
 	csb_clk = sys_clk / 2;
 
-	cpmf = (im->clk.spmr & SPMR_CPMF) >> SPMR_CPMF_SHIFT;
+	reg = in_be32(&im->clk.spmr);
+	cpmf = (reg & SPMR_CPMF) >> SPMR_CPMF_SHIFT;
 	core_clk = (csb_clk * cpmf_mult[cpmf][0]) / cpmf_mult[cpmf][1];
 
-	ips_div = (im->clk.scfr[0] & SCFR1_IPS_DIV_MASK) >> SCFR1_IPS_DIV_SHIFT;
+	reg = in_be32(&im->clk.scfr[0]);
+	ips_div = (reg & SCFR1_IPS_DIV_MASK) >> SCFR1_IPS_DIV_SHIFT;
 	if (ips_div != 0) {
 		ips_clk = csb_clk / ips_div;
 	} else {
 		/* in case we cannot get a sane IPS divisor, fail gracefully */
 		ips_clk = 0;
 	}
-	pci_div = (im->clk.scfr[0] & SCFR1_PCI_DIV_MASK) >> SCFR1_PCI_DIV_SHIFT;
+
+	reg = in_be32(&im->clk.scfr[0]);
+	pci_div = (reg & SCFR1_PCI_DIV_MASK) >> SCFR1_PCI_DIV_SHIFT;
 	if (pci_div != 0) {
 		pci_clk = csb_clk / pci_div;
 	} else {

drivers/net/mpc512x_fec.c

@@ -12,6 +12,7 @@
 #include <net.h>
 #include <netdev.h>
 #include <miiphy.h>
+#include <asm/io.h>
 #include "mpc512x_fec.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -66,7 +67,8 @@ static int mpc512x_fec_bd_init (mpc512x_fec_priv *fec)
 	 * Receive BDs init
 	 */
 	for (ix = 0; ix < FEC_RBD_NUM; ix++) {
-		fec->bdBase->rbd[ix].dataPointer = (uint32)&fec->bdBase->recv_frames[ix];
+		fec->bdBase->rbd[ix].dataPointer =
+				(uint32)&fec->bdBase->recv_frames[ix];
 		fec->bdBase->rbd[ix].status = FEC_RBD_EMPTY;
 		fec->bdBase->rbd[ix].dataLength = 0;
 	}
@@ -119,8 +121,9 @@ static void mpc512x_fec_rbd_clean (mpc512x_fec_priv *fec, volatile FEC_RBD * pRb
 
 	/*
 	 * Now, we have an empty RxBD, notify FEC
+	 * Set Descriptor polling active
 	 */
-	fec->eth->r_des_active = 0x01000000;	/* Descriptor polling active */
+	out_be32(&fec->eth->r_des_active, 0x01000000);
 }
 
 /********************************************************************/
@@ -203,18 +206,20 @@ static void mpc512x_fec_set_hwaddr (mpc512x_fec_priv *fec, char *mac)
 	 * Set individual hash table register
 	 */
 	if (crc >= 32) {
-		fec->eth->iaddr1 = (1 << (crc - 32));
-		fec->eth->iaddr2 = 0;
+		out_be32(&fec->eth->iaddr1, (1 << (crc - 32)));
+		out_be32(&fec->eth->iaddr2, 0);
 	} else {
-		fec->eth->iaddr1 = 0;
-		fec->eth->iaddr2 = (1 << crc);
+		out_be32(&fec->eth->iaddr1, 0);
+		out_be32(&fec->eth->iaddr2, (1 << crc));
 	}
 
 	/*
 	 * Set physical address
 	 */
-	fec->eth->paddr1 = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
-	fec->eth->paddr2 = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
+	out_be32(&fec->eth->paddr1, (mac[0] << 24) + (mac[1] << 16) +
+				    (mac[2] <<  8) + mac[3]);
+	out_be32(&fec->eth->paddr2, (mac[4] << 24) + (mac[5] << 16) +
+				     0x8808);
 }
 
 /********************************************************************/
@@ -227,45 +232,45 @@ static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis)
 #endif
 
 	/* Set interrupt mask register */
-	fec->eth->imask = 0x00000000;
+	out_be32(&fec->eth->imask, 0x00000000);
 
 	/* Clear FEC-Lite interrupt event register(IEVENT) */
-	fec->eth->ievent = 0xffffffff;
+	out_be32(&fec->eth->ievent, 0xffffffff);
 
 	/* Set transmit fifo watermark register(X_WMRK), default = 64 */
-	fec->eth->x_wmrk = 0x0;
+	out_be32(&fec->eth->x_wmrk, 0x0);
 
 	/* Set Opcode/Pause Duration Register */
-	fec->eth->op_pause = 0x00010020;
+	out_be32(&fec->eth->op_pause, 0x00010020);
 
 	/* Frame length=1522; MII mode */
-	fec->eth->r_cntrl = (FEC_MAX_FRAME_LEN << 16) | 0x24;
+	out_be32(&fec->eth->r_cntrl, (FEC_MAX_FRAME_LEN << 16) | 0x24);
 
 	/* Half-duplex, heartbeat disabled */
-	fec->eth->x_cntrl = 0x00000000;
+	out_be32(&fec->eth->x_cntrl, 0x00000000);
 
 	/* Enable MIB counters */
-	fec->eth->mib_control = 0x0;
+	out_be32(&fec->eth->mib_control, 0x0);
 
 	/* Setup recv fifo start and buff size */
-	fec->eth->r_fstart = 0x500;
-	fec->eth->r_buff_size = FEC_BUFFER_SIZE;
+	out_be32(&fec->eth->r_fstart, 0x500);
+	out_be32(&fec->eth->r_buff_size, FEC_BUFFER_SIZE);
 
 	/* Setup BD base addresses */
-	fec->eth->r_des_start = (uint32)fec->bdBase->rbd;
-	fec->eth->x_des_start = (uint32)fec->bdBase->tbd;
+	out_be32(&fec->eth->r_des_start, (uint32)fec->bdBase->rbd);
+	out_be32(&fec->eth->x_des_start, (uint32)fec->bdBase->tbd);
 
 	/* DMA Control */
-	fec->eth->dma_control = 0xc0000000;
+	out_be32(&fec->eth->dma_control, 0xc0000000);
 
 	/* Enable FEC */
-	fec->eth->ecntrl |= 0x00000006;
+	setbits_be32(&fec->eth->ecntrl, 0x00000006);
 
 	/* Initilize addresses and status words of BDs */
 	mpc512x_fec_bd_init (fec);
 
 	 /* Descriptor polling active */
-	fec->eth->r_des_active = 0x01000000;
+	out_be32(&fec->eth->r_des_active, 0x01000000);
 
 #if (DEBUG & 0x1)
 	printf("mpc512x_fec_init... Done \n");
@@ -288,19 +293,20 @@ int mpc512x_fec_init_phy (struct eth_device *dev, bd_t * bis)
 	/*
 	 * Clear FEC-Lite interrupt event register(IEVENT)
 	 */
-	fec->eth->ievent = 0xffffffff;
+	out_be32(&fec->eth->ievent, 0xffffffff);
 
 	/*
 	 * Set interrupt mask register
 	 */
-	fec->eth->imask = 0x00000000;
+	out_be32(&fec->eth->imask, 0x00000000);
 
 	if (fec->xcv_type != SEVENWIRE) {
 		/*
 		 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
 		 * and do not drop the Preamble.
 		 */
-		fec->eth->mii_speed = (((gd->ips_clk / 1000000) / 5) + 1) << 1;
+		out_be32(&fec->eth->mii_speed,
+			 (((gd->ips_clk / 1000000) / 5) + 1) << 1);
 
 		/*
 		 * Reset PHY, then delay 300ns
@@ -414,27 +420,28 @@ static void mpc512x_fec_halt (struct eth_device *dev)
 	/*
 	 * mask FEC chip interrupts
 	 */
-	fec->eth->imask = 0;
+	out_be32(&fec->eth->imask, 0);
 
 	/*
 	 * issue graceful stop command to the FEC transmitter if necessary
 	 */
-	fec->eth->x_cntrl |= 0x00000001;
+	setbits_be32(&fec->eth->x_cntrl, 0x00000001);
 
 	/*
 	 * wait for graceful stop to register
 	 */
-	while ((counter--) && (!(fec->eth->ievent & 0x10000000))) ;
+	while ((counter--) && (!(in_be32(&fec->eth->ievent) & 0x10000000)))
+		;
 
 	/*
 	 * Disable the Ethernet Controller
 	 */
-	fec->eth->ecntrl &= 0xfffffffd;
+	clrbits_be32(&fec->eth->ecntrl, 0x00000002);
 
 	/*
 	 * Issue a reset command to the FEC chip
 	 */
-	fec->eth->ecntrl |= 0x1;
+	setbits_be32(&fec->eth->ecntrl, 0x1);
 
 	/*
 	 * wait at least 16 clock cycles
@@ -493,7 +500,7 @@ static int mpc512x_fec_send (struct eth_device *dev, volatile void *eth_data,
 	fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
 
 	/* Activate transmit Buffer Descriptor polling */
-	fec->eth->x_des_active = 0x01000000;	/* Descriptor polling active	*/
+	out_be32(&fec->eth->x_des_active, 0x01000000);
 
 #if (DEBUG & 0x8)
 	printf ( "+" );
@@ -536,8 +543,8 @@ static int mpc512x_fec_recv (struct eth_device *dev)
 	/*
 	 * Check if any critical events have happened
 	 */
-	ievent = fec->eth->ievent;
-	fec->eth->ievent = ievent;
+	ievent = in_be32(&fec->eth->ievent);
+	out_be32(&fec->eth->ievent, ievent);
 	if (ievent & 0x20060000) {
 		/* BABT, Rx/Tx FIFO errors */
 		mpc512x_fec_halt (dev);
@@ -546,13 +553,13 @@ static int mpc512x_fec_recv (struct eth_device *dev)
 	}
 	if (ievent & 0x80000000) {
 		/* Heartbeat error */
-		fec->eth->x_cntrl |= 0x00000001;
+		setbits_be32(&fec->eth->x_cntrl, 0x00000001);
 	}
 	if (ievent & 0x10000000) {
 		/* Graceful stop complete */
-		if (fec->eth->x_cntrl & 0x00000001) {
+		if (in_be32(&fec->eth->x_cntrl) & 0x00000001) {
 			mpc512x_fec_halt (dev);
-			fec->eth->x_cntrl &= ~0x00000001;
+			clrbits_be32(&fec->eth->x_cntrl, 0x00000001);;
 			mpc512x_fec_init (dev, NULL);
 		}
 	}
@@ -598,7 +605,8 @@ static int mpc512x_fec_recv (struct eth_device *dev)
 	}
 
 	/* Try to fill Buffer Descriptors */
-	fec->eth->r_des_active = 0x01000000;	/* Descriptor polling active */
+	out_be32(&fec->eth->r_des_active, 0x01000000);
+
 	return frame_length;
 }
 
@@ -651,12 +659,12 @@ int mpc512x_fec_initialize (bd_t * bis)
 	/*
 	 * Set interrupt mask register
 	 */
-	fec->eth->imask = 0x00000000;
+	out_be32(&fec->eth->imask, 0x00000000);
 
 	/*
 	 * Clear FEC-Lite interrupt event register(IEVENT)
 	 */
-	fec->eth->ievent = 0xffffffff;
+	out_be32(&fec->eth->ievent, 0xffffffff);
 
 	/*
 	 * Try to set the mac address now. The fec mac address is
@@ -671,8 +679,8 @@ int mpc512x_fec_initialize (bd_t * bis)
 				tmp = (*end) ? end+1 : end;
 		}
 		mpc512x_fec_set_hwaddr (fec, env_enetaddr);
-		fec->eth->gaddr1 = 0x00000000;
-		fec->eth->gaddr2 = 0x00000000;
+		out_be32(&fec->eth->gaddr1, 0x00000000);
+		out_be32(&fec->eth->gaddr2, 0x00000000);
 	}
 
 	mpc512x_fec_init_phy (dev, bis);
@@ -696,12 +704,16 @@ int fec512x_miiphy_read (char *devname, uint8 phyAddr, uint8 regAddr, uint16 * r
 	reg = regAddr << FEC_MII_DATA_RA_SHIFT;
 	phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
 
-	eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy | reg);
+	out_be32(&eth->mii_data, FEC_MII_DATA_ST |
+				 FEC_MII_DATA_OP_RD |
+				 FEC_MII_DATA_TA |
+				 phy | reg);
 
 	/*
 	 * wait for the related interrupt
 	 */
-	while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
+	while ((timeout--) && (!(in_be32(&eth->ievent) & 0x00800000)))
+		;
 
 	if (timeout == 0) {
 #if (DEBUG & 0x2)
@@ -713,12 +725,12 @@ int fec512x_miiphy_read (char *devname, uint8 phyAddr, uint8 regAddr, uint16 * r
 	/*
 	 * clear mii interrupt bit
 	 */
-	eth->ievent = 0x00800000;
+	out_be32(&eth->ievent, 0x00800000);
 
 	/*
 	 * it's now safe to read the PHY's register
 	 */
-	*retVal = (uint16) eth->mii_data;
+	*retVal = (uint16) in_be32(&eth->mii_data);
 
 	return 0;
 }
@@ -734,13 +746,16 @@ int fec512x_miiphy_write (char *devname, uint8 phyAddr, uint8 regAddr, uint16 da
 	reg = regAddr << FEC_MII_DATA_RA_SHIFT;
 	phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
 
-	eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
-			FEC_MII_DATA_TA | phy | reg | data);
+	out_be32(&eth->mii_data, FEC_MII_DATA_ST |
+				 FEC_MII_DATA_OP_WR |
+				 FEC_MII_DATA_TA |
+				 phy | reg | data);
 
 	/*
 	 * wait for the MII interrupt
 	 */
-	while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
+	while ((timeout--) && (!(in_be32(&eth->ievent) & 0x00800000)))
+		;
 
 	if (timeout == 0) {
 #if (DEBUG & 0x2)
@@ -752,7 +767,7 @@ int fec512x_miiphy_write (char *devname, uint8 phyAddr, uint8 regAddr, uint16 da
 	/*
 	 * clear MII interrupt bit
 	 */
-	eth->ievent = 0x00800000;
+	out_be32(&eth->ievent, 0x00800000);
 
 	return 0;
 }