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@@ -30,6 +30,8 @@
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#include <asm/arch/at91_rstc.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/io.h>
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+#include <lcd.h>
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+#include <atmel_lcdc.h>
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#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
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#include <net.h>
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#endif
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@@ -150,6 +152,65 @@ static void at91sam9261ek_dm9000_hw_init(void)
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}
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#endif
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+#ifdef CONFIG_LCD
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+vidinfo_t panel_info = {
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+ vl_col: 240,
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+ vl_row: 320,
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+ vl_clk: 4965000,
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+ vl_sync: ATMEL_LCDC_INVLINE_INVERTED |
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+ ATMEL_LCDC_INVFRAME_INVERTED,
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+ vl_bpix: 3,
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+ vl_tft: 1,
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+ vl_hsync_len: 5,
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+ vl_left_margin: 1,
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+ vl_right_margin:33,
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+ vl_vsync_len: 1,
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+ vl_upper_margin:1,
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+ vl_lower_margin:0,
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+ mmio: AT91SAM9261_LCDC_BASE,
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+};
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+
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+void lcd_enable(void)
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+{
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+ at91_set_gpio_value(AT91_PIN_PA12, 0); /* power up */
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+}
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+
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+void lcd_disable(void)
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+{
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+ at91_set_gpio_value(AT91_PIN_PA12, 1); /* power down */
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+}
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+
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+static void at91sam9261ek_lcd_hw_init(void)
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+{
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+ at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */
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+ at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */
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+ at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */
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+ at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */
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+ at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */
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+ at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */
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+ at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */
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+ at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */
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+ at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */
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+ at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */
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+ at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */
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+ at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */
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+ at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */
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+ at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */
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+ at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */
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+ at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */
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+ at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */
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+ at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */
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+ at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */
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+ at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */
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+ at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */
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+ at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */
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+
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+ at91_sys_write(AT91_PMC_SCER, AT91_PMC_HCK1);
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+
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+ gd->fb_base = AT91SAM9261_SRAM_BASE;
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+}
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+#endif
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+
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int board_init(void)
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{
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/* Enable Ctrlc */
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@@ -169,6 +230,9 @@ int board_init(void)
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#endif
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#ifdef CONFIG_DRIVER_DM9000
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at91sam9261ek_dm9000_hw_init();
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+#endif
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+#ifdef CONFIG_LCD
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+ at91sam9261ek_lcd_hw_init();
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#endif
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return 0;
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}
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