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-/*
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- * Memory Setup stuff - taken from blob memsetup.S
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- *
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- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
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- * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
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- *
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- * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
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- * Copyright (C) 2009 Jean-Christopher PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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- *
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- * See file CREDITS for list of people who contributed to this
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- * project.
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- *
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- * This program is free software; you can redistribute it and/or
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- * modify it under the terms of the GNU General Public License as
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- * published by the Free Software Foundation; either version 2 of
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- * the License, or (at your option) any later version.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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- * GNU General Public License for more details.
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- *
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- * You should have received a copy of the GNU General Public License
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- * along with this program; if not, write to the Free Software
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- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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- * MA 02111-1307 USA
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- */
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-
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-#include <config.h>
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-#include <version.h>
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-#include <asm/arch/hardware.h>
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-#include <asm/arch/at91_pmc.h>
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-#include <asm/arch/at91_pio.h>
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-#include <asm/arch/at91_rstc.h>
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-#include <asm/arch/at91_wdt.h>
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-#include <asm/arch/at91sam9_sdramc.h>
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-#include <asm/arch/at91sam9_smc.h>
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-#include <asm/arch/at91sam9263_matrix.h>
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-
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-_TEXT_BASE:
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- .word TEXT_BASE
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-
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-.globl lowlevel_init
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-.type lowlevel_init,function
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-lowlevel_init:
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-
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- mov r5, pc /* r5 = POS1 + 4 current */
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-POS1:
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- ldr r0, =POS1 /* r0 = POS1 compile */
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- ldr r2, _TEXT_BASE
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- sub r0, r0, r2 /* r0 = POS1-_TEXT_BASE (POS1 relative) */
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- sub r5, r5, r0 /* r0 = TEXT_BASE-1 */
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- sub r5, r5, #4 /* r1 = text base - current */
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-
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- /* memory control configuration 1 */
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- ldr r0, =SMRDATA
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- ldr r2, =SMRDATA1
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- ldr r1, _TEXT_BASE
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- sub r0, r0, r1
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- sub r2, r2, r1
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- add r0, r0, r5
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- add r2, r2, r5
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-0:
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- /* the address */
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- ldr r1, [r0], #4
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- /* the value */
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- ldr r3, [r0], #4
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- str r3, [r1]
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- cmp r2, r0
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- bne 0b
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-
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-/* ----------------------------------------------------------------------------
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- * PMC Init Step 1.
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- * ----------------------------------------------------------------------------
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- * - Check if the PLL is already initialized
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- * ----------------------------------------------------------------------------
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- */
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- ldr r1, =(AT91_BASE_SYS + AT91_PMC_MCKR)
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- ldr r0, [r1]
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- and r0, r0, #3
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- cmp r0, #0
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- bne PLL_setup_end
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-
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-/* ---------------------------------------------------------------------------
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- * - Enable the Main Oscillator
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- * ---------------------------------------------------------------------------
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- */
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- ldr r1, =(AT91_BASE_SYS + AT91_CKGR_MOR)
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- ldr r2, =(AT91_BASE_SYS + AT91_PMC_SR)
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- ldr r0, =CONFIG_SYS_MOR_VAL
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- str r0, [r1] /* Enable main oscillator, OSCOUNT = 0xFF */
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-
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- /* Reading the PMC Status to detect when the Main Oscillator is enabled */
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- mov r4, #AT91_PMC_MOSCS
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-MOSCS_Loop:
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- ldr r3, [r2]
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- and r3, r4, r3
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- cmp r3, #AT91_PMC_MOSCS
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- bne MOSCS_Loop
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-
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-/* ----------------------------------------------------------------------------
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- * PMC Init Step 2.
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- * ----------------------------------------------------------------------------
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- * Setup PLLA
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- * ----------------------------------------------------------------------------
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- */
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- ldr r1, =(AT91_BASE_SYS + AT91_CKGR_PLLAR)
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- ldr r0, =CONFIG_SYS_PLLAR_VAL
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- str r0, [r1]
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-
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- /* Reading the PMC Status register to detect when the PLLA is locked */
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- mov r4, #AT91_PMC_LOCKA
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-MOSCS_Loop1:
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- ldr r3, [r2]
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- and r3, r4, r3
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- cmp r3, #AT91_PMC_LOCKA
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- bne MOSCS_Loop1
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-
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-/* ----------------------------------------------------------------------------
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- * PMC Init Step 3.
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- * ----------------------------------------------------------------------------
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- * - Switch on the Main Oscillator 16.367 MHz
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- * ----------------------------------------------------------------------------
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- */
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- ldr r1, =(AT91_BASE_SYS + AT91_PMC_MCKR)
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-
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- /* -Master Clock Controller register PMC_MCKR */
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- ldr r0, =CONFIG_SYS_MCKR1_VAL
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- str r0, [r1]
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-
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- /* Reading the PMC Status to detect when the Master clock is ready */
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- mov r4, #AT91_PMC_MCKRDY
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-MCKRDY_Loop:
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- ldr r3, [r2]
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- and r3, r4, r3
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- cmp r3, #AT91_PMC_MCKRDY
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- bne MCKRDY_Loop
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-
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- ldr r0, =CONFIG_SYS_MCKR2_VAL
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- str r0, [r1]
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-
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- /* Reading the PMC Status to detect when the Master clock is ready */
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- mov r4, #AT91_PMC_MCKRDY
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-MCKRDY_Loop1:
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- ldr r3, [r2]
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- and r3, r4, r3
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- cmp r3, #AT91_PMC_MCKRDY
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- bne MCKRDY_Loop1
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-
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-PLL_setup_end:
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-
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-/* ----------------------------------------------------------------------------
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- * - memory control configuration 2
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- * ----------------------------------------------------------------------------
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- */
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- ldr r0, =(AT91_BASE_SYS + AT91_SDRAMC_TR)
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- ldr r1, [r0]
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- cmp r1, #0
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- bne SDRAM_setup_end
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-
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- ldr r0, =SMRDATA1
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- ldr r2, =SMRDATA2
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- ldr r1, _TEXT_BASE
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- sub r0, r0, r1
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- sub r2, r2, r1
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- add r0, r0, r5
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- add r2, r2, r5
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-
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-2:
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- /* the address */
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- ldr r1, [r0], #4
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- /* the value */
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- ldr r3, [r0], #4
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- str r3, [r1]
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- cmp r2, r0
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- bne 2b
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-
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-SDRAM_setup_end:
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- /* everything is fine now */
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- mov pc, lr
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-
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- .ltorg
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-
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-SMRDATA:
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- .word (AT91_BASE_SYS + AT91_WDT_MR)
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- .word CONFIG_SYS_WDTC_WDMR_VAL
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-
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- .word (AT91_BASE_SYS + AT91_PIOD + PIO_PDR)
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- .word CONFIG_SYS_PIOD_PDR_VAL1
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- .word (AT91_BASE_SYS + AT91_PIOD + PIO_PUDR)
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- .word CONFIG_SYS_PIOD_PPUDR_VAL
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- .word (AT91_BASE_SYS + AT91_PIOD + PIO_ASR)
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- .word CONFIG_SYS_PIOD_PPUDR_VAL
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-
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- .word (AT91_BASE_SYS + AT91_MATRIX_EBI0CSA)
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- .word CONFIG_SYS_MATRIX_EBI0CSA_VAL
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-
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- /* flash */
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- .word (AT91_BASE_SYS + AT91_SMC_MODE(0))
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- .word CONFIG_SYS_SMC0_MODE0_VAL
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-
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- .word (AT91_BASE_SYS + AT91_SMC_CYCLE(0))
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- .word CONFIG_SYS_SMC0_CYCLE0_VAL
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-
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- .word (AT91_BASE_SYS + AT91_SMC_PULSE(0))
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- .word CONFIG_SYS_SMC0_PULSE0_VAL
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-
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- .word (AT91_BASE_SYS + AT91_SMC_SETUP(0))
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- .word CONFIG_SYS_SMC0_SETUP0_VAL
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-
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-SMRDATA1:
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- .word (AT91_BASE_SYS + AT91_SDRAMC_MR)
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- .word CONFIG_SYS_SDRC_MR_VAL1
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- .word (AT91_BASE_SYS + AT91_SDRAMC_TR)
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- .word CONFIG_SYS_SDRC_TR_VAL1
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- .word (AT91_BASE_SYS + AT91_SDRAMC_CR)
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- .word CONFIG_SYS_SDRC_CR_VAL
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- .word (AT91_BASE_SYS + AT91_SDRAMC_MDR)
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- .word CONFIG_SYS_SDRC_MDR_VAL
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- .word (AT91_BASE_SYS + AT91_SDRAMC_MR)
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- .word CONFIG_SYS_SDRC_MR_VAL2
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- .word AT91_SDRAM_BASE
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- .word CONFIG_SYS_SDRAM_VAL1
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- .word (AT91_BASE_SYS + AT91_SDRAMC_MR)
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- .word CONFIG_SYS_SDRC_MR_VAL3
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- .word AT91_SDRAM_BASE
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- .word CONFIG_SYS_SDRAM_VAL2
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- .word AT91_SDRAM_BASE
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- .word CONFIG_SYS_SDRAM_VAL3
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- .word AT91_SDRAM_BASE
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- .word CONFIG_SYS_SDRAM_VAL4
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- .word AT91_SDRAM_BASE
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- .word CONFIG_SYS_SDRAM_VAL5
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- .word AT91_SDRAM_BASE
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- .word CONFIG_SYS_SDRAM_VAL6
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- .word AT91_SDRAM_BASE
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- .word CONFIG_SYS_SDRAM_VAL7
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- .word AT91_SDRAM_BASE
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- .word CONFIG_SYS_SDRAM_VAL8
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- .word AT91_SDRAM_BASE
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- .word CONFIG_SYS_SDRAM_VAL9
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- .word (AT91_BASE_SYS + AT91_SDRAMC_MR)
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- .word CONFIG_SYS_SDRC_MR_VAL4
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- .word AT91_SDRAM_BASE
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- .word CONFIG_SYS_SDRAM_VAL10
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- .word (AT91_BASE_SYS + AT91_SDRAMC_MR)
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- .word CONFIG_SYS_SDRC_MR_VAL5
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- .word AT91_SDRAM_BASE
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- .word CONFIG_SYS_SDRAM_VAL11
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- .word (AT91_BASE_SYS + AT91_SDRAMC_TR)
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- .word CONFIG_SYS_SDRC_TR_VAL2
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- .word AT91_SDRAM_BASE
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- .word CONFIG_SYS_SDRAM_VAL12
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- /* User reset enable*/
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- .word (AT91_BASE_SYS + AT91_RSTC_MR)
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- .word CONFIG_SYS_RSTC_RMR_VAL
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-#ifdef CONFIG_SYS_MATRIX_MCFG_REMAP
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- /* MATRIX_MCFG - REMAP all masters */
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- .word (AT91_BASE_SYS + AT91_MATRIX_MCFG0)
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- .word 0x1FF
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-#endif
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-
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-SMRDATA2:
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- .word 0
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Jean-Christophe PLAGNIOL-VILLARD