vf610twr: Enable all masks of CCGRx registers.

This allows MQX applications to run when started from u-boot.

Signed-off-by: Anthony Felice <tony.felice@timesys.com>

arch/arm/include/asm/arch-vf610/crm_regs.h

@@ -180,25 +180,44 @@ struct anadig_reg {
 
 #define CCM_CLPCR_SBYOS_MASK            (0x1 << 6)
 
-#define CCM_REG_CTRL_MASK			0xffffffff
+#define CCM_REG_CTRL_MASK			(0xffffffff)
+#define CCM_CCGRX_ENABLE_ALL_CTRL_MASK		(0xffffffff)
+#define CCM_CCGR0_FLEXCAN0_CTRL_MASK		(0x3 << 0)
+#define CCM_CCGR0_DMA0_CTRL_MASK		(0x3 << 8)
+#define CCM_CCGR0_DMA1_CTRL_MASK		(0x3 << 10)
+#define CCM_CCGR0_UART0_CTRL_MASK		(0x3 << 14)
 #define CCM_CCGR0_UART1_CTRL_MASK		(0x3 << 16)
-#define CCM_CCGR1_USBC0_CTRL_MASK       (0x3 << 8)
+#define CCM_CCGR0_UART2_CTRL_MASK		(0x3 << 18)
+#define CCM_CCGR0_UART3_CTRL_MASK		(0x3 << 20)
+#define CCM_CCGR0_SPI0_CTRL_MASK		(0x3 << 24)
+#define CCM_CCGR0_SPI1_CTRL_MASK		(0x3 << 26)
+#define CCM_CCGR0_SAI0_CTRL_MASK		(0x3 << 30)
+#define CCM_CCGR1_SAI1_CTRL_MASK		(0x3 << 0)
+#define CCM_CCGR1_SAI2_CTRL_MASK		(0x3 << 2)
+#define CCM_CCGR1_SAI3_CTRL_MASK		(0x3 << 4)
+#define CCM_CCGR1_USBC0_CTRL_MASK       	(0x3 << 8)
 #define CCM_CCGR1_PIT_CTRL_MASK			(0x3 << 14)
+#define CCM_CCGR1_FTM0_CTRL_MASK		(0x3 << 16)
+#define CCM_CCGR1_FTM1_CTRL_MASK		(0x3 << 18)
+#define CCM_CCGR1_ADC0_CTRL_MASK		(0x3 << 22)
 #define CCM_CCGR1_WDOGA5_CTRL_MASK		(0x3 << 28)
+#define CCM_CCGR1_WDOGM4_CTRL_MASK		(0x3 << 30)
+#define CCM_CCGR2_QSPI0_CTRL_MASK		(0x3 << 8)
 #define CCM_CCGR2_IOMUXC_CTRL_MASK		(0x3 << 16)
 #define CCM_CCGR2_PORTA_CTRL_MASK		(0x3 << 18)
 #define CCM_CCGR2_PORTB_CTRL_MASK		(0x3 << 20)
 #define CCM_CCGR2_PORTC_CTRL_MASK		(0x3 << 22)
 #define CCM_CCGR2_PORTD_CTRL_MASK		(0x3 << 24)
 #define CCM_CCGR2_PORTE_CTRL_MASK		(0x3 << 26)
-#define CCM_CCGR3_ANADIG_CTRL_MASK		0x3
+#define CCM_CCGR3_ANADIG_CTRL_MASK		(0x3)
+#define CCM_CCGR3_DCU0_CTRL_MASK		(0x3 << 16)
 #define CCM_CCGR4_WKUP_CTRL_MASK		(0x3 << 20)
 #define CCM_CCGR4_CCM_CTRL_MASK			(0x3 << 22)
 #define CCM_CCGR4_GPC_CTRL_MASK			(0x3 << 24)
 #define CCM_CCGR6_OCOTP_CTRL_MASK		(0x3 << 10)
 #define CCM_CCGR6_DDRMC_CTRL_MASK		(0x3 << 28)
 #define CCM_CCGR7_SDHC1_CTRL_MASK		(0x3 << 4)
-#define CCM_CCGR9_FEC0_CTRL_MASK		0x3
+#define CCM_CCGR9_FEC0_CTRL_MASK		(0x3)
 #define CCM_CCGR9_FEC1_CTRL_MASK		(0x3 << 2)
 
 #define ANADIG_PLL3_CTRL_POWERDOWN		(1 << 12)

board/freescale/vf610twr/vf610twr.c

@@ -325,24 +325,25 @@ static void clock_init(void)
 	struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
 
 	clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
-		CCM_CCGR0_UART1_CTRL_MASK);
+		CCM_CCGRX_ENABLE_ALL_CTRL_MASK);
 	clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
-		CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
+		CCM_CCGRX_ENABLE_ALL_CTRL_MASK);
 	clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
-		CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
-		CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
-		CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK);
+		CCM_CCGRX_ENABLE_ALL_CTRL_MASK);
 	clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
-		CCM_CCGR3_ANADIG_CTRL_MASK);
+		CCM_CCGRX_ENABLE_ALL_CTRL_MASK);
 	clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
-		CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
-		CCM_CCGR4_GPC_CTRL_MASK);
+		CCM_CCGRX_ENABLE_ALL_CTRL_MASK);
 	clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
-		CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
+		CCM_CCGRX_ENABLE_ALL_CTRL_MASK);
 	clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
-		CCM_CCGR7_SDHC1_CTRL_MASK);
+		CCM_CCGRX_ENABLE_ALL_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr8, CCM_REG_CTRL_MASK,
+                CCM_CCGRX_ENABLE_ALL_CTRL_MASK);
 	clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
-		CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
+		CCM_CCGRX_ENABLE_ALL_CTRL_MASK);
+        clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
+                CCM_CCGRX_ENABLE_ALL_CTRL_MASK);
 
 	clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN,
 		ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);