mpc52xx: remove o2dnt board

Remove old o2dnt board without OF support. New support for this board
is added by the previous patch, O2I configuration.

Signed-off-by: Anatolij Gustschin <agust@denx.de>

board/o2dnt/Makefile

@@ -1,45 +0,0 @@
-
-#
-# (C) Copyright 2005-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################

board/o2dnt/flash.c

@@ -1,587 +0,0 @@
-/*
- * (C) Copyright 2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * flash_real_protect() routine based on boards/alaska/flash.c
- * (C) Copyright 2001
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-/* Intel-compatible flash commands */
-#define INTEL_ERASE	0x20
-#define INTEL_PROGRAM	0x40
-#define INTEL_CLEAR	0x50
-#define INTEL_LOCKBIT	0x60
-#define INTEL_PROTECT	0x01
-#define INTEL_STATUS	0x70
-#define INTEL_READID	0x90
-#define INTEL_READID	0x90
-#define INTEL_SUSPEND	0xB0
-#define INTEL_CONFIRM	0xD0
-#define INTEL_RESET	0xFF
-
-/* Intel-compatible flash status bits */
-#define INTEL_FINISHED	0x80
-#define INTEL_OK	0x80
-
-typedef unsigned char FLASH_PORT_WIDTH;
-typedef volatile unsigned char FLASH_PORT_WIDTHV;
-#define FPW		FLASH_PORT_WIDTH
-#define FPWV		FLASH_PORT_WIDTHV
-#define	FLASH_ID_MASK	0xFF
-
-#define ORMASK(size) ((-size) & OR_AM_MSK)
-
-#define FLASH_CYCLE1	0x0555
-#define FLASH_CYCLE2	0x02aa
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size(FPWV *addr, flash_info_t *info);
-static void flash_reset(flash_info_t *info);
-static flash_info_t *flash_get_info(ulong base);
-static int write_data (flash_info_t *info, FPWV *dest, FPW data); /* O2D */
-static void flash_sync_real_protect (flash_info_t * info);
-static unsigned char intel_sector_protected (flash_info_t *info, ushort sector);
-
-/*-----------------------------------------------------------------------
- * flash_init()
- *
- * sets up flash_info and returns size of FLASH (bytes)
- */
-unsigned long flash_init (void)
-{
-	unsigned long size = 0;
-	int i;
-	extern void flash_preinit(void);
-	extern void flash_afterinit(ulong);
-
-	flash_preinit();
-
-	/* Init: no FLASHes known */
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-		memset(&flash_info[i], 0, sizeof(flash_info_t));
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-	}
-
-	/* Query flash chip */
-	flash_info[0].size =
-		flash_get_size((FPW *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-	size += flash_info[0].size;
-
-	/* get the h/w and s/w protection status in sync */
-	flash_sync_real_protect(&flash_info[0]);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-	/* monitor protection ON by default */
-	flash_protect(FLAG_PROTECT_SET,
-			CONFIG_SYS_MONITOR_BASE,
-			CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
-			flash_get_info(CONFIG_SYS_MONITOR_BASE));
-#endif
-
-#ifdef	CONFIG_ENV_IS_IN_FLASH
-	/* ENV protection ON by default */
-	flash_protect(FLAG_PROTECT_SET,
-			CONFIG_ENV_ADDR,
-			CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
-			flash_get_info(CONFIG_ENV_ADDR));
-#endif
-
-
-	flash_afterinit(size);
-	return (size ? size : 1);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_reset(flash_info_t *info)
-{
-	FPWV *base = (FPWV *)(info->start[0]);
-
-	/* Put FLASH back in read mode */
-	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
-		*base = (FPW) INTEL_RESET;	/* Intel Read Mode */
-}
-
-/*-----------------------------------------------------------------------
- */
-
-static flash_info_t *flash_get_info(ulong base)
-{
-	int i;
-	flash_info_t * info;
-
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) {
-		info = & flash_info[i];
-		if (info->size &&
-				info->start[0] <= base &&
-				base <= info->start[0] + info->size - 1)
-			break;
-	}
-
-	return (i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info);
-}
-
-/*-----------------------------------------------------------------------
- */
-
-void flash_print_info (flash_info_t *info)
-{
-	int i;
-	uchar *boottype;
-	uchar *bootletter;
-	char *fmt;
-	uchar botbootletter[] = "B";
-	uchar topbootletter[] = "T";
-	uchar botboottype[] = "bottom boot sector";
-	uchar topboottype[] = "top boot sector";
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-		case FLASH_MAN_INTEL:
-			printf ("INTEL ");
-			break;
-		default:
-			printf ("Unknown Vendor ");
-			break;
-	}
-
-	/* check for top or bottom boot, if it applies */
-	if (info->flash_id & FLASH_BTYPE) {
-		boottype = botboottype;
-		bootletter = botbootletter;
-	} else {
-		boottype = topboottype;
-		bootletter = topbootletter;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-		case FLASH_28F128J3A:
-			fmt = "28F128J3 (128 Mbit, uniform sectors)\n";
-			break;
-		default:
-			fmt = "Unknown Chip Type\n";
-			break;
-	}
-
-	printf (fmt, bootletter, boottype);
-	printf ("  Size: %ld MB in %d Sectors\n",
-			info->size >> 20,
-			info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-	for (i=0; i<info->sector_count; ++i) {
-		if ((i % 5) == 0)
-			printf ("\n   ");
-
-		printf (" %08lX%s", info->start[i],
-				info->protect[i] ? " (RO)" : "     ");
-	}
-	printf ("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-ulong flash_get_size (FPWV *addr, flash_info_t *info)
-{
-	int i;
-
-	/* Write auto select command: read Manufacturer ID */
-	/* Write auto select command sequence and test FLASH answer */
-	addr[FLASH_CYCLE1] = (FPW) INTEL_READID;	/* selects Intel or AMD */
-
-	/* The manufacturer codes are only 1 byte, so just use 1 byte.
-	 * This works for any bus width and any FLASH device width.
-	 */
-	udelay(100);
-	switch (addr[0] & 0xff) {
-		case (uchar)INTEL_MANUFACT:
-			info->flash_id = FLASH_MAN_INTEL;
-			break;
-		default:
-			info->flash_id = FLASH_UNKNOWN;
-			info->sector_count = 0;
-			info->size = 0;
-			break;
-	}
-
-	/* Strataflash is configurable to 8/16bit Bus,
-	 * but the Query-Structure is Word-orientated */
-	if (info->flash_id != FLASH_UNKNOWN) {
-		switch ((FPW)addr[2]) {
-			case (FPW)INTEL_ID_28F128J3:
-				info->flash_id += FLASH_28F128J3A;
-				info->sector_count = 128;
-				info->size = 0x01000000;
-				for( i = 0; i < info->sector_count; i++ )
-					info->start[i] = (ulong)addr + (i * 0x20000);
-				break;				/* => Intel Strataflash 16MB */
-			default:
-				printf("Flash_id != %xd\n", (FPW)addr[2]);
-				info->flash_id = FLASH_UNKNOWN;
-				info->sector_count = 0;
-				info->size = 0;
-				return (0);			/* => no or unknown flash */
-		}
-	}
-
-	/* Put FLASH back in read mode */
-	flash_reset(info);
-
-	return (info->size);
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
-	FPWV *addr;
-	int flag, prot, sect;
-	ulong start, now, last;
-	int rcode = 0;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("- missing\n");
-		} else {
-			printf ("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-		case FLASH_28F128J3A:
-			break;
-		case FLASH_UNKNOWN:
-		default:
-			printf ("Can't erase unknown flash type %08lx - aborted\n",
-					info->flash_id);
-			return 1;
-	}
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; ++sect)
-		if (info->protect[sect])
-			prot++;
-
-	if (prot)
-		printf ("- Warning: %d protected sectors will not be erased!",
-				prot);
-
-	printf ("\n");
-	last = get_timer(0);
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect <= s_last && rcode == 0; sect++) {
-
-		if (info->protect[sect] != 0)	/* protected, skip it */
-			continue;
-
-		/* Disable interrupts which might cause a timeout here */
-		flag = disable_interrupts();
-
-		addr = (FPWV *)(info->start[sect]);
-		*addr = (FPW) INTEL_CLEAR; /* clear status register */
-		*addr = (FPW) INTEL_ERASE; /* erase setup */
-		*addr = (FPW) INTEL_CONFIRM; /* erase confirm */
-
-		/* re-enable interrupts if necessary */
-		if (flag)
-			enable_interrupts();
-
-		start = get_timer(0);
-
-		/* wait at least 80us for Intel - let's wait 1 ms */
-		udelay (1000);
-
-		while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
-			if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-				printf ("Timeout\n");
-				*addr = (FPW) INTEL_SUSPEND;/* suspend erase */
-				flash_reset(info);	/* reset to read mode */
-				rcode = 1;		/* failed */
-				break;
-			}
-
-			/* show that we're waiting */
-			if ((get_timer(last)) > CONFIG_SYS_HZ) { /* every second */
-				putc ('.');
-				last = get_timer(0);
-			}
-		}
-
-		flash_reset(info);	/* reset to read mode */
-	}
-
-	printf (" done\n");
-	return rcode;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-	FPW data = 0;	/* 16 or 32 bit word, matches flash bus width on MPC8XX */
-	int bytes;	/* number of bytes to program in current word		*/
-	int left;	/* number of bytes left to program			*/
-	int i, res;
-
-	for (left = cnt, res = 0;
-			left > 0 && res == 0;
-			addr += sizeof(data), left -= sizeof(data) - bytes) {
-
-		bytes = addr & (sizeof(data) - 1);
-		addr &= ~(sizeof(data) - 1);
-
-		/* combine source and destination data so can program
-		 * an entire word of 16 or 32 bits  */
-		for (i = 0; i < sizeof(data); i++) {
-			data <<= 8;
-			if (i < bytes || i - bytes >= left )
-				data += *((uchar *)addr + i);
-			else
-				data += *src++;
-		}
-
-		/* write one word to the flash */
-		switch (info->flash_id & FLASH_VENDMASK) {
-			case FLASH_MAN_INTEL:
-				res = write_data(info, (FPWV *)addr, data);
-				break;
-			default:
-				/* unknown flash type, error! */
-				printf ("missing or unknown FLASH type\n");
-				res = 1;	/* not really a timeout, but gives error */
-				break;
-		}
-	}
-
-	return (res);
-}
-
-/*-----------------------------------------------------------------------
- * Write a word or halfword to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_data (flash_info_t *info, FPWV *dest, FPW data)
-{
-	FPWV *addr = dest;
-	ulong status;
-	ulong start;
-	int flag;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*addr & data) != data) {
-		printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
-		return (2);
-	}
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts ();
-
-	*addr = (FPW) INTEL_PROGRAM;	/* write setup */
-	*addr = data;
-
-	/* arm simple, non interrupt dependent timer */
-	start = get_timer(0);
-
-	/* wait while polling the status register */
-	while (((status = *addr) & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
-		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-			*addr = (FPW) INTEL_RESET;	/* restore read mode */
-			return (1);
-		}
-	}
-
-	*addr = (FPW) INTEL_RESET;	/* restore read mode */
-	if (flag)
-		enable_interrupts();
-
-	return (0);
-}
-
-
-/*-----------------------------------------------------------------------
- * Set/Clear sector's lock bit, returns:
- * 0 - OK
- * 1 - Error (timeout, voltage problems, etc.)
- */
-int flash_real_protect (flash_info_t * info, long sector, int prot)
-{
-	ulong start;
-	int i;
-	int rc = 0;
-	FPWV *addr = (FPWV *) (info->start[sector]);
-	int flag = disable_interrupts ();
-
-	*addr = INTEL_CLEAR;	/* Clear status register    */
-	if (prot) {		/* Set sector lock bit      */
-		*addr = INTEL_LOCKBIT;	/* Sector lock bit          */
-		*addr = INTEL_PROTECT;	/* set                      */
-	} else {		/* Clear sector lock bit    */
-		*addr = INTEL_LOCKBIT;	/* All sectors lock bits    */
-		*addr = INTEL_CONFIRM;	/* clear                    */
-	}
-
-	start = get_timer (0);
-
-	while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
-		if (get_timer (start) > CONFIG_SYS_FLASH_UNLOCK_TOUT) {
-			printf ("Flash lock bit operation timed out\n");
-			rc = 1;
-			break;
-		}
-	}
-
-	if (*addr != INTEL_OK) {
-		printf ("Flash lock bit operation failed at %08X, CSR=%08X\n",
-			(uint) addr, (uint) * addr);
-		rc = 1;
-	}
-
-	if (!rc)
-		info->protect[sector] = prot;
-
-	/*
-	 * Clear lock bit command clears all sectors lock bits, so
-	 * we have to restore lock bits of protected sectors.
-	 */
-	if (!prot) {
-		for (i = 0; i < info->sector_count; i++) {
-			if (info->protect[i]) {
-				start = get_timer (0);
-				addr = (FPWV *) (info->start[i]);
-				*addr = INTEL_LOCKBIT;	/* Sector lock bit  */
-				*addr = INTEL_PROTECT;	/* set              */
-				while ((*addr & INTEL_FINISHED) !=
-				       INTEL_FINISHED) {
-					if (get_timer (start) >
-					    CONFIG_SYS_FLASH_UNLOCK_TOUT) {
-						printf ("Flash lock bit operation timed out\n");
-						rc = 1;
-						break;
-					}
-				}
-			}
-		}
-	}
-
-	if (flag)
-		enable_interrupts ();
-
-	*addr = INTEL_RESET;	/* Reset to read array mode */
-
-	return rc;
-}
-
-
-/*
- * This function gets the u-boot flash sector protection status
- * (flash_info_t.protect[]) in sync with the sector protection
- * status stored in hardware.
- */
-static void flash_sync_real_protect (flash_info_t * info)
-{
-	int i;
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_28F128J3A:
-		for (i = 0; i < info->sector_count; ++i) {
-			info->protect[i] = intel_sector_protected(info, i);
-		}
-		break;
-	default:
-		/* no h/w protect support */
-		break;
-	}
-}
-
-
-/*
- * checks if "sector" in bank "info" is protected. Should work on intel
- * strata flash chips 28FxxxJ3x in 8-bit mode.
- * Returns 1 if sector is protected (or timed-out while trying to read
- * protection status), 0 if it is not.
- */
-static unsigned char intel_sector_protected (flash_info_t *info, ushort sector)
-{
-	FPWV *addr;
-	FPWV *lock_conf_addr;
-	ulong start;
-	unsigned char ret;
-
-	/*
-	 * first, wait for the WSM to be finished. The rationale for
-	 * waiting for the WSM to become idle for at most
-	 * CONFIG_SYS_FLASH_ERASE_TOUT is as follows. The WSM can be busy
-	 * because of: (1) erase, (2) program or (3) lock bit
-	 * configuration. So we just wait for the longest timeout of
-	 * the (1)-(3), i.e. the erase timeout.
-	 */
-
-	/* wait at least 35ns (W12) before issuing Read Status Register */
-	udelay(1);
-	addr = (FPWV *) info->start[sector];
-	*addr = (FPW) INTEL_STATUS;
-
-	start = get_timer (0);
-	while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
-		if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-			*addr = (FPW) INTEL_RESET; /* restore read mode */
-			printf("WSM busy too long, can't get prot status\n");
-			return 1;
-		}
-	}
-
-	/* issue the Read Identifier Codes command */
-	*addr = (FPW) INTEL_READID;
-
-	/* wait at least 35ns (W12) before reading */
-	udelay(1);
-
-	/* Intel example code uses offset of 4 for 8-bit flash */
-	lock_conf_addr = (FPWV *) info->start[sector] + 4;
-	ret = (*lock_conf_addr & (FPW) INTEL_PROTECT) ? 1 : 0;
-
-	/* put flash back in read mode */
-	*addr = (FPW) INTEL_RESET;
-
-	return ret;
-}

board/o2dnt/o2dnt.c

@@ -1,189 +0,0 @@
-/*
- * (C) Copyright 2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <netdev.h>
-
-#define SDRAM_MODE      0x00CD0000
-#define SDRAM_CONTROL   0x504F0000
-#define SDRAM_CONFIG1   0xD2322800
-#define SDRAM_CONFIG2   0x8AD70000
-
-static void sdram_start (int hi_addr)
-{
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
-	/* unlock mode register */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* precharge all banks */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* precharge all banks */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* auto refresh */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* set mode register */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
-	__asm__ volatile ("sync");
-
-	/* normal operation */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
-	__asm__ volatile ("sync");
-}
-
-/*
- * ATTENTION: Although partially referenced initdram does NOT make real use
- *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
- *            is something else than 0x00000000.
- */
-phys_size_t initdram (int board_type)
-{
-	ulong dramsize = 0;
-	ulong dramsize2 = 0;
-	ulong test1, test2;
-
-	/* setup SDRAM chip selects */
-	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
-	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
-	__asm__ volatile ("sync");
-
-	/* setup config registers */
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
-	__asm__ volatile ("sync");
-
-	/* find RAM size using SDRAM CS0 only */
-	sdram_start(0);
-	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	sdram_start(1);
-	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20)) {
-		dramsize = 0;
-	}
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0)
-		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
-	else
-		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
-
-	/* let SDRAM CS1 start right after CS0 */
-	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
-
-	/* find RAM size using SDRAM CS1 only */
-	if (!dramsize)
-		sdram_start(0);
-
-	test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
-
-	if (!dramsize) {
-		sdram_start(1);
-		test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
-	}
-
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize2 = test1;
-	} else {
-		dramsize2 = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize2 < (1 << 20))
-		dramsize2 = 0;
-
-	/* set SDRAM CS1 size according to the amount of RAM found */
-	if (dramsize2 > 0) {
-		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
-			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
-	} else {
-		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
-	}
-
-	return dramsize + dramsize2;
-}
-
-int checkboard (void)
-{
-	puts ("Board: O2DNT\n");
-	return 0;
-}
-
-void flash_preinit(void)
-{
-	/*
-	 * Now, when we are in RAM, enable flash write
-	 * access for detection process.
-	 * Note that CS_BOOT cannot be cleared when
-	 * executing in flash.
-	 */
-	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
-}
-
-void flash_afterinit(ulong size)
-{
-	if (size == 0x800000) { /* adjust mapping */
-		*(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
-			START_REG(CONFIG_SYS_BOOTCS_START | size);
-
-		*(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
-			STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
-	}
-}
-
-#ifdef	CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
-	pci_mpc5xxx_init(&hose);
-}
-#endif
-
-int board_eth_init(bd_t *bis)
-{
-	cpu_eth_init(bis); /* Built in FEC comes first */
-	return pci_eth_init(bis);
-}

boards.cfg

@@ -462,7 +462,6 @@ mcc200_highboot_SDRAM        powerpc     mpc5xxx     mcc200              -
 mcc200_SDRAM                 powerpc     mpc5xxx     mcc200              -              -           mcc200:MCC200_SDRAM
 motionpro                    powerpc     mpc5xxx
 munices                      powerpc     mpc5xxx
-o2dnt                        powerpc     mpc5xxx
 PM520                        powerpc     mpc5xxx     pm520
 PM520_DDR                    powerpc     mpc5xxx     pm520               -              -           PM520:MPC5200_DDR
 PM520_ROMBOOT                powerpc     mpc5xxx     pm520               -              -           PM520:BOOT_ROM

include/configs/o2dnt.h

@@ -1,297 +0,0 @@
-/*
- * (C) Copyright 2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
-#define CONFIG_MPC5200
-#define CONFIG_O2DNT		1	/* ... on O2DNT board */
-
-#define	CONFIG_SYS_TEXT_BASE	0xFF000000	/* boot low for 16 MiB boards */
-
-#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
-
-#define CONFIG_HIGH_BATS	1	/* High BATs supported */
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	5	/* console is on PSC5 */
-#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * PCI Mapping:
- * 0x40000000 - 0x4fffffff - PCI Memory
- * 0x50000000 - 0x50ffffff - PCI IO Space
- */
-#define CONFIG_PCI		1
-#define CONFIG_PCI_PNP		1
-/* #define CONFIG_PCI_SCAN_SHOW	1 */
-#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1
-
-#define CONFIG_PCI_MEM_BUS	0x40000000
-#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE	0x10000000
-
-#define CONFIG_PCI_IO_BUS	0x50000000
-#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE	0x01000000
-
-#define CONFIG_SYS_XLB_PIPELINING	1
-
-#define CONFIG_EEPRO100
-#define CONFIG_SYS_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
-#define CONFIG_NS8382X		1
-
-/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
-
-#define CONFIG_TIMESTAMP	/* Print image info with timestamp */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_PCI
-
-
-#if (CONFIG_SYS_TEXT_BASE == 0xFF000000)		/* Boot low with 16 MB Flash */
-#   define CONFIG_SYS_LOWBOOT		1
-#else
-#   error "CONFIG_SYS_TEXT_BASE must be 0xFF000000"
-#endif
-
-/*
- * Autobooting
- */
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"flash_nfs=run nfsargs addip;"					\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip;"					\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
-	"rootpath=/opt/eldk/ppc_82xx\0"					\
-	"bootfile=/tftpboot/MPC5200/uImage\0"				\
-	""
-
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-/*
- * IPB Bus clocking configuration.
- */
-#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
-
-#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
-/*
- * PCI Bus clocking configuration
- *
- * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
- *  of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
- */
-#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2	/* define for 66MHz speed */
-#endif
-
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
-#define CONFIG_SYS_I2C_MODULE		1	/* Select I2C module #1 or #2 */
-
-#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE		0x7F
-
-/*
- * EEPROM configuration:
- *
- * O2DNT board is equiped with Ramtron FRAM device FM24CL16
- * 16 Kib Ferroelectric Nonvolatile serial RAM memory
- * organized as 2048 x 8 bits and addressable as eight I2C devices
- * 0x50 ... 0x57 each 256 bytes in size
- *
- */
-#define CONFIG_SYS_I2C_FRAM
-#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
-/*
- * There is no write delay with FRAM, write operations are performed at bus
- * speed. Thus, no status polling or write delay is needed.
- */
-/*#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	70*/
-
-
-/*
- * Flash configuration
- */
-#define CONFIG_SYS_FLASH_BASE		0xFF000000
-#define CONFIG_SYS_FLASH_SIZE		0x01000000
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00040000)
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
-#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
-#define CONFIG_SYS_FLASH_PROTECTION		/* "Real" (hardware) sectors protection */
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_SIZE		0x20000
-#define CONFIG_ENV_SECT_SIZE	0x20000
-#define CONFIG_ENV_OVERWRITE	1
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR		0xF0000000
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
-
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */
-
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
-#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC	1
-#define CONFIG_MPC5xxx_FEC_MII100
-/*
- * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
- */
-/* #define CONFIG_MPC5xxx_FEC_MII10 */
-#define CONFIG_PHY_ADDR		0x00
-
-/*
- * GPIO configuration
- */
-/*#define CONFIG_SYS_GPS_PORT_CONFIG	0x10002004 */
-#define CONFIG_SYS_GPS_PORT_CONFIG	0x00002006	/* no CAN */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
-#else
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
-
-#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
-
-#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
-
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL		HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
-
-#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
-/*
- * For 66 MHz PCI clock additional Wait State is needed for CS0 (flash).
- */
-#define CONFIG_SYS_BOOTCS_CFG		0x00057801 /* for pci_clk = 66 MHz */
-#else
-#define CONFIG_SYS_BOOTCS_CFG		0x00047801 /* for pci_clk = 33 MHz */
-#endif
-
-#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
-
-#define CONFIG_SYS_CS_BURST		0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
-
-#define CONFIG_SYS_RESET_ADDRESS	0xff000000
-
-#endif /* __CONFIG_H */