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powerpc/85xx: improve definition of BR_PHYS_ADDR macro

The BR_PHYS_ADDR(x) macro was missing parentheses around "x" in the macro
definition, so callers had to supply their own parenthesis.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Timur Tabi hace 13 años
padre
145dbc0250
commit
7ee411071f
Se han modificado 8 ficheros con 21 adiciones y 23 borrados
Dividir vista Mostrar estadísticas de diff
  1. 3 3
      arch/powerpc/include/asm/fsl_lbc.h
  2. 4 5
      include/configs/MPC8536DS.h
  3. 1 2
      include/configs/MPC8548CDS.h
  4. 4 5
      include/configs/MPC8572DS.h
  5. 1 1
      include/configs/P1022DS.h
  6. 5 4
      include/configs/P2020DS.h
  7. 1 1
      include/configs/corenet_ds.h
  8. 2 2
      include/configs/p1_p2_rdb_pc.h

+ 3 - 3
arch/powerpc/include/asm/fsl_lbc.h
Ver fichero 

@@ -82,10 +82,10 @@ void lbc_sdram_init(void);
 
 
 /* Convert an address into the right format for the BR registers */
 
 #if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_FSL_ELBC)
 
-#define BR_PHYS_ADDR(x)	((unsigned long)((x & 0x0ffff8000ULL) | \
 
-					 ((x & 0x300000000ULL) >> 19)))
 
+#define BR_PHYS_ADDR(x)	\
 
+	((u32)(((x) & 0x0ffff8000ULL) | (((x) & 0x300000000ULL) >> 19)))
 
 #else
 
-#define BR_PHYS_ADDR(x) (x & 0xffff8000)
 
+#define BR_PHYS_ADDR(x) ((u32)(x) & 0xffff8000)
 
 #endif
 
 
 /* OR - Option Registers

+ 4 - 5
include/configs/MPC8536DS.h
Ver fichero 

@@ -217,8 +217,7 @@
 
 #endif
 
 
 #define CONFIG_FLASH_BR_PRELIM \
 
-		(BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \
 
-		 | BR_PS_16 | BR_V)
 
+	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
 
 #define CONFIG_FLASH_OR_PRELIM	0xf8000ff7
 
 
 #define CONFIG_SYS_BR1_PRELIM \
 
@@ -380,14 +379,14 @@
 
 #endif
 
 
 #define CONFIG_SYS_BR4_PRELIM \
 
-		(BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)) \
 
+		(BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
 
 		| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
 
 		| BR_PS_8		/* Port Size = 8 bit */ \
 
 		| BR_MS_FCM		/* MSEL = FCM */ \
 
 		| BR_V)			/* valid */
 
 #define CONFIG_SYS_OR4_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 
 #define CONFIG_SYS_BR5_PRELIM \
 
-		(BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)) \
 
+		(BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \
 
 		| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
 
 		| BR_PS_8		/* Port Size = 8 bit */ \
 
 		| BR_MS_FCM		/* MSEL = FCM */ \
 
@@ -395,7 +394,7 @@
 
 #define CONFIG_SYS_OR5_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 
 
 #define CONFIG_SYS_BR6_PRELIM \
 
-		(BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)) \
 
+		(BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \
 
 		| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
 
 		| BR_PS_8		/* Port Size = 8 bit */ \
 
 		| BR_MS_FCM		/* MSEL = FCM */ \

+ 1 - 2
include/configs/MPC8548CDS.h
Ver fichero 

@@ -189,8 +189,7 @@ extern unsigned long get_clock_freq(void);
 
 #endif
 
 
 #define CONFIG_SYS_BR0_PRELIM \
 
-	(BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x800000)) \
 
-	| BR_PS_16 | BR_V)
 
+	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V)
 
 #define CONFIG_SYS_BR1_PRELIM \
 
 	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)

+ 4 - 5
include/configs/MPC8572DS.h
Ver fichero 

@@ -205,8 +205,7 @@
 
 
 
 #define CONFIG_FLASH_BR_PRELIM \
 
-	(BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \
 
-	| BR_PS_16 | BR_V)
 
+	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
 
 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
 
 
 #define CONFIG_SYS_BR1_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 
@@ -376,20 +375,20 @@
 
 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 
 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 
 #endif
 
-#define CONFIG_SYS_BR4_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
 
+#define CONFIG_SYS_BR4_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
 
 			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 
 			       | BR_PS_8	       /* Port Size = 8 bit */ \
 
 			       | BR_MS_FCM	       /* MSEL = FCM */ \
 
 			       | BR_V)		       /* valid */
 
 #define CONFIG_SYS_OR4_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 
-#define CONFIG_SYS_BR5_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\
 
+#define CONFIG_SYS_BR5_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\
 
 			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 
 			       | BR_PS_8	       /* Port Size = 8 bit */ \
 
 			       | BR_MS_FCM	       /* MSEL = FCM */ \
 
 			       | BR_V)		       /* valid */
 
 #define CONFIG_SYS_OR5_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 
 
-#define CONFIG_SYS_BR6_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\
 
+#define CONFIG_SYS_BR6_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\
 
 			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 
 			       | BR_PS_8	       /* Port Size = 8 bit */ \
 
 			       | BR_MS_FCM	       /* MSEL = FCM */ \

+ 1 - 1
include/configs/P1022DS.h
Ver fichero 

@@ -134,7 +134,7 @@
 
 #endif
 
 
 #define CONFIG_FLASH_BR_PRELIM  \
 
-	(BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
 
+	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
 
 #define CONFIG_FLASH_OR_PRELIM	(OR_AM_128MB | 0xff7)
 
 
 #define CONFIG_SYS_BR0_PRELIM	CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */

+ 5 - 4
include/configs/P2020DS.h
Ver fichero 

@@ -236,7 +236,8 @@
 
 #define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
 
 #endif
 
 
-#define CONFIG_FLASH_BR_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
 
+#define CONFIG_FLASH_BR_PRELIM  \
 
+	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
 
 #define CONFIG_FLASH_OR_PRELIM	0xf8000ff7
 
 
 #define CONFIG_SYS_BR1_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 
@@ -338,20 +339,20 @@
 
 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM  /* NAND Base Address */
 
 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM  /* NAND Options */
 
 
-#define CONFIG_SYS_BR4_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
 
+#define CONFIG_SYS_BR4_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
 
 				| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
 
 				| BR_PS_8		/* Port Size = 8bit */ \
 
 				| BR_MS_FCM		/* MSEL = FCM */ \
 
 				| BR_V)			/* valid */
 
 #define CONFIG_SYS_OR4_PRELIM  CONFIG_SYS_NAND_OR_PRELIM	/* NAND Options */
 
-#define CONFIG_SYS_BR5_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\
 
+#define CONFIG_SYS_BR5_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \
 
 				| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
 
 				| BR_PS_8		/* Port Size = 8bit */ \
 
 				| BR_MS_FCM		/* MSEL = FCM */ \
 
 				| BR_V)			/* valid */
 
 #define CONFIG_SYS_OR5_PRELIM  CONFIG_SYS_NAND_OR_PRELIM	/* NAND Options */
 
 
-#define CONFIG_SYS_BR6_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\
 
+#define CONFIG_SYS_BR6_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \
 
 				| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
 
 				| BR_PS_8		/* Port Size = 8bit */ \
 
 				| BR_MS_FCM		/* MSEL = FCM */ \

+ 1 - 1
include/configs/corenet_ds.h
Ver fichero 

@@ -211,7 +211,7 @@
 
 #endif
 
 
 #define CONFIG_SYS_FLASH_BR_PRELIM \
 
-		(BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \
 
+		(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
 
 		 | BR_PS_16 | BR_V)
 
 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
 
 					| OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)

+ 2 - 2
include/configs/p1_p2_rdb_pc.h
Ver fichero 

@@ -357,7 +357,7 @@
 
 #define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
 
 #endif
 
 
-#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \
 
+#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
 
 	| BR_PS_16 | BR_V)
 
 
 #define CONFIG_FLASH_OR_PRELIM	0xfc000ff7
 
@@ -401,7 +401,7 @@
 
 #define CONFIG_SYS_NAND_U_BOOT_RELOC	0x00010000
 
 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP	(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
 
 
-#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS)) \
 
+#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 
 	| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
 
 	| BR_PS_8	/* Port Size = 8 bit */ \
 
 	| BR_MS_FCM	/* MSEL = FCM */ \