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@@ -0,0 +1,23 @@
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+#ifndef __ASM_NIOS2_DMA_MAPPING_H
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+#define __ASM_NIOS2_DMA_MAPPING_H
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+
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+/* dma_alloc_coherent() return cache-line aligned allocation which is mapped
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+ * to uncached io region.
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+ *
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+ * IO_REGION_BASE should be defined in board config header file
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+ * 0x80000000 for nommu, 0xe0000000 for mmu
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+ */
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+
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+static inline void *dma_alloc_coherent(size_t len, unsigned long *handle)
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+{
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+ void *addr = malloc(len + CONFIG_SYS_DCACHELINE_SIZE);
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+ if (!addr)
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+ return 0;
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+ flush_dcache((unsigned long)addr, len + CONFIG_SYS_DCACHELINE_SIZE);
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+ *handle = ((unsigned long)addr +
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+ (CONFIG_SYS_DCACHELINE_SIZE - 1)) &
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+ ~(CONFIG_SYS_DCACHELINE_SIZE - 1) & ~(IO_REGION_BASE);
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+ return (void *)(*handle | IO_REGION_BASE);
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+}
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+
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+#endif /* __ASM_NIOS2_DMA_MAPPING_H */
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