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@@ -45,11 +45,11 @@ void mx28_power_clock2pll(void)
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struct mx28_clkctrl_regs *clkctrl_regs =
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(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
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- writel(CLKCTRL_PLL0CTRL0_POWER,
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- &clkctrl_regs->hw_clkctrl_pll0ctrl0_set);
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+ setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0,
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+ CLKCTRL_PLL0CTRL0_POWER);
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early_delay(100);
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- writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
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- &clkctrl_regs->hw_clkctrl_clkseq_clr);
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+ setbits_le32(&clkctrl_regs->hw_clkctrl_clkseq,
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+ CLKCTRL_CLKSEQ_BYPASS_CPU);
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}
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void mx28_power_clear_auto_restart(void)
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@@ -455,9 +455,14 @@ void mx28_power_enable_4p2(void)
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mx28_power_init_4p2_regulator();
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/* Shutdown battery (none present) */
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- clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK);
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- writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
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- writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr);
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+ if (!mx28_is_batt_ready()) {
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+ clrbits_le32(&power_regs->hw_power_dcdc4p2,
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+ POWER_DCDC4P2_BO_MASK);
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+ writel(POWER_CTRL_DCDC4P2_BO_IRQ,
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+ &power_regs->hw_power_ctrl_clr);
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+ writel(POWER_CTRL_ENIRQ_DCDC4P2_BO,
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+ &power_regs->hw_power_ctrl_clr);
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+ }
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mx28_power_init_dcdc_4p2_source();
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@@ -515,6 +520,50 @@ void mx28_powerdown(void)
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&power_regs->hw_power_reset);
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}
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+void mx28_batt_boot(void)
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+{
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+ struct mx28_power_regs *power_regs =
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+ (struct mx28_power_regs *)MXS_POWER_BASE;
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+
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+ clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
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+ clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ENABLE_DCDC);
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+
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+ clrbits_le32(&power_regs->hw_power_dcdc4p2,
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+ POWER_DCDC4P2_ENABLE_DCDC | POWER_DCDC4P2_ENABLE_4P2);
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+ writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_clr);
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+
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+ /* 5V to battery handoff. */
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+ setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
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+ early_delay(30);
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+ clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
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+
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+ writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr);
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+
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+ clrsetbits_le32(&power_regs->hw_power_minpwr,
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+ POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
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+
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+ mx28_power_set_linreg();
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+
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+ clrbits_le32(&power_regs->hw_power_vdddctrl,
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+ POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG);
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+
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+ clrbits_le32(&power_regs->hw_power_vddactrl,
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+ POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG);
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+
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+ clrbits_le32(&power_regs->hw_power_vddioctrl,
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+ POWER_VDDIOCTRL_DISABLE_FET);
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+
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+ setbits_le32(&power_regs->hw_power_5vctrl,
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+ POWER_5VCTRL_PWD_CHARGE_4P2_MASK);
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+
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+ setbits_le32(&power_regs->hw_power_5vctrl,
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+ POWER_5VCTRL_ENABLE_DCDC);
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+
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+ clrsetbits_le32(&power_regs->hw_power_5vctrl,
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+ POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
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+ 0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
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+}
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+
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void mx28_handle_5v_conflict(void)
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{
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struct mx28_power_regs *power_regs =
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@@ -539,6 +588,11 @@ void mx28_handle_5v_conflict(void)
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mx28_powerdown();
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break;
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}
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+
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+ if (tmp & POWER_STS_PSWITCH_MASK) {
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+ mx28_batt_boot();
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+ break;
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+ }
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}
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}
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@@ -595,12 +649,42 @@ void mx28_switch_vddd_to_dcdc_source(void)
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void mx28_power_configure_power_source(void)
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{
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+ int batt_ready, batt_good;
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+ struct mx28_power_regs *power_regs =
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+ (struct mx28_power_regs *)MXS_POWER_BASE;
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+ struct mx28_lradc_regs *lradc_regs =
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+ (struct mx28_lradc_regs *)MXS_LRADC_BASE;
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+
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mx28_src_power_init();
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- mx28_5v_boot();
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+ batt_ready = mx28_is_batt_ready();
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+
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+ if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
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+ batt_good = mx28_is_batt_good();
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+ if (batt_ready) {
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+ /* 5V source detected, good battery detected. */
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+ mx28_batt_boot();
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+ } else {
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+ if (batt_good) {
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+ /* 5V source detected, low battery detceted. */
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+ } else {
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+ /* 5V source detected, bad battery detected. */
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+ writel(LRADC_CONVERSION_AUTOMATIC,
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+ &lradc_regs->hw_lradc_conversion_clr);
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+ clrbits_le32(&power_regs->hw_power_battmonitor,
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+ POWER_BATTMONITOR_BATT_VAL_MASK);
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+ }
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+ mx28_5v_boot();
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+ }
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+ } else {
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+ /* 5V not detected, booting from battery. */
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+ mx28_batt_boot();
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+ }
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+
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mx28_power_clock2pll();
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mx28_init_batt_bo();
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+
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mx28_switch_vddd_to_dcdc_source();
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}
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