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@@ -167,6 +167,7 @@
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* set up. While still running from cache, I experienced problems accessing
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* the NAND controller. sr - 2006-08-25
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*/
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+#if defined (CONFIG_NAND_U_BOOT)
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#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
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#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
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#define CFG_NAND_BOOT_SPL_DST (CFG_OCM_BASE + (12 << 10)) /* Copy SPL here */
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@@ -195,6 +196,7 @@
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#define CFG_NAND_OOBSIZE 16
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#define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
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#define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
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+#endif
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#ifdef CFG_ENV_IS_IN_NAND
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/*
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@@ -501,6 +503,7 @@
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#define NAND_MAX_CHIPS 1
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#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS)
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#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
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+#define CFG_NAND_QUIET_TEST 1
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/*
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* Internal Definitions
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