Merge branch 'master' of git://git.denx.de/u-boot-sh

* 'master' of git://git.denx.de/u-boot-sh:
  sh: tmu: Removed arch/sh/include/asm/clk.h
  sh: tmu: Changed switch statement to shift operation
  sh: tmu: Changed TMU driver using array of structures

Signed-off-by: Wolfgang Denk <wd@denx.de>

arch/sh/include/asm/clk.h

@@ -1,35 +0,0 @@
-/*
- * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef __ASM_SH_CLK_H__
-#define __ASM_SH_CLK_H__
-
-static inline unsigned long get_peripheral_clk_rate(void)
-{
-	return CONFIG_SYS_CLK_FREQ;
-}
-
-static inline unsigned long get_tmu0_clk_rate(void)
-{
-	return CONFIG_SYS_CLK_FREQ;
-}
-
-#endif /* __ASM_SH_CLK_H__ */

arch/sh/include/asm/cpu_sh7706.h

@@ -41,10 +41,7 @@
 #define SCIF0_BASE	SCSMR_2
 
 /* Timer */
-#define TSTR0		0xFFFFFE92
-#define TSTR		TSTR0
-#define TCNT0		0xFFFFFE98
-#define TCR0		0xFFFFFE9C
+#define TMU_BASE	0xFFFFFE90
 
 /* On chip oscillator circuits */
 #define	WTCNT	0xFFFFFF84

arch/sh/include/asm/cpu_sh7710.h

@@ -51,10 +51,7 @@
 #define SCIF1_BASE	SCSMR_1
 
 /* Timer */
-#define TSTR0		0xA412FE92
-#define TSTR		TSTR0
-#define TCNT0		0xa412FE98
-#define TCR0		0xa412FE9C
+#define TMU_BASE	0xA412FE90
 
 /* On chip oscillator circuits */
 #define FRQCR		0xA415FF80

arch/sh/include/asm/cpu_sh7720.h

@@ -105,16 +105,6 @@
 
 /*	TMU	*/
 #define TMU_BASE	0xA412FE90
-#define TSTR		(TMU_BASE + 0x02)
-#define TCOR0		(TMU_BASE + 0x04)
-#define TCNT0		(TMU_BASE + 0x08)
-#define TCR0		(TMU_BASE + 0x0C)
-#define TCOR1		(TMU_BASE + 0x10)
-#define TCNT1		(TMU_BASE + 0x14)
-#define TCR1		(TMU_BASE + 0x18)
-#define TCOR2		(TMU_BASE + 0x1C)
-#define TCNT2		(TMU_BASE + 0x20)
-#define TCR2		(TMU_BASE + 0x24)
 
 /*	TPU	*/
 #define TPU_BASE	0xA4480000

arch/sh/include/asm/cpu_sh7722.h

@@ -226,16 +226,7 @@
 
 
 /*	TMU	*/
-#define TSTR        0xFFD80004
-#define TCOR0       0xFFD80008
-#define TCNT0       0xFFD8000C
-#define TCR0        0xFFD80010
-#define TCOR1       0xFFD80014
-#define TCNT1       0xFFD80018
-#define TCR1        0xFFD8001C
-#define TCOR2       0xFFD80020
-#define TCNT2       0xFFD80024
-#define TCR2        0xFFD80028
+#define TMU_BASE	0xFFD80000
 
 /*	TPU	*/
 #define TPU_TSTR    0xA4C90000

arch/sh/include/asm/cpu_sh7723.h

@@ -95,16 +95,7 @@
 #define WTCNT		RWTCNT
 
 /* TMU */
-#define TSTR        0xFFD80004
-#define TCOR0       0xFFD80008
-#define TCNT0       0xFFD8000C
-#define TCR0        0xFFD80010
-#define TCOR1       0xFFD80014
-#define TCNT1       0xFFD80018
-#define TCR1        0xFFD8001C
-#define TCOR2       0xFFD80020
-#define TCNT2       0xFFD80024
-#define TCR2        0xFFD80028
+#define TMU_BASE	0xFFD80000
 
 /* TPU */
 

arch/sh/include/asm/cpu_sh7724.h

@@ -116,16 +116,7 @@
 #define WTCNT		RWTCNT
 
 /* TMU */
-#define TSTR        0xFFD80004
-#define TCOR0       0xFFD80008
-#define TCNT0       0xFFD8000C
-#define TCR0        0xFFD80010
-#define TCOR1       0xFFD80014
-#define TCNT1       0xFFD80018
-#define TCR1        0xFFD8001C
-#define TCOR2       0xFFD80020
-#define TCNT2       0xFFD80024
-#define TCR2        0xFFD80028
+#define TMU_BASE	0xFFD80000
 
 /* TPU */
 

arch/sh/include/asm/cpu_sh7734.h

@@ -36,9 +36,7 @@
 #define SCIF5_BASE  0xFFE45000
 
 /* Timer */
-#define TSTR	0xFFD80004
-#define TCNT0	0xFFD8000C
-#define TCR0	0xFFD80010
+#define TMU_BASE 0xFFD80000
 
 /* PFC */
 #define PMMR    (0xFFFC0000)

arch/sh/include/asm/cpu_sh7750.h

@@ -143,26 +143,7 @@
 #define CLKSTPCLR	0xFE0A0008
 
 /*      TMU     */
-#define TSTR2	0xFE100004
-#define TCOR3	0xFE100008
-#define TCNT3	0xFE10000C
-#define TCR3	0xFE100010
-#define TCOR4	0xFE100014
-#define TCNT4	0xFE100018
-#define TCR4	0xFE10001C
-#define TOCR	0xFFD80000
-#define TSTR0	0xFFD80004
-#define TCOR0	0xFFD80008
-#define TCNT0	0xFFD8000C
-#define TCR0	0xFFD80010
-#define TCOR1	0xFFD80014
-#define TCNT1	0xFFD80018
-#define TCR1	0xFFD8001C
-#define TCOR2	0xFFD80020
-#define TCNT2	0xFFD80024
-#define TCR2	0xFFD80028
-#define TCPR2	0xFFD8002C
-#define TSTR	TSTR0
+#define TMU_BASE	0xFFD80000
 
 /*      SCI     */
 #define SCSMR1	0xFFE00000

arch/sh/include/asm/cpu_sh7757.h

@@ -51,19 +51,7 @@ struct mmu_regs {
 #define SMR0		0xfe470000
 
 /* TMU0 */
-#define TSTR		0xFE430004
-#define TOCR		0xFE430000
-#define TSTR0		0xFE430004
-#define TCOR0		0xFE430008
-#define TCNT0		0xFE43000C
-#define TCR0		0xFE430010
-#define TCOR1		0xFE430014
-#define TCNT1		0xFE430018
-#define TCR1		0xFE43001C
-#define TCOR2		0xFE430020
-#define TCNT2		0xFE430024
-#define TCR2		0xFE430028
-#define TCPR2		0xFE43002C
+#define TMU_BASE    0xFE430000
 
 /* ETHER, GETHER MAC address */
 struct ether_mac_regs {

arch/sh/include/asm/cpu_sh7763.h

@@ -43,9 +43,6 @@
 #define WDTST		0xFFCC0000
 
 /* TMU */
-#define TSTR		0xFFD80004
-#define TCOR0		0xFFD80008
-#define TCNT0		0xFFD8000C
-#define TCR0		0xFFD80010
+#define TMU_BASE	0xFFD80000
 
 #endif /* _ASM_CPU_SH7763_H_ */

arch/sh/include/asm/cpu_sh7780.h

@@ -272,29 +272,7 @@
 #define	MSTPCR	0xFFC80030
 
 /* Timer Unit */
-#define	TSTR	TSTR0
-#define	TOCR	0xFFD80000
-#define	TSTR0	0xFFD80004
-#define	TCOR0	0xFFD80008
-#define	TCNT0	0xFFD8000C
-#define	TCR0	0xFFD80010
-#define	TCOR1	0xFFD80014
-#define	TCNT1	0xFFD80018
-#define	TCR1	0xFFD8001C
-#define	TCOR2	0xFFD80020
-#define	TCNT2	0xFFD80024
-#define	TCR2	0xFFD80028
-#define	TCPR2	0xFFD8002C
-#define	TSTR1	0xFFDC0004
-#define	TCOR3	0xFFDC0008
-#define	TCNT3	0xFFDC000C
-#define	TCR3	0xFFDC0010
-#define	TCOR4	0xFFDC0014
-#define	TCNT4	0xFFDC0018
-#define	TCR4	0xFFDC001C
-#define	TCOR5	0xFFDC0020
-#define	TCNT5	0xFFDC0024
-#define	TCR5	0xFFDC0028
+#define TMU_BASE    0xFFD80000
 
 /* Timer/Counter */
 #define	CMTCFG	0xFFE30000

arch/sh/include/asm/cpu_sh7785.h

@@ -46,29 +46,7 @@
 #define	WDTBCNT	0xFFCC0018
 
 /* Timer Unit */
-#define	TSTR	TSTR0
-#define	TOCR	0xFFD80000
-#define	TSTR0	0xFFD80004
-#define	TCOR0	0xFFD80008
-#define	TCNT0	0xFFD8000C
-#define	TCR0	0xFFD80010
-#define	TCOR1	0xFFD80014
-#define	TCNT1	0xFFD80018
-#define	TCR1	0xFFD8001C
-#define	TCOR2	0xFFD80020
-#define	TCNT2	0xFFD80024
-#define	TCR2	0xFFD80028
-#define	TCPR2	0xFFD8002C
-#define	TSTR1	0xFFDC0004
-#define	TCOR3	0xFFDC0008
-#define	TCNT3	0xFFDC000C
-#define	TCR3	0xFFDC0010
-#define	TCOR4	0xFFDC0014
-#define	TCNT4	0xFFDC0018
-#define	TCR4	0xFFDC001C
-#define	TCOR5	0xFFDC0020
-#define	TCNT5	0xFFDC0024
-#define	TCR5	0xFFDC0028
+#define TMU_BASE	0xFFD80000
 
 /* Serial Communication	Interface with FIFO */
 #define	SCIF1_BASE	0xffeb0000

arch/sh/lib/time.c

@@ -2,7 +2,7 @@
  * (C) Copyright 2009
  * Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  *
- * (C) Copyright 2007-2010
+ * (C) Copyright 2007-2012
  * Nobobuhiro Iwamatsu <iwamatsu@nigauri.org>
  *
  * (C) Copyright 2003
@@ -30,71 +30,54 @@
 #include <common.h>
 #include <div64.h>
 #include <asm/processor.h>
-#include <asm/clk.h>
 #include <asm/io.h>
+#include <sh_tmu.h>
 
-#define TMU_MAX_COUNTER (~0UL)
+static struct tmu_regs *tmu = (struct tmu_regs *)TMU_BASE;
 
-static ulong timer_freq;
+static u16 bit;
 static unsigned long last_tcnt;
 static unsigned long long overflow_ticks;
 
+unsigned long get_tbclk(void)
+{
+	return get_tmu0_clk_rate() >> ((bit + 1) * 2);
+}
+
 static inline unsigned long long tick_to_time(unsigned long long tick)
 {
 	tick *= CONFIG_SYS_HZ;
-	do_div(tick, timer_freq);
+	do_div(tick, get_tbclk());
 
 	return tick;
 }
 
 static inline unsigned long long usec_to_tick(unsigned long long usec)
 {
-	usec *= timer_freq;
+	usec *= get_tbclk();
 	do_div(usec, 1000000);
 
 	return usec;
 }
 
-static void tmu_timer_start (unsigned int timer)
+static void tmu_timer_start(unsigned int timer)
 {
 	if (timer > 2)
 		return;
-	writeb(readb(TSTR) | (1 << timer), TSTR);
+	writeb(readb(&tmu->tstr) | (1 << timer), &tmu->tstr);
 }
 
-static void tmu_timer_stop (unsigned int timer)
+static void tmu_timer_stop(unsigned int timer)
 {
 	if (timer > 2)
 		return;
-	writeb(readb(TSTR) & ~(1 << timer), TSTR);
+	writeb(readb(&tmu->tstr) & ~(1 << timer), &tmu->tstr);
 }
 
-int timer_init (void)
+int timer_init(void)
 {
-	/* Divide clock by CONFIG_SYS_TMU_CLK_DIV */
-	u16 bit = 0;
-
-	switch (CONFIG_SYS_TMU_CLK_DIV) {
-	case 1024:
-		bit = 4;
-		break;
-	case 256:
-		bit = 3;
-		break;
-	case 64:
-		bit = 2;
-		break;
-	case 16:
-		bit = 1;
-		break;
-	case 4:
-	default:
-		break;
-	}
-	writew(readw(TCR0) | bit, TCR0);
-
-	/* Calc clock rate */
-	timer_freq = get_tmu0_clk_rate() >> ((bit + 1) * 2);
+	bit = (ffs(CONFIG_SYS_TMU_CLK_DIV) >> 1) - 1;
+	writew(readw(&tmu->tcr0) | bit, &tmu->tcr0);
 
 	tmu_timer_stop(0);
 	tmu_timer_start(0);
@@ -105,9 +88,9 @@ int timer_init (void)
 	return 0;
 }
 
-unsigned long long get_ticks (void)
+unsigned long long get_ticks(void)
 {
-	unsigned long tcnt = 0 - readl(TCNT0);
+	unsigned long tcnt = 0 - readl(&tmu->tcnt0);
 
 	if (last_tcnt > tcnt) /* overflow */
 		overflow_ticks++;
@@ -116,7 +99,7 @@ unsigned long long get_ticks (void)
 	return (overflow_ticks << 32) | tcnt;
 }
 
-void __udelay (unsigned long usec)
+void __udelay(unsigned long usec)
 {
 	unsigned long long tmp;
 	ulong tmo;
@@ -128,13 +111,20 @@ void __udelay (unsigned long usec)
 		 /*NOP*/;
 }
 
-unsigned long get_timer (unsigned long base)
+unsigned long get_timer(unsigned long base)
 {
 	/* return msec */
 	return tick_to_time(get_ticks()) - base;
 }
 
-unsigned long get_tbclk (void)
+void set_timer(unsigned long t)
+{
+	writel((0 - t), &tmu->tcnt0);
+}
+
+void reset_timer(void)
 {
-	return timer_freq;
+	tmu_timer_stop(0);
+	set_timer(0);
+	tmu_timer_start(0);
 }

include/sh_tmu.h

@@ -0,0 +1,75 @@
+/*
+ * Copyright (C) 2012  Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __SH_TMU_H
+#define __SH_TMU_H
+
+#include <asm/types.h>
+
+#if defined(CONFIG_SH3)
+struct tmu_regs {
+	u8	tocr;
+	u8	reserved0;
+	u8	tstr;
+	u8	reserved1;
+	u32	tcor0;
+	u32	tcnt0;
+	u16	tcr0;
+	u16	reserved2;
+	u32	tcor1;
+	u32	tcnt1;
+	u16	tcr1;
+	u16	reserved3;
+	u32	tcor2;
+	u32	tcnt2;
+	u16	tcr2;
+	u16	reserved4;
+	u32	tcpr2;
+};
+#endif /* CONFIG_SH3 */
+
+#if defined(CONFIG_SH4) || defined(CONFIG_SH4A)
+struct tmu_regs {
+	u32 reserved;
+	u8  tstr;
+	u8  reserved2[3];
+	u32 tcor0;
+	u32 tcnt0;
+	u16 tcr0;
+	u16 reserved3;
+	u32 tcor1;
+	u32 tcnt1;
+	u16 tcr1;
+	u16 reserved4;
+	u32 tcor2;
+	u32 tcnt2;
+	u16 tcr2;
+	u16 reserved5;
+};
+#endif /* CONFIG_SH4 */
+
+static inline unsigned long get_tmu0_clk_rate(void)
+{
+	return CONFIG_SYS_CLK_FREQ;
+}
+
+#endif	/* __SH_TMU_H */