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@@ -246,7 +246,7 @@ static void enable_per_clocks(void)
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;
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}
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-static void mpu_pll_config(void)
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+void mpu_pll_config_val(int mpull_m)
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{
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u32 clkmode, clksel, div_m2;
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@@ -260,7 +260,7 @@ static void mpu_pll_config(void)
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;
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clksel = clksel & (~CLK_SEL_MASK);
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- clksel = clksel | ((MPUPLL_M << CLK_SEL_SHIFT) | MPUPLL_N);
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+ clksel = clksel | ((mpull_m << CLK_SEL_SHIFT) | MPUPLL_N);
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writel(clksel, &cmwkup->clkseldpllmpu);
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div_m2 = div_m2 & ~CLK_DIV_MASK;
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@@ -274,6 +274,11 @@ static void mpu_pll_config(void)
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;
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}
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+static void mpu_pll_config(void)
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+{
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+ mpu_pll_config_val(CONFIG_SYS_MPUCLK);
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+}
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+
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static void core_pll_config(void)
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{
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u32 clkmode, clksel, div_m4, div_m5, div_m6;
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