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@@ -27,17 +27,13 @@
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#include <configs/omap1510.h>
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#include <configs/omap1510.h>
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-/*
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- * High Level Configuration Options
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- * (easy to change)
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- */
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#define CONFIG_ARM925T 1 /* This is an arm925t CPU */
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#define CONFIG_ARM925T 1 /* This is an arm925t CPU */
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#define CONFIG_OMAP 1 /* in a TI OMAP core */
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#define CONFIG_OMAP 1 /* in a TI OMAP core */
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#define CONFIG_OMAP1510 1 /* which is in a 5910 */
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#define CONFIG_OMAP1510 1 /* which is in a 5910 */
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/* Input clock of PLL */
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/* Input clock of PLL */
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-#define CONFIG_SYS_CLK_FREQ 150000000 /* 150MHz input clock */
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-#define CONFIG_XTAL_FREQ 12000000
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+#define CONFIG_SYS_CLK_FREQ 150000000 /* 150MHz */
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+#define CONFIG_XTAL_FREQ 12000000 /* 12MHz */
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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@@ -54,10 +50,10 @@
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/*
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/*
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* Physical Memory Map
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* Physical Memory Map
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*/
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*/
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-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
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-#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
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-#define PHYS_SDRAM_1_SIZE (64 * 1024 * 1024)
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-#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
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+#define CONFIG_NR_DRAM_BANKS 1
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+#define PHYS_SDRAM_1 0x10000000
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+#define PHYS_SDRAM_1_SIZE (64 * 1024 * 1024)
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+#define PHYS_FLASH_1 0x00000000
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#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
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#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
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@@ -66,23 +62,23 @@
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* Environment settings
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* Environment settings
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*/
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*/
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_IS_IN_FLASH
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-#define CONFIG_ENV_ADDR 0x4000
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-#define CONFIG_ENV_SIZE (8 * 1024)
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-#define CONFIG_ENV_SECT_SIZE (8 * 1024)
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-#define CONFIG_ENV_ADDR_REDUND 0x6000
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-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
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+#define CONFIG_ENV_ADDR 0x4000
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+#define CONFIG_ENV_SIZE (8 * 1024)
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+#define CONFIG_ENV_SECT_SIZE (8 * 1024)
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+#define CONFIG_ENV_ADDR_REDUND 0x6000
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+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_ENV_OVERWRITE
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/*
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/*
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* Size of malloc() pool
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* Size of malloc() pool
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*/
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*/
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-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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+#define CONFIG_SYS_GBL_DATA_SIZE 128
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#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
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/*
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/*
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* The stack size is set up in start.S using the settings below
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* The stack size is set up in start.S using the settings below
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*/
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*/
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-#define CONFIG_STACKSIZE (1 * 1024 * 1024) /* regular stack */
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+#define CONFIG_STACKSIZE (1 * 1024 * 1024)
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/*
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/*
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* Hardware drivers
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* Hardware drivers
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@@ -90,8 +86,8 @@
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE (-4)
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#define CONFIG_SYS_NS16550_REG_SIZE (-4)
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-#define CONFIG_SYS_NS16550_CLK (CONFIG_XTAL_FREQ) /* can be 12M/32Khz or 48Mhz */
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-#define CONFIG_SYS_NS16550_COM1 OMAP1510_UART1_BASE /* uart1 */
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+#define CONFIG_SYS_NS16550_CLK (CONFIG_XTAL_FREQ)
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+#define CONFIG_SYS_NS16550_COM1 OMAP1510_UART1_BASE
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#define CONFIG_NET_MULTI
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#define CONFIG_NET_MULTI
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#define CONFIG_SMC91111
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#define CONFIG_SMC91111
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@@ -128,10 +124,10 @@
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/*#define CONFIG_SKIP_LOWLEVEL_INIT */
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/*#define CONFIG_SKIP_LOWLEVEL_INIT */
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/*
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/*
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- * partitions (mtdparts command line support)
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+ * Partitions (mtdparts command line support)
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*/
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*/
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#define CONFIG_CMD_MTDPARTS
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#define CONFIG_CMD_MTDPARTS
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-#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
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+#define CONFIG_MTD_DEVICE
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#define CONFIG_FLASH_CFI_MTD
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#define CONFIG_FLASH_CFI_MTD
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#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=gen_nand.0"
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#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=gen_nand.0"
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#define MTDPARTS_DEFAULT "mtdparts=" \
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#define MTDPARTS_DEFAULT "mtdparts=" \
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@@ -139,7 +135,7 @@
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"gen_nand.0:4M(kernel0),40M(rootfs0),4M(kernel1),40M(rootfs1),-(data)"
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"gen_nand.0:4M(kernel0),40M(rootfs0),4M(kernel1),40M(rootfs1),-(data)"
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/*
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/*
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- * Command line configuration.
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+ * Command line configuration
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*/
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*/
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#define CONFIG_CMD_BDI
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#define CONFIG_CMD_BDI
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#define CONFIG_CMD_BOOTD
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#define CONFIG_CMD_BOOTD
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@@ -204,12 +200,13 @@
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/*
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/*
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* Miscellaneous configurable options
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* Miscellaneous configurable options
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*/
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*/
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-#define CONFIG_SYS_LONGHELP /* undef to save memory */
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-#define CONFIG_SYS_PROMPT "# " /* Monitor Command Prompt */
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-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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+#define CONFIG_SYS_LONGHELP
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+#define CONFIG_SYS_PROMPT "# "
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+#define CONFIG_SYS_CBSIZE 256
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+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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+ sizeof(CONFIG_SYS_PROMPT) + 16)
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+#define CONFIG_SYS_MAXARGS 16
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+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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@@ -217,9 +214,9 @@
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#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
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#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
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#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE - \
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#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE - \
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- (CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_MALLOC_LEN + CONFIG_STACKSIZE)
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+ (CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_MALLOC_LEN + CONFIG_STACKSIZE)
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-#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1 + 0x400000 /* default load address */
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+#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x400000)
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/* The 1510 has 3 timers, they can be driven by the RefClk (12MHz) or by DPLL1.
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/* The 1510 has 3 timers, they can be driven by the RefClk (12MHz) or by DPLL1.
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* This time is further subdivided by a local divisor.
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* This time is further subdivided by a local divisor.
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@@ -228,9 +225,9 @@
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#define CONFIG_SYS_PTV 7
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#define CONFIG_SYS_PTV 7
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_SYS_HZ 1000
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-#define OMAP5910_DPLL_DIV 1
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-#define OMAP5910_DPLL_MUL ((CONFIG_SYS_CLK_FREQ * \
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- (1 << OMAP5910_DPLL_DIV)) / CONFIG_XTAL_FREQ)
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+#define OMAP5910_DPLL_DIV 1
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+#define OMAP5910_DPLL_MUL \
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+ ((CONFIG_SYS_CLK_FREQ * (1 << OMAP5910_DPLL_DIV)) / CONFIG_XTAL_FREQ)
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#define OMAP5910_ARM_PER_DIV 2 /* CKL/4 */
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#define OMAP5910_ARM_PER_DIV 2 /* CKL/4 */
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#define OMAP5910_LCD_DIV 2 /* CKL/4 */
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#define OMAP5910_LCD_DIV 2 /* CKL/4 */
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@@ -240,7 +237,7 @@
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#define OMAP5910_DSP_MMU_DIV 1 /* CKL/2 */
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#define OMAP5910_DSP_MMU_DIV 1 /* CKL/2 */
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#define OMAP5910_ARM_TIM_SEL 1 /* CKL used for MPU timers */
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#define OMAP5910_ARM_TIM_SEL 1 /* CKL used for MPU timers */
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-#define OMAP5910_ARM_EN_CLK 0x03d6 /* 0000 0011 1101 0110b Clock Enable */
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+#define OMAP5910_ARM_EN_CLK 0x03d6 /* 0000 0011 1101 0110b */
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#define OMAP5910_ARM_CKCTL ((OMAP5910_ARM_PER_DIV) | \
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#define OMAP5910_ARM_CKCTL ((OMAP5910_ARM_PER_DIV) | \
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(OMAP5910_LCD_DIV << 2) | \
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(OMAP5910_LCD_DIV << 2) | \
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(OMAP5910_ARM_DIV << 4) | \
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(OMAP5910_ARM_DIV << 4) | \
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